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  59. <p>
  60. Next: <a href="Sparc_002dAligned_002dData.html#Sparc_002dAligned_002dData" accesskey="n" rel="next">Sparc-Aligned-Data</a>, Up: <a href="Sparc_002dDependent.html#Sparc_002dDependent" accesskey="u" rel="up">Sparc-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  62. <hr>
  63. <a name="Options-24"></a>
  64. <h4 class="subsection">9.44.1 Options</h4>
  65. <a name="index-options-for-SPARC"></a>
  66. <a name="index-SPARC-options"></a>
  67. <a name="index-architectures_002c-SPARC"></a>
  68. <a name="index-SPARC-architectures"></a>
  69. <p>The SPARC chip family includes several successive versions, using the same
  70. core instruction set, but including a few additional instructions at
  71. each version. There are exceptions to this however. For details on what
  72. instructions each variant supports, please see the chip&rsquo;s architecture
  73. reference manual.
  74. </p>
  75. <p>By default, <code>as</code> assumes the core instruction set (SPARC
  76. v6), but &ldquo;bumps&rdquo; the architecture level as needed: it switches to
  77. successively higher architectures as it encounters instructions that
  78. only exist in the higher levels.
  79. </p>
  80. <p>If not configured for SPARC v9 (<code>sparc64-*-*</code>) GAS will not bump
  81. past sparclite by default, an option must be passed to enable the
  82. v9 instructions.
  83. </p>
  84. <p>GAS treats sparclite as being compatible with v8, unless an architecture
  85. is explicitly requested. SPARC v9 is always incompatible with sparclite.
  86. </p>
  87. <dl compact="compact">
  88. <dd><a name="index-_002dAv6"></a>
  89. <a name="index-_002dAv7"></a>
  90. <a name="index-_002dAv8"></a>
  91. <a name="index-_002dAleon"></a>
  92. <a name="index-_002dAsparclet"></a>
  93. <a name="index-_002dAsparclite"></a>
  94. <a name="index-_002dAv9"></a>
  95. <a name="index-_002dAv9a"></a>
  96. <a name="index-_002dAv9b"></a>
  97. <a name="index-_002dAv9c"></a>
  98. <a name="index-_002dAv9d"></a>
  99. <a name="index-_002dAv9e"></a>
  100. <a name="index-_002dAv9v"></a>
  101. <a name="index-_002dAv9m"></a>
  102. <a name="index-_002dAsparc"></a>
  103. <a name="index-_002dAsparcvis"></a>
  104. <a name="index-_002dAsparcvis2"></a>
  105. <a name="index-_002dAsparcfmaf"></a>
  106. <a name="index-_002dAsparcima"></a>
  107. <a name="index-_002dAsparcvis3"></a>
  108. <a name="index-_002dAsparcvis3r"></a>
  109. </dd>
  110. <dt><code>-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite</code></dt>
  111. <dt><code>-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |</code></dt>
  112. <dt><code>-Av8plusv | -Av8plusm | -Av8plusm8</code></dt>
  113. <dt><code>-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8</code></dt>
  114. <dt><code>-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima</code></dt>
  115. <dt><code>-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6</code></dt>
  116. <dd><p>Use one of the &lsquo;<samp>-A</samp>&rsquo; options to select one of the SPARC
  117. architectures explicitly. If you select an architecture explicitly,
  118. <code>as</code> reports a fatal error if it encounters an instruction
  119. or feature requiring an incompatible or higher level.
  120. </p>
  121. <p>&lsquo;<samp>-Av8plus</samp>&rsquo;, &lsquo;<samp>-Av8plusa</samp>&rsquo;, &lsquo;<samp>-Av8plusb</samp>&rsquo;, &lsquo;<samp>-Av8plusc</samp>&rsquo;,
  122. &lsquo;<samp>-Av8plusd</samp>&rsquo;, and &lsquo;<samp>-Av8plusv</samp>&rsquo; select a 32 bit environment.
  123. </p>
  124. <p>&lsquo;<samp>-Av9</samp>&rsquo;, &lsquo;<samp>-Av9a</samp>&rsquo;, &lsquo;<samp>-Av9b</samp>&rsquo;, &lsquo;<samp>-Av9c</samp>&rsquo;, &lsquo;<samp>-Av9d</samp>&rsquo;,
  125. &lsquo;<samp>-Av9e</samp>&rsquo;, &lsquo;<samp>-Av9v</samp>&rsquo; and &lsquo;<samp>-Av9m</samp>&rsquo; select a 64 bit
  126. environment and are not available unless GAS is explicitly configured
  127. with 64 bit environment support.
  128. </p>
  129. <p>&lsquo;<samp>-Av8plusa</samp>&rsquo; and &lsquo;<samp>-Av9a</samp>&rsquo; enable the SPARC V9 instruction set with
  130. UltraSPARC VIS 1.0 extensions.
  131. </p>
  132. <p>&lsquo;<samp>-Av8plusb</samp>&rsquo; and &lsquo;<samp>-Av9b</samp>&rsquo; enable the UltraSPARC VIS 2.0 instructions,
  133. as well as the instructions enabled by &lsquo;<samp>-Av8plusa</samp>&rsquo; and &lsquo;<samp>-Av9a</samp>&rsquo;.
  134. </p>
  135. <p>&lsquo;<samp>-Av8plusc</samp>&rsquo; and &lsquo;<samp>-Av9c</samp>&rsquo; enable the UltraSPARC Niagara instructions,
  136. as well as the instructions enabled by &lsquo;<samp>-Av8plusb</samp>&rsquo; and &lsquo;<samp>-Av9b</samp>&rsquo;.
  137. </p>
  138. <p>&lsquo;<samp>-Av8plusd</samp>&rsquo; and &lsquo;<samp>-Av9d</samp>&rsquo; enable the floating point fused
  139. multiply-add, VIS 3.0, and HPC extension instructions, as well as the
  140. instructions enabled by &lsquo;<samp>-Av8plusc</samp>&rsquo; and &lsquo;<samp>-Av9c</samp>&rsquo;.
  141. </p>
  142. <p>&lsquo;<samp>-Av8pluse</samp>&rsquo; and &lsquo;<samp>-Av9e</samp>&rsquo; enable the cryptographic
  143. instructions, as well as the instructions enabled by &lsquo;<samp>-Av8plusd</samp>&rsquo;
  144. and &lsquo;<samp>-Av9d</samp>&rsquo;.
  145. </p>
  146. <p>&lsquo;<samp>-Av8plusv</samp>&rsquo; and &lsquo;<samp>-Av9v</samp>&rsquo; enable floating point unfused
  147. multiply-add, and integer multiply-add, as well as the instructions
  148. enabled by &lsquo;<samp>-Av8pluse</samp>&rsquo; and &lsquo;<samp>-Av9e</samp>&rsquo;.
  149. </p>
  150. <p>&lsquo;<samp>-Av8plusm</samp>&rsquo; and &lsquo;<samp>-Av9m</samp>&rsquo; enable the VIS 4.0, subtract extended,
  151. xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
  152. enabled by &lsquo;<samp>-Av8plusv</samp>&rsquo; and &lsquo;<samp>-Av9v</samp>&rsquo;.
  153. </p>
  154. <p>&lsquo;<samp>-Av8plusm8</samp>&rsquo; and &lsquo;<samp>-Av9m8</samp>&rsquo; enable the instructions introduced
  155. in the Oracle SPARC Architecture 2017 and the M8 processor, as
  156. well as the instructions enabled by &lsquo;<samp>-Av8plusm</samp>&rsquo; and &lsquo;<samp>-Av9m</samp>&rsquo;.
  157. </p>
  158. <p>&lsquo;<samp>-Asparc</samp>&rsquo; specifies a v9 environment. It is equivalent to
  159. &lsquo;<samp>-Av9</samp>&rsquo; if the word size is 64-bit, and &lsquo;<samp>-Av8plus</samp>&rsquo; otherwise.
  160. </p>
  161. <p>&lsquo;<samp>-Asparcvis</samp>&rsquo; specifies a v9a environment. It is equivalent to
  162. &lsquo;<samp>-Av9a</samp>&rsquo; if the word size is 64-bit, and &lsquo;<samp>-Av8plusa</samp>&rsquo; otherwise.
  163. </p>
  164. <p>&lsquo;<samp>-Asparcvis2</samp>&rsquo; specifies a v9b environment. It is equivalent to
  165. &lsquo;<samp>-Av9b</samp>&rsquo; if the word size is 64-bit, and &lsquo;<samp>-Av8plusb</samp>&rsquo; otherwise.
  166. </p>
  167. <p>&lsquo;<samp>-Asparcfmaf</samp>&rsquo; specifies a v9b environment with the floating point
  168. fused multiply-add instructions enabled.
  169. </p>
  170. <p>&lsquo;<samp>-Asparcima</samp>&rsquo; specifies a v9b environment with the integer
  171. multiply-add instructions enabled.
  172. </p>
  173. <p>&lsquo;<samp>-Asparcvis3</samp>&rsquo; specifies a v9b environment with the VIS 3.0,
  174. HPC , and floating point fused multiply-add instructions enabled.
  175. </p>
  176. <p>&lsquo;<samp>-Asparcvis3r</samp>&rsquo; specifies a v9b environment with the VIS 3.0, HPC,
  177. and floating point unfused multiply-add instructions enabled.
  178. </p>
  179. <p>&lsquo;<samp>-Asparc5</samp>&rsquo; is equivalent to &lsquo;<samp>-Av9m</samp>&rsquo;.
  180. </p>
  181. <p>&lsquo;<samp>-Asparc6</samp>&rsquo; is equivalent to &lsquo;<samp>-Av9m8</samp>&rsquo;.
  182. </p>
  183. </dd>
  184. <dt><code>-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc</code></dt>
  185. <dt><code>-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |</code></dt>
  186. <dt><code>-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b</code></dt>
  187. <dt><code>-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v</code></dt>
  188. <dt><code>-xarch=v9m | -xarch=v9m8</code></dt>
  189. <dt><code>-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2</code></dt>
  190. <dt><code>-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3</code></dt>
  191. <dt><code>-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6</code></dt>
  192. <dd><p>For compatibility with the SunOS v9 assembler. These options are
  193. equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
  194. -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d,
  195. -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2,
  196. -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and
  197. -Asparc6 respectively.
  198. </p>
  199. </dd>
  200. <dt><code>-bump</code></dt>
  201. <dd><p>Warn whenever it is necessary to switch to another level.
  202. If an architecture level is explicitly requested, GAS will not issue
  203. warnings until that level is reached, and will then bump the level
  204. as required (except between incompatible levels).
  205. </p>
  206. </dd>
  207. <dt><code>-32 | -64</code></dt>
  208. <dd><p>Select the word size, either 32 bits or 64 bits.
  209. These options are only available with the ELF object file format,
  210. and require that the necessary BFD support has been included.
  211. </p>
  212. </dd>
  213. <dt><code>--dcti-couples-detect</code></dt>
  214. <dd><p>Warn if a DCTI (delayed control transfer instruction) couple is found
  215. when generating code for a variant of the SPARC architecture in which
  216. the execution of the couple is unpredictable, or very slow. This is
  217. disabled by default.
  218. </p></dd>
  219. </dl>
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