as.info 1.1 MB

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  1. This is as.info, produced by makeinfo version 5.2 from as.texinfo.
  2. This file documents the GNU Assembler "as".
  3. Copyright (C) 1991-2017 Free Software Foundation, Inc.
  4. Permission is granted to copy, distribute and/or modify this document
  5. under the terms of the GNU Free Documentation License, Version 1.3 or
  6. any later version published by the Free Software Foundation; with no
  7. Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
  8. Texts. A copy of the license is included in the section entitled "GNU
  9. Free Documentation License".
  10. INFO-DIR-SECTION Software development
  11. START-INFO-DIR-ENTRY
  12. * As: (as). The GNU assembler.
  13. * Gas: (as). The GNU assembler.
  14. END-INFO-DIR-ENTRY
  15. 
  16. File: as.info, Node: Top, Next: Overview, Up: (dir)
  17. Using as
  18. ********
  19. This file is a user guide to the GNU assembler 'as' (GNU Binutils)
  20. version 2.28.
  21. This document is distributed under the terms of the GNU Free
  22. Documentation License. A copy of the license is included in the section
  23. entitled "GNU Free Documentation License".
  24. * Menu:
  25. * Overview:: Overview
  26. * Invoking:: Command-Line Options
  27. * Syntax:: Syntax
  28. * Sections:: Sections and Relocation
  29. * Symbols:: Symbols
  30. * Expressions:: Expressions
  31. * Pseudo Ops:: Assembler Directives
  32. * Object Attributes:: Object Attributes
  33. * Machine Dependencies:: Machine Dependent Features
  34. * Reporting Bugs:: Reporting Bugs
  35. * Acknowledgements:: Who Did What
  36. * GNU Free Documentation License:: GNU Free Documentation License
  37. * AS Index:: AS Index
  38. 
  39. File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top
  40. 1 Overview
  41. **********
  42. Here is a brief summary of how to invoke 'as'. For details, see *note
  43. Command-Line Options: Invoking.
  44. as [-a[cdghlns][=FILE]] [-alternate] [-D]
  45. [-compress-debug-sections] [-nocompress-debug-sections]
  46. [-debug-prefix-map OLD=NEW]
  47. [-defsym SYM=VAL] [-f] [-g] [-gstabs]
  48. [-gstabs+] [-gdwarf-2] [-gdwarf-sections]
  49. [-help] [-I DIR] [-J]
  50. [-K] [-L] [-listing-lhs-width=NUM]
  51. [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
  52. [-listing-cont-lines=NUM] [-keep-locals]
  53. [-no-pad-sections]
  54. [-o OBJFILE] [-R]
  55. [-hash-size=NUM] [-reduce-memory-overheads]
  56. [-statistics]
  57. [-v] [-version] [-version]
  58. [-W] [-warn] [-fatal-warnings] [-w] [-x]
  59. [-Z] [@FILE]
  60. [-sectname-subst] [-size-check=[error|warning]]
  61. [-elf-stt-common=[no|yes]]
  62. [-target-help] [TARGET-OPTIONS]
  63. [-|FILES ...]
  64. _Target AArch64 options:_
  65. [-EB|-EL]
  66. [-mabi=ABI]
  67. _Target Alpha options:_
  68. [-mCPU]
  69. [-mdebug | -no-mdebug]
  70. [-replace | -noreplace]
  71. [-relax] [-g] [-GSIZE]
  72. [-F] [-32addr]
  73. _Target ARC options:_
  74. [-mcpu=CPU]
  75. [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]
  76. [-mcode-density]
  77. [-mrelax]
  78. [-EB|-EL]
  79. _Target ARM options:_
  80. [-mcpu=PROCESSOR[+EXTENSION...]]
  81. [-march=ARCHITECTURE[+EXTENSION...]]
  82. [-mfpu=FLOATING-POINT-FORMAT]
  83. [-mfloat-abi=ABI]
  84. [-meabi=VER]
  85. [-mthumb]
  86. [-EB|-EL]
  87. [-mapcs-32|-mapcs-26|-mapcs-float|
  88. -mapcs-reentrant]
  89. [-mthumb-interwork] [-k]
  90. _Target Blackfin options:_
  91. [-mcpu=PROCESSOR[-SIREVISION]]
  92. [-mfdpic]
  93. [-mno-fdpic]
  94. [-mnopic]
  95. _Target CRIS options:_
  96. [-underscore | -no-underscore]
  97. [-pic] [-N]
  98. [-emulation=criself | -emulation=crisaout]
  99. [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
  100. _Target D10V options:_
  101. [-O]
  102. _Target D30V options:_
  103. [-O|-n|-N]
  104. _Target EPIPHANY options:_
  105. [-mepiphany|-mepiphany16]
  106. _Target H8/300 options:_
  107. [-h-tick-hex]
  108. _Target i386 options:_
  109. [-32|-x32|-64] [-n]
  110. [-march=CPU[+EXTENSION...]] [-mtune=CPU]
  111. _Target i960 options:_
  112. [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
  113. -AKC|-AMC]
  114. [-b] [-no-relax]
  115. _Target IA-64 options:_
  116. [-mconstant-gp|-mauto-pic]
  117. [-milp32|-milp64|-mlp64|-mp64]
  118. [-mle|mbe]
  119. [-mtune=itanium1|-mtune=itanium2]
  120. [-munwind-check=warning|-munwind-check=error]
  121. [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
  122. [-x|-xexplicit] [-xauto] [-xdebug]
  123. _Target IP2K options:_
  124. [-mip2022|-mip2022ext]
  125. _Target M32C options:_
  126. [-m32c|-m16c] [-relax] [-h-tick-hex]
  127. _Target M32R options:_
  128. [-m32rx|-[no-]warn-explicit-parallel-conflicts|
  129. -W[n]p]
  130. _Target M680X0 options:_
  131. [-l] [-m68000|-m68010|-m68020|...]
  132. _Target M68HC11 options:_
  133. [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]
  134. [-mshort|-mlong]
  135. [-mshort-double|-mlong-double]
  136. [-force-long-branches] [-short-branches]
  137. [-strict-direct-mode] [-print-insn-syntax]
  138. [-print-opcodes] [-generate-example]
  139. _Target MCORE options:_
  140. [-jsri2bsr] [-sifilter] [-relax]
  141. [-mcpu=[210|340]]
  142. _Target Meta options:_
  143. [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU]
  144. _Target MICROBLAZE options:_
  145. _Target MIPS options:_
  146. [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
  147. [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
  148. [-non_shared] [-xgot [-mvxworks-pic]
  149. [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
  150. [-mfp64] [-mgp64] [-mfpxx]
  151. [-modd-spreg] [-mno-odd-spreg]
  152. [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
  153. [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
  154. [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]
  155. [-mips64r3] [-mips64r5] [-mips64r6]
  156. [-construct-floats] [-no-construct-floats]
  157. [-mignore-branch-isa] [-mno-ignore-branch-isa]
  158. [-mnan=ENCODING]
  159. [-trap] [-no-break] [-break] [-no-trap]
  160. [-mips16] [-no-mips16]
  161. [-mmicromips] [-mno-micromips]
  162. [-msmartmips] [-mno-smartmips]
  163. [-mips3d] [-no-mips3d]
  164. [-mdmx] [-no-mdmx]
  165. [-mdsp] [-mno-dsp]
  166. [-mdspr2] [-mno-dspr2]
  167. [-mdspr3] [-mno-dspr3]
  168. [-mmsa] [-mno-msa]
  169. [-mxpa] [-mno-xpa]
  170. [-mmt] [-mno-mt]
  171. [-mmcu] [-mno-mcu]
  172. [-minsn32] [-mno-insn32]
  173. [-mfix7000] [-mno-fix7000]
  174. [-mfix-rm7000] [-mno-fix-rm7000]
  175. [-mfix-vr4120] [-mno-fix-vr4120]
  176. [-mfix-vr4130] [-mno-fix-vr4130]
  177. [-mdebug] [-no-mdebug]
  178. [-mpdr] [-mno-pdr]
  179. _Target MMIX options:_
  180. [-fixed-special-register-names] [-globalize-symbols]
  181. [-gnu-syntax] [-relax] [-no-predefined-symbols]
  182. [-no-expand] [-no-merge-gregs] [-x]
  183. [-linker-allocated-gregs]
  184. _Target Nios II options:_
  185. [-relax-all] [-relax-section] [-no-relax]
  186. [-EB] [-EL]
  187. _Target NDS32 options:_
  188. [-EL] [-EB] [-O] [-Os] [-mcpu=CPU]
  189. [-misa=ISA] [-mabi=ABI] [-mall-ext]
  190. [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]
  191. [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]
  192. [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]
  193. [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]
  194. [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]
  195. [-mb2bb]
  196. _Target PDP11 options:_
  197. [-mpic|-mno-pic] [-mall] [-mno-extensions]
  198. [-mEXTENSION|-mno-EXTENSION]
  199. [-mCPU] [-mMACHINE]
  200. _Target picoJava options:_
  201. [-mb|-me]
  202. _Target PowerPC options:_
  203. [-a32|-a64]
  204. [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|
  205. -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64|
  206. -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge|
  207. -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6|
  208. -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|
  209. -mcell|-mspe|-mtitan|-me300|-mcom]
  210. [-many] [-maltivec|-mvsx|-mhtm|-mvle]
  211. [-mregnames|-mno-regnames]
  212. [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]
  213. [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]
  214. [-msolaris|-mno-solaris]
  215. [-nops=COUNT]
  216. _Target RL78 options:_
  217. [-mg10]
  218. [-m32bit-doubles|-m64bit-doubles]
  219. _Target RX options:_
  220. [-mlittle-endian|-mbig-endian]
  221. [-m32bit-doubles|-m64bit-doubles]
  222. [-muse-conventional-section-names]
  223. [-msmall-data-limit]
  224. [-mpid]
  225. [-mrelax]
  226. [-mint-register=NUMBER]
  227. [-mgcc-abi|-mrx-abi]
  228. _Target RISC-V options:_
  229. [-march=ISA]
  230. [-mabi=ABI]
  231. _Target s390 options:_
  232. [-m31|-m64] [-mesa|-mzarch] [-march=CPU]
  233. [-mregnames|-mno-regnames]
  234. [-mwarn-areg-zero]
  235. _Target SCORE options:_
  236. [-EB][-EL][-FIXDD][-NWARN]
  237. [-SCORE5][-SCORE5U][-SCORE7][-SCORE3]
  238. [-march=score7][-march=score3]
  239. [-USE_R1][-KPIC][-O0][-G NUM][-V]
  240. _Target SPARC options:_
  241. [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite
  242. -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd
  243. -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c
  244. -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis
  245. -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3
  246. -Asparcvisr|-Asparc5]
  247. [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc
  248. -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9
  249. -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e
  250. -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis
  251. -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima
  252. -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5
  253. -bump]
  254. [-32|-64]
  255. [-enforce-aligned-data][-dcti-couples-detect]
  256. _Target TIC54X options:_
  257. [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
  258. [-merrors-to-file <FILENAME>|-me <FILENAME>]
  259. _Target TIC6X options:_
  260. [-march=ARCH] [-mbig-endian|-mlittle-endian]
  261. [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]
  262. [-mpic|-mno-pic]
  263. _Target TILE-Gx options:_
  264. [-m32|-m64][-EB][-EL]
  265. _Target Visium options:_
  266. [-mtune=ARCH]
  267. _Target Xtensa options:_
  268. [-[no-]text-section-literals] [-[no-]auto-litpools]
  269. [-[no-]absolute-literals]
  270. [-[no-]target-align] [-[no-]longcalls]
  271. [-[no-]transform]
  272. [-rename-section OLDNAME=NEWNAME]
  273. [-[no-]trampolines]
  274. _Target Z80 options:_
  275. [-z80] [-r800]
  276. [ -ignore-undocumented-instructions] [-Wnud]
  277. [ -ignore-unportable-instructions] [-Wnup]
  278. [ -warn-undocumented-instructions] [-Wud]
  279. [ -warn-unportable-instructions] [-Wup]
  280. [ -forbid-undocumented-instructions] [-Fud]
  281. [ -forbid-unportable-instructions] [-Fup]
  282. '@FILE'
  283. Read command-line options from FILE. The options read are inserted
  284. in place of the original @FILE option. If FILE does not exist, or
  285. cannot be read, then the option will be treated literally, and not
  286. removed.
  287. Options in FILE are separated by whitespace. A whitespace
  288. character may be included in an option by surrounding the entire
  289. option in either single or double quotes. Any character (including
  290. a backslash) may be included by prefixing the character to be
  291. included with a backslash. The FILE may itself contain additional
  292. @FILE options; any such options will be processed recursively.
  293. '-a[cdghlmns]'
  294. Turn on listings, in any of a variety of ways:
  295. '-ac'
  296. omit false conditionals
  297. '-ad'
  298. omit debugging directives
  299. '-ag'
  300. include general information, like as version and options
  301. passed
  302. '-ah'
  303. include high-level source
  304. '-al'
  305. include assembly
  306. '-am'
  307. include macro expansions
  308. '-an'
  309. omit forms processing
  310. '-as'
  311. include symbols
  312. '=file'
  313. set the name of the listing file
  314. You may combine these options; for example, use '-aln' for assembly
  315. listing without forms processing. The '=file' option, if used,
  316. must be the last one. By itself, '-a' defaults to '-ahls'.
  317. '--alternate'
  318. Begin in alternate macro mode. *Note '.altmacro': Altmacro.
  319. '--compress-debug-sections'
  320. Compress DWARF debug sections using zlib with SHF_COMPRESSED from
  321. the ELF ABI. The resulting object file may not be compatible with
  322. older linkers and object file utilities. Note if compression would
  323. make a given section _larger_ then it is not compressed.
  324. '--compress-debug-sections=none'
  325. '--compress-debug-sections=zlib'
  326. '--compress-debug-sections=zlib-gnu'
  327. '--compress-debug-sections=zlib-gabi'
  328. These options control how DWARF debug sections are compressed.
  329. '--compress-debug-sections=none' is equivalent to
  330. '--nocompress-debug-sections'. '--compress-debug-sections=zlib'
  331. and '--compress-debug-sections=zlib-gabi' are equivalent to
  332. '--compress-debug-sections'. '--compress-debug-sections=zlib-gnu'
  333. compresses DWARF debug sections using zlib. The debug sections are
  334. renamed to begin with '.zdebug'. Note if compression would make a
  335. given section _larger_ then it is not compressed nor renamed.
  336. '--nocompress-debug-sections'
  337. Do not compress DWARF debug sections. This is usually the default
  338. for all targets except the x86/x86_64, but a configure time option
  339. can be used to override this.
  340. '-D'
  341. Ignored. This option is accepted for script compatibility with
  342. calls to other assemblers.
  343. '--debug-prefix-map OLD=NEW'
  344. When assembling files in directory 'OLD', record debugging
  345. information describing them as in 'NEW' instead.
  346. '--defsym SYM=VALUE'
  347. Define the symbol SYM to be VALUE before assembling the input file.
  348. VALUE must be an integer constant. As in C, a leading '0x'
  349. indicates a hexadecimal value, and a leading '0' indicates an octal
  350. value. The value of the symbol can be overridden inside a source
  351. file via the use of a '.set' pseudo-op.
  352. '-f'
  353. "fast"--skip whitespace and comment preprocessing (assume source is
  354. compiler output).
  355. '-g'
  356. '--gen-debug'
  357. Generate debugging information for each assembler source line using
  358. whichever debug format is preferred by the target. This currently
  359. means either STABS, ECOFF or DWARF2.
  360. '--gstabs'
  361. Generate stabs debugging information for each assembler line. This
  362. may help debugging assembler code, if the debugger can handle it.
  363. '--gstabs+'
  364. Generate stabs debugging information for each assembler line, with
  365. GNU extensions that probably only gdb can handle, and that could
  366. make other debuggers crash or refuse to read your program. This
  367. may help debugging assembler code. Currently the only GNU
  368. extension is the location of the current working directory at
  369. assembling time.
  370. '--gdwarf-2'
  371. Generate DWARF2 debugging information for each assembler line.
  372. This may help debugging assembler code, if the debugger can handle
  373. it. Note--this option is only supported by some targets, not all
  374. of them.
  375. '--gdwarf-sections'
  376. Instead of creating a .debug_line section, create a series of
  377. .debug_line.FOO sections where FOO is the name of the corresponding
  378. code section. For example a code section called .TEXT.FUNC will
  379. have its dwarf line number information placed into a section called
  380. .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT
  381. then debug line section will still be called just .DEBUG_LINE
  382. without any suffix.
  383. '--size-check=error'
  384. '--size-check=warning'
  385. Issue an error or warning for invalid ELF .size directive.
  386. '--elf-stt-common=no'
  387. '--elf-stt-common=yes'
  388. These options control whether the ELF assembler should generate
  389. common symbols with the 'STT_COMMON' type. The default can be
  390. controlled by a configure option '--enable-elf-stt-common'.
  391. '--help'
  392. Print a summary of the command line options and exit.
  393. '--target-help'
  394. Print a summary of all target specific options and exit.
  395. '-I DIR'
  396. Add directory DIR to the search list for '.include' directives.
  397. '-J'
  398. Don't warn about signed overflow.
  399. '-K'
  400. Issue warnings when difference tables altered for long
  401. displacements.
  402. '-L'
  403. '--keep-locals'
  404. Keep (in the symbol table) local symbols. These symbols start with
  405. system-specific local label prefixes, typically '.L' for ELF
  406. systems or 'L' for traditional a.out systems. *Note Symbol
  407. Names::.
  408. '--listing-lhs-width=NUMBER'
  409. Set the maximum width, in words, of the output data column for an
  410. assembler listing to NUMBER.
  411. '--listing-lhs-width2=NUMBER'
  412. Set the maximum width, in words, of the output data column for
  413. continuation lines in an assembler listing to NUMBER.
  414. '--listing-rhs-width=NUMBER'
  415. Set the maximum width of an input source line, as displayed in a
  416. listing, to NUMBER bytes.
  417. '--listing-cont-lines=NUMBER'
  418. Set the maximum number of lines printed in a listing for a single
  419. line of input to NUMBER + 1.
  420. '--no-pad-sections'
  421. Stop the assembler for padding the ends of output sections to the
  422. alignment of that section. The default is to pad the sections, but
  423. this can waste space which might be needed on targets which have
  424. tight memory constraints.
  425. '-o OBJFILE'
  426. Name the object-file output from 'as' OBJFILE.
  427. '-R'
  428. Fold the data section into the text section.
  429. '--hash-size=NUMBER'
  430. Set the default size of GAS's hash tables to a prime number close
  431. to NUMBER. Increasing this value can reduce the length of time it
  432. takes the assembler to perform its tasks, at the expense of
  433. increasing the assembler's memory requirements. Similarly reducing
  434. this value can reduce the memory requirements at the expense of
  435. speed.
  436. '--reduce-memory-overheads'
  437. This option reduces GAS's memory requirements, at the expense of
  438. making the assembly processes slower. Currently this switch is a
  439. synonym for '--hash-size=4051', but in the future it may have other
  440. effects as well.
  441. '--sectname-subst'
  442. Honor substitution sequences in section names. *Note '.section
  443. NAME': Section Name Substitutions.
  444. '--statistics'
  445. Print the maximum space (in bytes) and total time (in seconds) used
  446. by assembly.
  447. '--strip-local-absolute'
  448. Remove local absolute symbols from the outgoing symbol table.
  449. '-v'
  450. '-version'
  451. Print the 'as' version.
  452. '--version'
  453. Print the 'as' version and exit.
  454. '-W'
  455. '--no-warn'
  456. Suppress warning messages.
  457. '--fatal-warnings'
  458. Treat warnings as errors.
  459. '--warn'
  460. Don't suppress warning messages or treat them as errors.
  461. '-w'
  462. Ignored.
  463. '-x'
  464. Ignored.
  465. '-Z'
  466. Generate an object file even after errors.
  467. '-- | FILES ...'
  468. Standard input, or source files to assemble.
  469. *Note AArch64 Options::, for the options available when as is
  470. configured for the 64-bit mode of the ARM Architecture (AArch64).
  471. *Note Alpha Options::, for the options available when as is
  472. configured for an Alpha processor.
  473. The following options are available when as is configured for an ARC
  474. processor.
  475. '-mcpu=CPU'
  476. This option selects the core processor variant.
  477. '-EB | -EL'
  478. Select either big-endian (-EB) or little-endian (-EL) output.
  479. '-mcode-density'
  480. Enable Code Density extenssion instructions.
  481. The following options are available when as is configured for the ARM
  482. processor family.
  483. '-mcpu=PROCESSOR[+EXTENSION...]'
  484. Specify which ARM processor variant is the target.
  485. '-march=ARCHITECTURE[+EXTENSION...]'
  486. Specify which ARM architecture variant is used by the target.
  487. '-mfpu=FLOATING-POINT-FORMAT'
  488. Select which Floating Point architecture is the target.
  489. '-mfloat-abi=ABI'
  490. Select which floating point ABI is in use.
  491. '-mthumb'
  492. Enable Thumb only instruction decoding.
  493. '-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
  494. Select which procedure calling convention is in use.
  495. '-EB | -EL'
  496. Select either big-endian (-EB) or little-endian (-EL) output.
  497. '-mthumb-interwork'
  498. Specify that the code has been generated with interworking between
  499. Thumb and ARM code in mind.
  500. '-mccs'
  501. Turns on CodeComposer Studio assembly syntax compatibility mode.
  502. '-k'
  503. Specify that PIC code has been generated.
  504. *Note Blackfin Options::, for the options available when as is
  505. configured for the Blackfin processor family.
  506. See the info pages for documentation of the CRIS-specific options.
  507. The following options are available when as is configured for a D10V
  508. processor.
  509. '-O'
  510. Optimize output by parallelizing instructions.
  511. The following options are available when as is configured for a D30V
  512. processor.
  513. '-O'
  514. Optimize output by parallelizing instructions.
  515. '-n'
  516. Warn when nops are generated.
  517. '-N'
  518. Warn when a nop after a 32-bit multiply instruction is generated.
  519. The following options are available when as is configured for the
  520. Adapteva EPIPHANY series.
  521. *Note Epiphany Options::, for the options available when as is
  522. configured for an Epiphany processor.
  523. *Note i386-Options::, for the options available when as is configured
  524. for an i386 processor.
  525. The following options are available when as is configured for the
  526. Intel 80960 processor.
  527. '-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
  528. Specify which variant of the 960 architecture is the target.
  529. '-b'
  530. Add code to collect statistics about branches taken.
  531. '-no-relax'
  532. Do not alter compare-and-branch instructions for long
  533. displacements; error if necessary.
  534. The following options are available when as is configured for the
  535. Ubicom IP2K series.
  536. '-mip2022ext'
  537. Specifies that the extended IP2022 instructions are allowed.
  538. '-mip2022'
  539. Restores the default behaviour, which restricts the permitted
  540. instructions to just the basic IP2022 ones.
  541. The following options are available when as is configured for the
  542. Renesas M32C and M16C processors.
  543. '-m32c'
  544. Assemble M32C instructions.
  545. '-m16c'
  546. Assemble M16C instructions (the default).
  547. '-relax'
  548. Enable support for link-time relaxations.
  549. '-h-tick-hex'
  550. Support H'00 style hex constants in addition to 0x00 style.
  551. The following options are available when as is configured for the
  552. Renesas M32R (formerly Mitsubishi M32R) series.
  553. '--m32rx'
  554. Specify which processor in the M32R family is the target. The
  555. default is normally the M32R, but this option changes it to the
  556. M32RX.
  557. '--warn-explicit-parallel-conflicts or --Wp'
  558. Produce warning messages when questionable parallel constructs are
  559. encountered.
  560. '--no-warn-explicit-parallel-conflicts or --Wnp'
  561. Do not produce warning messages when questionable parallel
  562. constructs are encountered.
  563. The following options are available when as is configured for the
  564. Motorola 68000 series.
  565. '-l'
  566. Shorten references to undefined symbols, to one word instead of
  567. two.
  568. '-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
  569. '| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
  570. '| -m68333 | -m68340 | -mcpu32 | -m5200'
  571. Specify what processor in the 68000 family is the target. The
  572. default is normally the 68020, but this can be changed at
  573. configuration time.
  574. '-m68881 | -m68882 | -mno-68881 | -mno-68882'
  575. The target machine does (or does not) have a floating-point
  576. coprocessor. The default is to assume a coprocessor for 68020,
  577. 68030, and cpu32. Although the basic 68000 is not compatible with
  578. the 68881, a combination of the two can be specified, since it's
  579. possible to do emulation of the coprocessor instructions with the
  580. main processor.
  581. '-m68851 | -mno-68851'
  582. The target machine does (or does not) have a memory-management unit
  583. coprocessor. The default is to assume an MMU for 68020 and up.
  584. *Note Nios II Options::, for the options available when as is
  585. configured for an Altera Nios II processor.
  586. For details about the PDP-11 machine dependent features options, see
  587. *note PDP-11-Options::.
  588. '-mpic | -mno-pic'
  589. Generate position-independent (or position-dependent) code. The
  590. default is '-mpic'.
  591. '-mall'
  592. '-mall-extensions'
  593. Enable all instruction set extensions. This is the default.
  594. '-mno-extensions'
  595. Disable all instruction set extensions.
  596. '-mEXTENSION | -mno-EXTENSION'
  597. Enable (or disable) a particular instruction set extension.
  598. '-mCPU'
  599. Enable the instruction set extensions supported by a particular
  600. CPU, and disable all other extensions.
  601. '-mMACHINE'
  602. Enable the instruction set extensions supported by a particular
  603. machine model, and disable all other extensions.
  604. The following options are available when as is configured for a
  605. picoJava processor.
  606. '-mb'
  607. Generate "big endian" format output.
  608. '-ml'
  609. Generate "little endian" format output.
  610. The following options are available when as is configured for the
  611. Motorola 68HC11 or 68HC12 series.
  612. '-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg'
  613. Specify what processor is the target. The default is defined by
  614. the configuration option when building the assembler.
  615. '--xgate-ramoffset'
  616. Instruct the linker to offset RAM addresses from S12X address space
  617. into XGATE address space.
  618. '-mshort'
  619. Specify to use the 16-bit integer ABI.
  620. '-mlong'
  621. Specify to use the 32-bit integer ABI.
  622. '-mshort-double'
  623. Specify to use the 32-bit double ABI.
  624. '-mlong-double'
  625. Specify to use the 64-bit double ABI.
  626. '--force-long-branches'
  627. Relative branches are turned into absolute ones. This concerns
  628. conditional branches, unconditional branches and branches to a sub
  629. routine.
  630. '-S | --short-branches'
  631. Do not turn relative branches into absolute ones when the offset is
  632. out of range.
  633. '--strict-direct-mode'
  634. Do not turn the direct addressing mode into extended addressing
  635. mode when the instruction does not support direct addressing mode.
  636. '--print-insn-syntax'
  637. Print the syntax of instruction in case of error.
  638. '--print-opcodes'
  639. Print the list of instructions with syntax and then exit.
  640. '--generate-example'
  641. Print an example of instruction for each possible instruction and
  642. then exit. This option is only useful for testing 'as'.
  643. The following options are available when 'as' is configured for the
  644. SPARC architecture:
  645. '-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
  646. '-Av8plus | -Av8plusa | -Av9 | -Av9a'
  647. Explicitly select a variant of the SPARC architecture.
  648. '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and
  649. '-Av9a' select a 64 bit environment.
  650. '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with
  651. UltraSPARC extensions.
  652. '-xarch=v8plus | -xarch=v8plusa'
  653. For compatibility with the Solaris v9 assembler. These options are
  654. equivalent to -Av8plus and -Av8plusa, respectively.
  655. '-bump'
  656. Warn when the assembler switches to another architecture.
  657. The following options are available when as is configured for the
  658. 'c54x architecture.
  659. '-mfar-mode'
  660. Enable extended addressing mode. All addresses and relocations
  661. will assume extended addressing (usually 23 bits).
  662. '-mcpu=CPU_VERSION'
  663. Sets the CPU version being compiled for.
  664. '-merrors-to-file FILENAME'
  665. Redirect error output to a file, for broken systems which don't
  666. support such behaviour in the shell.
  667. The following options are available when as is configured for a MIPS
  668. processor.
  669. '-G NUM'
  670. This option sets the largest size of an object that can be
  671. referenced implicitly with the 'gp' register. It is only accepted
  672. for targets that use ECOFF format, such as a DECstation running
  673. Ultrix. The default value is 8.
  674. '-EB'
  675. Generate "big endian" format output.
  676. '-EL'
  677. Generate "little endian" format output.
  678. '-mips1'
  679. '-mips2'
  680. '-mips3'
  681. '-mips4'
  682. '-mips5'
  683. '-mips32'
  684. '-mips32r2'
  685. '-mips32r3'
  686. '-mips32r5'
  687. '-mips32r6'
  688. '-mips64'
  689. '-mips64r2'
  690. '-mips64r3'
  691. '-mips64r5'
  692. '-mips64r6'
  693. Generate code for a particular MIPS Instruction Set Architecture
  694. level. '-mips1' is an alias for '-march=r3000', '-mips2' is an
  695. alias for '-march=r6000', '-mips3' is an alias for '-march=r4000'
  696. and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32',
  697. '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', '-mips64',
  698. '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' correspond
  699. to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3,
  700. MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2,
  701. MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA
  702. processors, respectively.
  703. '-march=CPU'
  704. Generate code for a particular MIPS CPU.
  705. '-mtune=CPU'
  706. Schedule and tune for a particular MIPS CPU.
  707. '-mfix7000'
  708. '-mno-fix7000'
  709. Cause nops to be inserted if the read of the destination register
  710. of an mfhi or mflo instruction occurs in the following two
  711. instructions.
  712. '-mfix-rm7000'
  713. '-mno-fix-rm7000'
  714. Cause nops to be inserted if a dmult or dmultu instruction is
  715. followed by a load instruction.
  716. '-mdebug'
  717. '-no-mdebug'
  718. Cause stabs-style debugging output to go into an ECOFF-style
  719. .mdebug section instead of the standard ELF .stabs sections.
  720. '-mpdr'
  721. '-mno-pdr'
  722. Control generation of '.pdr' sections.
  723. '-mgp32'
  724. '-mfp32'
  725. The register sizes are normally inferred from the ISA and ABI, but
  726. these flags force a certain group of registers to be treated as 32
  727. bits wide at all times. '-mgp32' controls the size of
  728. general-purpose registers and '-mfp32' controls the size of
  729. floating-point registers.
  730. '-mgp64'
  731. '-mfp64'
  732. The register sizes are normally inferred from the ISA and ABI, but
  733. these flags force a certain group of registers to be treated as 64
  734. bits wide at all times. '-mgp64' controls the size of
  735. general-purpose registers and '-mfp64' controls the size of
  736. floating-point registers.
  737. '-mfpxx'
  738. The register sizes are normally inferred from the ISA and ABI, but
  739. using this flag in combination with '-mabi=32' enables an ABI
  740. variant which will operate correctly with floating-point registers
  741. which are 32 or 64 bits wide.
  742. '-modd-spreg'
  743. '-mno-odd-spreg'
  744. Enable use of floating-point operations on odd-numbered
  745. single-precision registers when supported by the ISA. '-mfpxx'
  746. implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'.
  747. '-mips16'
  748. '-no-mips16'
  749. Generate code for the MIPS 16 processor. This is equivalent to
  750. putting '.set mips16' at the start of the assembly file.
  751. '-no-mips16' turns off this option.
  752. '-mmicromips'
  753. '-mno-micromips'
  754. Generate code for the microMIPS processor. This is equivalent to
  755. putting '.set micromips' at the start of the assembly file.
  756. '-mno-micromips' turns off this option. This is equivalent to
  757. putting '.set nomicromips' at the start of the assembly file.
  758. '-msmartmips'
  759. '-mno-smartmips'
  760. Enables the SmartMIPS extension to the MIPS32 instruction set.
  761. This is equivalent to putting '.set smartmips' at the start of the
  762. assembly file. '-mno-smartmips' turns off this option.
  763. '-mips3d'
  764. '-no-mips3d'
  765. Generate code for the MIPS-3D Application Specific Extension. This
  766. tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
  767. turns off this option.
  768. '-mdmx'
  769. '-no-mdmx'
  770. Generate code for the MDMX Application Specific Extension. This
  771. tells the assembler to accept MDMX instructions. '-no-mdmx' turns
  772. off this option.
  773. '-mdsp'
  774. '-mno-dsp'
  775. Generate code for the DSP Release 1 Application Specific Extension.
  776. This tells the assembler to accept DSP Release 1 instructions.
  777. '-mno-dsp' turns off this option.
  778. '-mdspr2'
  779. '-mno-dspr2'
  780. Generate code for the DSP Release 2 Application Specific Extension.
  781. This option implies '-mdsp'. This tells the assembler to accept
  782. DSP Release 2 instructions. '-mno-dspr2' turns off this option.
  783. '-mdspr3'
  784. '-mno-dspr3'
  785. Generate code for the DSP Release 3 Application Specific Extension.
  786. This option implies '-mdsp' and '-mdspr2'. This tells the
  787. assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns
  788. off this option.
  789. '-mmsa'
  790. '-mno-msa'
  791. Generate code for the MIPS SIMD Architecture Extension. This tells
  792. the assembler to accept MSA instructions. '-mno-msa' turns off
  793. this option.
  794. '-mxpa'
  795. '-mno-xpa'
  796. Generate code for the MIPS eXtended Physical Address (XPA)
  797. Extension. This tells the assembler to accept XPA instructions.
  798. '-mno-xpa' turns off this option.
  799. '-mmt'
  800. '-mno-mt'
  801. Generate code for the MT Application Specific Extension. This
  802. tells the assembler to accept MT instructions. '-mno-mt' turns off
  803. this option.
  804. '-mmcu'
  805. '-mno-mcu'
  806. Generate code for the MCU Application Specific Extension. This
  807. tells the assembler to accept MCU instructions. '-mno-mcu' turns
  808. off this option.
  809. '-minsn32'
  810. '-mno-insn32'
  811. Only use 32-bit instruction encodings when generating code for the
  812. microMIPS processor. This option inhibits the use of any 16-bit
  813. instructions. This is equivalent to putting '.set insn32' at the
  814. start of the assembly file. '-mno-insn32' turns off this option.
  815. This is equivalent to putting '.set noinsn32' at the start of the
  816. assembly file. By default '-mno-insn32' is selected, allowing all
  817. instructions to be used.
  818. '--construct-floats'
  819. '--no-construct-floats'
  820. The '--no-construct-floats' option disables the construction of
  821. double width floating point constants by loading the two halves of
  822. the value into the two single width floating point registers that
  823. make up the double width register. By default '--construct-floats'
  824. is selected, allowing construction of these floating point
  825. constants.
  826. '--relax-branch'
  827. '--no-relax-branch'
  828. The '--relax-branch' option enables the relaxation of out-of-range
  829. branches. By default '--no-relax-branch' is selected, causing any
  830. out-of-range branches to produce an error.
  831. '-mignore-branch-isa'
  832. '-mno-ignore-branch-isa'
  833. Ignore branch checks for invalid transitions between ISA modes.
  834. The semantics of branches does not provide for an ISA mode switch,
  835. so in most cases the ISA mode a branch has been encoded for has to
  836. be the same as the ISA mode of the branch's target label.
  837. Therefore GAS has checks implemented that verify in branch assembly
  838. that the two ISA modes match. '-mignore-branch-isa' disables these
  839. checks. By default '-mno-ignore-branch-isa' is selected, causing
  840. any invalid branch requiring a transition between ISA modes to
  841. produce an error.
  842. '-mnan=ENCODING'
  843. Select between the IEEE 754-2008 ('-mnan=2008') or the legacy
  844. ('-mnan=legacy') NaN encoding format. The latter is the default.
  845. '--emulation=NAME'
  846. This option was formerly used to switch between ELF and ECOFF
  847. output on targets like IRIX 5 that supported both. MIPS ECOFF
  848. support was removed in GAS 2.24, so the option now serves little
  849. purpose. It is retained for backwards compatibility.
  850. The available configuration names are: 'mipself', 'mipslelf' and
  851. 'mipsbelf'. Choosing 'mipself' now has no effect, since the output
  852. is always ELF. 'mipslelf' and 'mipsbelf' select little- and
  853. big-endian output respectively, but '-EL' and '-EB' are now the
  854. preferred options instead.
  855. '-nocpp'
  856. 'as' ignores this option. It is accepted for compatibility with
  857. the native tools.
  858. '--trap'
  859. '--no-trap'
  860. '--break'
  861. '--no-break'
  862. Control how to deal with multiplication overflow and division by
  863. zero. '--trap' or '--no-break' (which are synonyms) take a trap
  864. exception (and only work for Instruction Set Architecture level 2
  865. and higher); '--break' or '--no-trap' (also synonyms, and the
  866. default) take a break exception.
  867. '-n'
  868. When this option is used, 'as' will issue a warning every time it
  869. generates a nop instruction from a macro.
  870. The following options are available when as is configured for an
  871. MCore processor.
  872. '-jsri2bsr'
  873. '-nojsri2bsr'
  874. Enable or disable the JSRI to BSR transformation. By default this
  875. is enabled. The command line option '-nojsri2bsr' can be used to
  876. disable it.
  877. '-sifilter'
  878. '-nosifilter'
  879. Enable or disable the silicon filter behaviour. By default this is
  880. disabled. The default can be overridden by the '-sifilter' command
  881. line option.
  882. '-relax'
  883. Alter jump instructions for long displacements.
  884. '-mcpu=[210|340]'
  885. Select the cpu type on the target hardware. This controls which
  886. instructions can be assembled.
  887. '-EB'
  888. Assemble for a big endian target.
  889. '-EL'
  890. Assemble for a little endian target.
  891. *Note Meta Options::, for the options available when as is configured
  892. for a Meta processor.
  893. See the info pages for documentation of the MMIX-specific options.
  894. *Note NDS32 Options::, for the options available when as is
  895. configured for a NDS32 processor.
  896. *Note PowerPC-Opts::, for the options available when as is configured
  897. for a PowerPC processor.
  898. *Note RISC-V-Opts::, for the options available when as is configured
  899. for a RISC-V processor.
  900. See the info pages for documentation of the RX-specific options.
  901. The following options are available when as is configured for the
  902. s390 processor family.
  903. '-m31'
  904. '-m64'
  905. Select the word size, either 31/32 bits or 64 bits.
  906. '-mesa'
  907. '-mzarch'
  908. Select the architecture mode, either the Enterprise System
  909. Architecture (esa) or the z/Architecture mode (zarch).
  910. '-march=PROCESSOR'
  911. Specify which s390 processor variant is the target, 'g5' (or
  912. 'arch3'), 'g6', 'z900' (or 'arch5'), 'z990' (or 'arch6'), 'z9-109',
  913. 'z9-ec' (or 'arch7'), 'z10' (or 'arch8'), 'z196' (or 'arch9'),
  914. 'zEC12' (or 'arch10'), 'z13' (or 'arch11'), or 'z14' (or 'arch12').
  915. '-mregnames'
  916. '-mno-regnames'
  917. Allow or disallow symbolic names for registers.
  918. '-mwarn-areg-zero'
  919. Warn whenever the operand for a base or index register has been
  920. specified but evaluates to zero.
  921. *Note TIC6X Options::, for the options available when as is
  922. configured for a TMS320C6000 processor.
  923. *Note TILE-Gx Options::, for the options available when as is
  924. configured for a TILE-Gx processor.
  925. *Note Visium Options::, for the options available when as is
  926. configured for a Visium processor.
  927. *Note Xtensa Options::, for the options available when as is
  928. configured for an Xtensa processor.
  929. The following options are available when as is configured for a Z80
  930. family processor.
  931. '-z80'
  932. Assemble for Z80 processor.
  933. '-r800'
  934. Assemble for R800 processor.
  935. '-ignore-undocumented-instructions'
  936. '-Wnud'
  937. Assemble undocumented Z80 instructions that also work on R800
  938. without warning.
  939. '-ignore-unportable-instructions'
  940. '-Wnup'
  941. Assemble all undocumented Z80 instructions without warning.
  942. '-warn-undocumented-instructions'
  943. '-Wud'
  944. Issue a warning for undocumented Z80 instructions that also work on
  945. R800.
  946. '-warn-unportable-instructions'
  947. '-Wup'
  948. Issue a warning for undocumented Z80 instructions that do not work
  949. on R800.
  950. '-forbid-undocumented-instructions'
  951. '-Fud'
  952. Treat all undocumented instructions as errors.
  953. '-forbid-unportable-instructions'
  954. '-Fup'
  955. Treat undocumented Z80 instructions that do not work on R800 as
  956. errors.
  957. * Menu:
  958. * Manual:: Structure of this Manual
  959. * GNU Assembler:: The GNU Assembler
  960. * Object Formats:: Object File Formats
  961. * Command Line:: Command Line
  962. * Input Files:: Input Files
  963. * Object:: Output (Object) File
  964. * Errors:: Error and Warning Messages
  965. 
  966. File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview
  967. 1.1 Structure of this Manual
  968. ============================
  969. This manual is intended to describe what you need to know to use GNU
  970. 'as'. We cover the syntax expected in source files, including notation
  971. for symbols, constants, and expressions; the directives that 'as'
  972. understands; and of course how to invoke 'as'.
  973. This manual also describes some of the machine-dependent features of
  974. various flavors of the assembler.
  975. On the other hand, this manual is _not_ intended as an introduction
  976. to programming in assembly language--let alone programming in general!
  977. In a similar vein, we make no attempt to introduce the machine
  978. architecture; we do _not_ describe the instruction set, standard
  979. mnemonics, registers or addressing modes that are standard to a
  980. particular architecture. You may want to consult the manufacturer's
  981. machine architecture manual for this information.
  982. 
  983. File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview
  984. 1.2 The GNU Assembler
  985. =====================
  986. GNU 'as' is really a family of assemblers. If you use (or have used)
  987. the GNU assembler on one architecture, you should find a fairly similar
  988. environment when you use it on another architecture. Each version has
  989. much in common with the others, including object file formats, most
  990. assembler directives (often called "pseudo-ops") and assembler syntax.
  991. 'as' is primarily intended to assemble the output of the GNU C
  992. compiler 'gcc' for use by the linker 'ld'. Nevertheless, we've tried to
  993. make 'as' assemble correctly everything that other assemblers for the
  994. same machine would assemble. Any exceptions are documented explicitly
  995. (*note Machine Dependencies::). This doesn't mean 'as' always uses the
  996. same syntax as another assembler for the same architecture; for example,
  997. we know of several incompatible versions of 680x0 assembly language
  998. syntax.
  999. Unlike older assemblers, 'as' is designed to assemble a source
  1000. program in one pass of the source file. This has a subtle impact on the
  1001. '.org' directive (*note '.org': Org.).
  1002. 
  1003. File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview
  1004. 1.3 Object File Formats
  1005. =======================
  1006. The GNU assembler can be configured to produce several alternative
  1007. object file formats. For the most part, this does not affect how you
  1008. write assembly language programs; but directives for debugging symbols
  1009. are typically different in different file formats. *Note Symbol
  1010. Attributes: Symbol Attributes.
  1011. 
  1012. File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview
  1013. 1.4 Command Line
  1014. ================
  1015. After the program name 'as', the command line may contain options and
  1016. file names. Options may appear in any order, and may be before, after,
  1017. or between file names. The order of file names is significant.
  1018. '--' (two hyphens) by itself names the standard input file
  1019. explicitly, as one of the files for 'as' to assemble.
  1020. Except for '--' any command line argument that begins with a hyphen
  1021. ('-') is an option. Each option changes the behavior of 'as'. No
  1022. option changes the way another option works. An option is a '-'
  1023. followed by one or more letters; the case of the letter is important.
  1024. All options are optional.
  1025. Some options expect exactly one file name to follow them. The file
  1026. name may either immediately follow the option's letter (compatible with
  1027. older assemblers) or it may be the next command argument (GNU standard).
  1028. These two command lines are equivalent:
  1029. as -o my-object-file.o mumble.s
  1030. as -omy-object-file.o mumble.s
  1031. 
  1032. File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview
  1033. 1.5 Input Files
  1034. ===============
  1035. We use the phrase "source program", abbreviated "source", to describe
  1036. the program input to one run of 'as'. The program may be in one or more
  1037. files; how the source is partitioned into files doesn't change the
  1038. meaning of the source.
  1039. The source program is a concatenation of the text in all the files,
  1040. in the order specified.
  1041. Each time you run 'as' it assembles exactly one source program. The
  1042. source program is made up of one or more files. (The standard input is
  1043. also a file.)
  1044. You give 'as' a command line that has zero or more input file names.
  1045. The input files are read (from left file name to right). A command line
  1046. argument (in any position) that has no special meaning is taken to be an
  1047. input file name.
  1048. If you give 'as' no file names it attempts to read one input file
  1049. from the 'as' standard input, which is normally your terminal. You may
  1050. have to type <ctl-D> to tell 'as' there is no more program to assemble.
  1051. Use '--' if you need to explicitly name the standard input file in
  1052. your command line.
  1053. If the source is empty, 'as' produces a small, empty object file.
  1054. Filenames and Line-numbers
  1055. --------------------------
  1056. There are two ways of locating a line in the input file (or files) and
  1057. either may be used in reporting error messages. One way refers to a
  1058. line number in a physical file; the other refers to a line number in a
  1059. "logical" file. *Note Error and Warning Messages: Errors.
  1060. "Physical files" are those files named in the command line given to
  1061. 'as'.
  1062. "Logical files" are simply names declared explicitly by assembler
  1063. directives; they bear no relation to physical files. Logical file names
  1064. help error messages reflect the original source file, when 'as' source
  1065. is itself synthesized from other files. 'as' understands the '#'
  1066. directives emitted by the 'gcc' preprocessor. See also *note '.file':
  1067. File.
  1068. 
  1069. File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview
  1070. 1.6 Output (Object) File
  1071. ========================
  1072. Every time you run 'as' it produces an output file, which is your
  1073. assembly language program translated into numbers. This file is the
  1074. object file. Its default name is 'a.out'. You can give it another name
  1075. by using the '-o' option. Conventionally, object file names end with
  1076. '.o'. The default name is used for historical reasons: older assemblers
  1077. were capable of assembling self-contained programs directly into a
  1078. runnable program. (For some formats, this isn't currently possible, but
  1079. it can be done for the 'a.out' format.)
  1080. The object file is meant for input to the linker 'ld'. It contains
  1081. assembled program code, information to help 'ld' integrate the assembled
  1082. program into a runnable file, and (optionally) symbolic information for
  1083. the debugger.
  1084. 
  1085. File: as.info, Node: Errors, Prev: Object, Up: Overview
  1086. 1.7 Error and Warning Messages
  1087. ==============================
  1088. 'as' may write warnings and error messages to the standard error file
  1089. (usually your terminal). This should not happen when a compiler runs
  1090. 'as' automatically. Warnings report an assumption made so that 'as'
  1091. could keep assembling a flawed program; errors report a grave problem
  1092. that stops the assembly.
  1093. Warning messages have the format
  1094. file_name:NNN:Warning Message Text
  1095. (where NNN is a line number). If both a logical file name (*note
  1096. '.file': File.) and a logical line number (*note '.line': Line.) have
  1097. been given then they will be used, otherwise the file name and line
  1098. number in the current assembler source file will be used. The message
  1099. text is intended to be self explanatory (in the grand Unix tradition).
  1100. Note the file name must be set via the logical version of the '.file'
  1101. directive, not the DWARF2 version of the '.file' directive. For
  1102. example:
  1103. .file 2 "bar.c"
  1104. error_assembler_source
  1105. .file "foo.c"
  1106. .line 30
  1107. error_c_source
  1108. produces this output:
  1109. Assembler messages:
  1110. asm.s:2: Error: no such instruction: `error_assembler_source'
  1111. foo.c:31: Error: no such instruction: `error_c_source'
  1112. Error messages have the format
  1113. file_name:NNN:FATAL:Error Message Text
  1114. The file name and line number are derived as for warning messages.
  1115. The actual message text may be rather less explanatory because many of
  1116. them aren't supposed to happen.
  1117. 
  1118. File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top
  1119. 2 Command-Line Options
  1120. **********************
  1121. This chapter describes command-line options available in _all_ versions
  1122. of the GNU assembler; see *note Machine Dependencies::, for options
  1123. specific to particular machine architectures.
  1124. If you are invoking 'as' via the GNU C compiler, you can use the
  1125. '-Wa' option to pass arguments through to the assembler. The assembler
  1126. arguments must be separated from each other (and the '-Wa') by commas.
  1127. For example:
  1128. gcc -c -g -O -Wa,-alh,-L file.c
  1129. This passes two options to the assembler: '-alh' (emit a listing to
  1130. standard output with high-level and assembly source) and '-L' (retain
  1131. local symbols in the symbol table).
  1132. Usually you do not need to use this '-Wa' mechanism, since many
  1133. compiler command-line options are automatically passed to the assembler
  1134. by the compiler. (You can call the GNU compiler driver with the '-v'
  1135. option to see precisely what options it passes to each compilation pass,
  1136. including the assembler.)
  1137. * Menu:
  1138. * a:: -a[cdghlns] enable listings
  1139. * alternate:: -alternate enable alternate macro syntax
  1140. * D:: -D for compatibility
  1141. * f:: -f to work faster
  1142. * I:: -I for .include search path
  1143. * K:: -K for difference tables
  1144. * L:: -L to retain local symbols
  1145. * listing:: -listing-XXX to configure listing output
  1146. * M:: -M or -mri to assemble in MRI compatibility mode
  1147. * MD:: -MD for dependency tracking
  1148. * no-pad-sections:: -no-pad-sections to stop section padding
  1149. * o:: -o to name the object file
  1150. * R:: -R to join data and text sections
  1151. * statistics:: -statistics to see statistics about assembly
  1152. * traditional-format:: -traditional-format for compatible output
  1153. * v:: -v to announce version
  1154. * W:: -W, -no-warn, -warn, -fatal-warnings to control warnings
  1155. * Z:: -Z to make object file even after errors
  1156. 
  1157. File: as.info, Node: a, Next: alternate, Up: Invoking
  1158. 2.1 Enable Listings: '-a[cdghlns]'
  1159. ==================================
  1160. These options enable listing output from the assembler. By itself, '-a'
  1161. requests high-level, assembly, and symbols listing. You can use other
  1162. letters to select specific options for the list: '-ah' requests a
  1163. high-level language listing, '-al' requests an output-program assembly
  1164. listing, and '-as' requests a symbol table listing. High-level listings
  1165. require that a compiler debugging option like '-g' be used, and that
  1166. assembly listings ('-al') be requested also.
  1167. Use the '-ag' option to print a first section with general assembly
  1168. information, like as version, switches passed, or time stamp.
  1169. Use the '-ac' option to omit false conditionals from a listing. Any
  1170. lines which are not assembled because of a false '.if' (or '.ifdef', or
  1171. any other conditional), or a true '.if' followed by an '.else', will be
  1172. omitted from the listing.
  1173. Use the '-ad' option to omit debugging directives from the listing.
  1174. Once you have specified one of these options, you can further control
  1175. listing output and its appearance using the directives '.list',
  1176. '.nolist', '.psize', '.eject', '.title', and '.sbttl'. The '-an' option
  1177. turns off all forms processing. If you do not request listing output
  1178. with one of the '-a' options, the listing-control directives have no
  1179. effect.
  1180. The letters after '-a' may be combined into one option, _e.g._,
  1181. '-aln'.
  1182. Note if the assembler source is coming from the standard input (e.g.,
  1183. because it is being created by 'gcc' and the '-pipe' command line switch
  1184. is being used) then the listing will not contain any comments or
  1185. preprocessor directives. This is because the listing code buffers input
  1186. source lines from stdin only after they have been preprocessed by the
  1187. assembler. This reduces memory usage and makes the code more efficient.
  1188. 
  1189. File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking
  1190. 2.2 '--alternate'
  1191. =================
  1192. Begin in alternate macro mode, see *note '.altmacro': Altmacro.
  1193. 
  1194. File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking
  1195. 2.3 '-D'
  1196. ========
  1197. This option has no effect whatsoever, but it is accepted to make it more
  1198. likely that scripts written for other assemblers also work with 'as'.
  1199. 
  1200. File: as.info, Node: f, Next: I, Prev: D, Up: Invoking
  1201. 2.4 Work Faster: '-f'
  1202. =====================
  1203. '-f' should only be used when assembling programs written by a (trusted)
  1204. compiler. '-f' stops the assembler from doing whitespace and comment
  1205. preprocessing on the input file(s) before assembling them. *Note
  1206. Preprocessing: Preprocessing.
  1207. _Warning:_ if you use '-f' when the files actually need to be
  1208. preprocessed (if they contain comments, for example), 'as' does not
  1209. work correctly.
  1210. 
  1211. File: as.info, Node: I, Next: K, Prev: f, Up: Invoking
  1212. 2.5 '.include' Search Path: '-I' PATH
  1213. =====================================
  1214. Use this option to add a PATH to the list of directories 'as' searches
  1215. for files specified in '.include' directives (*note '.include':
  1216. Include.). You may use '-I' as many times as necessary to include a
  1217. variety of paths. The current working directory is always searched
  1218. first; after that, 'as' searches any '-I' directories in the same order
  1219. as they were specified (left to right) on the command line.
  1220. 
  1221. File: as.info, Node: K, Next: L, Prev: I, Up: Invoking
  1222. 2.6 Difference Tables: '-K'
  1223. ===========================
  1224. 'as' sometimes alters the code emitted for directives of the form '.word
  1225. SYM1-SYM2'. *Note '.word': Word. You can use the '-K' option if you
  1226. want a warning issued when this is done.
  1227. 
  1228. File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking
  1229. 2.7 Include Local Symbols: '-L'
  1230. ===============================
  1231. Symbols beginning with system-specific local label prefixes, typically
  1232. '.L' for ELF systems or 'L' for traditional a.out systems, are called
  1233. "local symbols". *Note Symbol Names::. Normally you do not see such
  1234. symbols when debugging, because they are intended for the use of
  1235. programs (like compilers) that compose assembler programs, not for your
  1236. notice. Normally both 'as' and 'ld' discard such symbols, so you do not
  1237. normally debug with them.
  1238. This option tells 'as' to retain those local symbols in the object
  1239. file. Usually if you do this you also tell the linker 'ld' to preserve
  1240. those symbols.
  1241. 
  1242. File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking
  1243. 2.8 Configuring listing output: '--listing'
  1244. ===========================================
  1245. The listing feature of the assembler can be enabled via the command line
  1246. switch '-a' (*note a::). This feature combines the input source file(s)
  1247. with a hex dump of the corresponding locations in the output object
  1248. file, and displays them as a listing file. The format of this listing
  1249. can be controlled by directives inside the assembler source (i.e.,
  1250. '.list' (*note List::), '.title' (*note Title::), '.sbttl' (*note
  1251. Sbttl::), '.psize' (*note Psize::), and '.eject' (*note Eject::) and
  1252. also by the following switches:
  1253. '--listing-lhs-width='number''
  1254. Sets the maximum width, in words, of the first line of the hex byte
  1255. dump. This dump appears on the left hand side of the listing
  1256. output.
  1257. '--listing-lhs-width2='number''
  1258. Sets the maximum width, in words, of any further lines of the hex
  1259. byte dump for a given input source line. If this value is not
  1260. specified, it defaults to being the same as the value specified for
  1261. '--listing-lhs-width'. If neither switch is used the default is to
  1262. one.
  1263. '--listing-rhs-width='number''
  1264. Sets the maximum width, in characters, of the source line that is
  1265. displayed alongside the hex dump. The default value for this
  1266. parameter is 100. The source line is displayed on the right hand
  1267. side of the listing output.
  1268. '--listing-cont-lines='number''
  1269. Sets the maximum number of continuation lines of hex dump that will
  1270. be displayed for a given single line of source input. The default
  1271. value is 4.
  1272. 
  1273. File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking
  1274. 2.9 Assemble in MRI Compatibility Mode: '-M'
  1275. ============================================
  1276. The '-M' or '--mri' option selects MRI compatibility mode. This changes
  1277. the syntax and pseudo-op handling of 'as' to make it compatible with the
  1278. 'ASM68K' or the 'ASM960' (depending upon the configured target)
  1279. assembler from Microtec Research. The exact nature of the MRI syntax
  1280. will not be documented here; see the MRI manuals for more information.
  1281. Note in particular that the handling of macros and macro arguments is
  1282. somewhat different. The purpose of this option is to permit assembling
  1283. existing MRI assembler code using 'as'.
  1284. The MRI compatibility is not complete. Certain operations of the MRI
  1285. assembler depend upon its object file format, and can not be supported
  1286. using other object file formats. Supporting these would require
  1287. enhancing each object file format individually. These are:
  1288. * global symbols in common section
  1289. The m68k MRI assembler supports common sections which are merged by
  1290. the linker. Other object file formats do not support this. 'as'
  1291. handles common sections by treating them as a single common symbol.
  1292. It permits local symbols to be defined within a common section, but
  1293. it can not support global symbols, since it has no way to describe
  1294. them.
  1295. * complex relocations
  1296. The MRI assemblers support relocations against a negated section
  1297. address, and relocations which combine the start addresses of two
  1298. or more sections. These are not support by other object file
  1299. formats.
  1300. * 'END' pseudo-op specifying start address
  1301. The MRI 'END' pseudo-op permits the specification of a start
  1302. address. This is not supported by other object file formats. The
  1303. start address may instead be specified using the '-e' option to the
  1304. linker, or in a linker script.
  1305. * 'IDNT', '.ident' and 'NAME' pseudo-ops
  1306. The MRI 'IDNT', '.ident' and 'NAME' pseudo-ops assign a module name
  1307. to the output file. This is not supported by other object file
  1308. formats.
  1309. * 'ORG' pseudo-op
  1310. The m68k MRI 'ORG' pseudo-op begins an absolute section at a given
  1311. address. This differs from the usual 'as' '.org' pseudo-op, which
  1312. changes the location within the current section. Absolute sections
  1313. are not supported by other object file formats. The address of a
  1314. section may be assigned within a linker script.
  1315. There are some other features of the MRI assembler which are not
  1316. supported by 'as', typically either because they are difficult or
  1317. because they seem of little consequence. Some of these may be supported
  1318. in future releases.
  1319. * EBCDIC strings
  1320. EBCDIC strings are not supported.
  1321. * packed binary coded decimal
  1322. Packed binary coded decimal is not supported. This means that the
  1323. 'DC.P' and 'DCB.P' pseudo-ops are not supported.
  1324. * 'FEQU' pseudo-op
  1325. The m68k 'FEQU' pseudo-op is not supported.
  1326. * 'NOOBJ' pseudo-op
  1327. The m68k 'NOOBJ' pseudo-op is not supported.
  1328. * 'OPT' branch control options
  1329. The m68k 'OPT' branch control options--'B', 'BRS', 'BRB', 'BRL',
  1330. and 'BRW'--are ignored. 'as' automatically relaxes all branches,
  1331. whether forward or backward, to an appropriate size, so these
  1332. options serve no purpose.
  1333. * 'OPT' list control options
  1334. The following m68k 'OPT' list control options are ignored: 'C',
  1335. 'CEX', 'CL', 'CRE', 'E', 'G', 'I', 'M', 'MEX', 'MC', 'MD', 'X'.
  1336. * other 'OPT' options
  1337. The following m68k 'OPT' options are ignored: 'NEST', 'O', 'OLD',
  1338. 'OP', 'P', 'PCO', 'PCR', 'PCS', 'R'.
  1339. * 'OPT' 'D' option is default
  1340. The m68k 'OPT' 'D' option is the default, unlike the MRI assembler.
  1341. 'OPT NOD' may be used to turn it off.
  1342. * 'XREF' pseudo-op.
  1343. The m68k 'XREF' pseudo-op is ignored.
  1344. * '.debug' pseudo-op
  1345. The i960 '.debug' pseudo-op is not supported.
  1346. * '.extended' pseudo-op
  1347. The i960 '.extended' pseudo-op is not supported.
  1348. * '.list' pseudo-op.
  1349. The various options of the i960 '.list' pseudo-op are not
  1350. supported.
  1351. * '.optimize' pseudo-op
  1352. The i960 '.optimize' pseudo-op is not supported.
  1353. * '.output' pseudo-op
  1354. The i960 '.output' pseudo-op is not supported.
  1355. * '.setreal' pseudo-op
  1356. The i960 '.setreal' pseudo-op is not supported.
  1357. 
  1358. File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking
  1359. 2.10 Dependency Tracking: '--MD'
  1360. ================================
  1361. 'as' can generate a dependency file for the file it creates. This file
  1362. consists of a single rule suitable for 'make' describing the
  1363. dependencies of the main source file.
  1364. The rule is written to the file named in its argument.
  1365. This feature is used in the automatic updating of makefiles.
  1366. 
  1367. File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking
  1368. 2.11 Output Section Padding
  1369. ===========================
  1370. Normally the assembler will pad the end of each output section up to its
  1371. alignment boundary. But this can waste space, which can be significant
  1372. on memory constrained targets. So the '--no-pad-sections' option will
  1373. disable this behaviour.
  1374. 
  1375. File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking
  1376. 2.12 Name the Object File: '-o'
  1377. ===============================
  1378. There is always one object file output when you run 'as'. By default it
  1379. has the name 'a.out' (or 'b.out', for Intel 960 targets only). You use
  1380. this option (which takes exactly one filename) to give the object file a
  1381. different name.
  1382. Whatever the object file is called, 'as' overwrites any existing file
  1383. of the same name.
  1384. 
  1385. File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking
  1386. 2.13 Join Data and Text Sections: '-R'
  1387. ======================================
  1388. '-R' tells 'as' to write the object file as if all data-section data
  1389. lives in the text section. This is only done at the very last moment:
  1390. your binary data are the same, but data section parts are relocated
  1391. differently. The data section part of your object file is zero bytes
  1392. long because all its bytes are appended to the text section. (*Note
  1393. Sections and Relocation: Sections.)
  1394. When you specify '-R' it would be possible to generate shorter
  1395. address displacements (because we do not have to cross between text and
  1396. data section). We refrain from doing this simply for compatibility with
  1397. older versions of 'as'. In future, '-R' may work this way.
  1398. When 'as' is configured for COFF or ELF output, this option is only
  1399. useful if you use sections named '.text' and '.data'.
  1400. '-R' is not supported for any of the HPPA targets. Using '-R'
  1401. generates a warning from 'as'.
  1402. 
  1403. File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking
  1404. 2.14 Display Assembly Statistics: '--statistics'
  1405. ================================================
  1406. Use '--statistics' to display two statistics about the resources used by
  1407. 'as': the maximum amount of space allocated during the assembly (in
  1408. bytes), and the total execution time taken for the assembly (in CPU
  1409. seconds).
  1410. 
  1411. File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking
  1412. 2.15 Compatible Output: '--traditional-format'
  1413. ==============================================
  1414. For some targets, the output of 'as' is different in some ways from the
  1415. output of some existing assembler. This switch requests 'as' to use the
  1416. traditional format instead.
  1417. For example, it disables the exception frame optimizations which 'as'
  1418. normally does by default on 'gcc' output.
  1419. 
  1420. File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking
  1421. 2.16 Announce Version: '-v'
  1422. ===========================
  1423. You can find out what version of as is running by including the option
  1424. '-v' (which you can also spell as '-version') on the command line.
  1425. 
  1426. File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking
  1427. 2.17 Control Warnings: '-W', '--warn', '--no-warn', '--fatal-warnings'
  1428. ======================================================================
  1429. 'as' should never give a warning or error message when assembling
  1430. compiler output. But programs written by people often cause 'as' to
  1431. give a warning that a particular assumption was made. All such warnings
  1432. are directed to the standard error file.
  1433. If you use the '-W' and '--no-warn' options, no warnings are issued.
  1434. This only affects the warning messages: it does not change any
  1435. particular of how 'as' assembles your file. Errors, which stop the
  1436. assembly, are still reported.
  1437. If you use the '--fatal-warnings' option, 'as' considers files that
  1438. generate warnings to be in error.
  1439. You can switch these options off again by specifying '--warn', which
  1440. causes warnings to be output as usual.
  1441. 
  1442. File: as.info, Node: Z, Prev: W, Up: Invoking
  1443. 2.18 Generate Object File in Spite of Errors: '-Z'
  1444. ==================================================
  1445. After an error message, 'as' normally produces no output. If for some
  1446. reason you are interested in object file output even after 'as' gives an
  1447. error message on your program, use the '-Z' option. If there are any
  1448. errors, 'as' continues anyways, and writes an object file after a final
  1449. warning message of the form 'N errors, M warnings, generating bad object
  1450. file.'
  1451. 
  1452. File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top
  1453. 3 Syntax
  1454. ********
  1455. This chapter describes the machine-independent syntax allowed in a
  1456. source file. 'as' syntax is similar to what many other assemblers use;
  1457. it is inspired by the BSD 4.2 assembler, except that 'as' does not
  1458. assemble Vax bit-fields.
  1459. * Menu:
  1460. * Preprocessing:: Preprocessing
  1461. * Whitespace:: Whitespace
  1462. * Comments:: Comments
  1463. * Symbol Intro:: Symbols
  1464. * Statements:: Statements
  1465. * Constants:: Constants
  1466. 
  1467. File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax
  1468. 3.1 Preprocessing
  1469. =================
  1470. The 'as' internal preprocessor:
  1471. * adjusts and removes extra whitespace. It leaves one space or tab
  1472. before the keywords on a line, and turns any other whitespace on
  1473. the line into a single space.
  1474. * removes all comments, replacing them with a single space, or an
  1475. appropriate number of newlines.
  1476. * converts character constants into the appropriate numeric values.
  1477. It does not do macro processing, include file handling, or anything
  1478. else you may get from your C compiler's preprocessor. You can do
  1479. include file processing with the '.include' directive (*note '.include':
  1480. Include.). You can use the GNU C compiler driver to get other "CPP"
  1481. style preprocessing by giving the input file a '.S' suffix. *Note
  1482. Options Controlling the Kind of Output: (gcc info)Overall Options.
  1483. Excess whitespace, comments, and character constants cannot be used
  1484. in the portions of the input text that are not preprocessed.
  1485. If the first line of an input file is '#NO_APP' or if you use the
  1486. '-f' option, whitespace and comments are not removed from the input
  1487. file. Within an input file, you can ask for whitespace and comment
  1488. removal in specific portions of the by putting a line that says '#APP'
  1489. before the text that may contain whitespace or comments, and putting a
  1490. line that says '#NO_APP' after this text. This feature is mainly intend
  1491. to support 'asm' statements in compilers whose output is otherwise free
  1492. of comments and whitespace.
  1493. 
  1494. File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax
  1495. 3.2 Whitespace
  1496. ==============
  1497. "Whitespace" is one or more blanks or tabs, in any order. Whitespace is
  1498. used to separate symbols, and to make programs neater for people to
  1499. read. Unless within character constants (*note Character Constants:
  1500. Characters.), any whitespace means the same as exactly one space.
  1501. 
  1502. File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax
  1503. 3.3 Comments
  1504. ============
  1505. There are two ways of rendering comments to 'as'. In both cases the
  1506. comment is equivalent to one space.
  1507. Anything from '/*' through the next '*/' is a comment. This means
  1508. you may not nest these comments.
  1509. /*
  1510. The only way to include a newline ('\n') in a comment
  1511. is to use this sort of comment.
  1512. */
  1513. /* This sort of comment does not nest. */
  1514. Anything from a "line comment" character up to the next newline is
  1515. considered a comment and is ignored. The line comment character is
  1516. target specific, and some targets multiple comment characters. Some
  1517. targets also have line comment characters that only work if they are the
  1518. first character on a line. Some targets use a sequence of two
  1519. characters to introduce a line comment. Some targets can also change
  1520. their line comment characters depending upon command line options that
  1521. have been used. For more details see the _Syntax_ section in the
  1522. documentation for individual targets.
  1523. If the line comment character is the hash sign ('#') then it still
  1524. has the special ability to enable and disable preprocessing (*note
  1525. Preprocessing::) and to specify logical line numbers:
  1526. To be compatible with past assemblers, lines that begin with '#' have
  1527. a special interpretation. Following the '#' should be an absolute
  1528. expression (*note Expressions::): the logical line number of the _next_
  1529. line. Then a string (*note Strings: Strings.) is allowed: if present it
  1530. is a new logical file name. The rest of the line, if any, should be
  1531. whitespace.
  1532. If the first non-whitespace characters on the line are not numeric,
  1533. the line is ignored. (Just like a comment.)
  1534. # This is an ordinary comment.
  1535. # 42-6 "new_file_name" # New logical file name
  1536. # This is logical line # 36.
  1537. This feature is deprecated, and may disappear from future versions of
  1538. 'as'.
  1539. 
  1540. File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax
  1541. 3.4 Symbols
  1542. ===========
  1543. A "symbol" is one or more characters chosen from the set of all letters
  1544. (both upper and lower case), digits and the three characters '_.$'. On
  1545. most machines, you can also use '$' in symbol names; exceptions are
  1546. noted in *note Machine Dependencies::. No symbol may begin with a
  1547. digit. Case is significant. There is no length limit; all characters
  1548. are significant. Multibyte characters are supported. Symbols are
  1549. delimited by characters not in that set, or by the beginning of a file
  1550. (since the source program must end with a newline, the end of a file is
  1551. not a possible symbol delimiter). *Note Symbols::.
  1552. Symbol names may also be enclosed in double quote '"' characters. In
  1553. such cases any characters are allowed, except for the NUL character. If
  1554. a double quote character is to be included in the symbol name it must be
  1555. preceeded by a backslash '\' character.
  1556. 
  1557. File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax
  1558. 3.5 Statements
  1559. ==============
  1560. A "statement" ends at a newline character ('\n') or a "line separator
  1561. character". The line separator character is target specific and
  1562. described in the _Syntax_ section of each target's documentation. Not
  1563. all targets support a line separator character. The newline or line
  1564. separator character is considered to be part of the preceding statement.
  1565. Newlines and separators within character constants are an exception:
  1566. they do not end statements.
  1567. It is an error to end any statement with end-of-file: the last
  1568. character of any input file should be a newline.
  1569. An empty statement is allowed, and may include whitespace. It is
  1570. ignored.
  1571. A statement begins with zero or more labels, optionally followed by a
  1572. key symbol which determines what kind of statement it is. The key
  1573. symbol determines the syntax of the rest of the statement. If the
  1574. symbol begins with a dot '.' then the statement is an assembler
  1575. directive: typically valid for any computer. If the symbol begins with
  1576. a letter the statement is an assembly language "instruction": it
  1577. assembles into a machine language instruction. Different versions of
  1578. 'as' for different computers recognize different instructions. In fact,
  1579. the same symbol may represent a different instruction in a different
  1580. computer's assembly language.
  1581. A label is a symbol immediately followed by a colon (':').
  1582. Whitespace before a label or after a colon is permitted, but you may not
  1583. have whitespace between a label's symbol and its colon. *Note Labels::.
  1584. For HPPA targets, labels need not be immediately followed by a colon,
  1585. but the definition of a label must begin in column zero. This also
  1586. implies that only one label may be defined on each line.
  1587. label: .directive followed by something
  1588. another_label: # This is an empty statement.
  1589. instruction operand_1, operand_2, ...
  1590. 
  1591. File: as.info, Node: Constants, Prev: Statements, Up: Syntax
  1592. 3.6 Constants
  1593. =============
  1594. A constant is a number, written so that its value is known by
  1595. inspection, without knowing any context. Like this:
  1596. .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
  1597. .ascii "Ring the bell\7" # A string constant.
  1598. .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum.
  1599. .float 0f-314159265358979323846264338327\
  1600. 95028841971.693993751E-40 # - pi, a flonum.
  1601. * Menu:
  1602. * Characters:: Character Constants
  1603. * Numbers:: Number Constants
  1604. 
  1605. File: as.info, Node: Characters, Next: Numbers, Up: Constants
  1606. 3.6.1 Character Constants
  1607. -------------------------
  1608. There are two kinds of character constants. A "character" stands for
  1609. one character in one byte and its value may be used in numeric
  1610. expressions. String constants (properly called string _literals_) are
  1611. potentially many bytes and their values may not be used in arithmetic
  1612. expressions.
  1613. * Menu:
  1614. * Strings:: Strings
  1615. * Chars:: Characters
  1616. 
  1617. File: as.info, Node: Strings, Next: Chars, Up: Characters
  1618. 3.6.1.1 Strings
  1619. ...............
  1620. A "string" is written between double-quotes. It may contain
  1621. double-quotes or null characters. The way to get special characters
  1622. into a string is to "escape" these characters: precede them with a
  1623. backslash '\' character. For example '\\' represents one backslash: the
  1624. first '\' is an escape which tells 'as' to interpret the second
  1625. character literally as a backslash (which prevents 'as' from recognizing
  1626. the second '\' as an escape character). The complete list of escapes
  1627. follows.
  1628. '\b'
  1629. Mnemonic for backspace; for ASCII this is octal code 010.
  1630. 'backslash-f'
  1631. Mnemonic for FormFeed; for ASCII this is octal code 014.
  1632. '\n'
  1633. Mnemonic for newline; for ASCII this is octal code 012.
  1634. '\r'
  1635. Mnemonic for carriage-Return; for ASCII this is octal code 015.
  1636. '\t'
  1637. Mnemonic for horizontal Tab; for ASCII this is octal code 011.
  1638. '\ DIGIT DIGIT DIGIT'
  1639. An octal character code. The numeric code is 3 octal digits. For
  1640. compatibility with other Unix systems, 8 and 9 are accepted as
  1641. digits: for example, '\008' has the value 010, and '\009' the value
  1642. 011.
  1643. '\x HEX-DIGITS...'
  1644. A hex character code. All trailing hex digits are combined.
  1645. Either upper or lower case 'x' works.
  1646. '\\'
  1647. Represents one '\' character.
  1648. '\"'
  1649. Represents one '"' character. Needed in strings to represent this
  1650. character, because an unescaped '"' would end the string.
  1651. '\ ANYTHING-ELSE'
  1652. Any other character when escaped by '\' gives a warning, but
  1653. assembles as if the '\' was not present. The idea is that if you
  1654. used an escape sequence you clearly didn't want the literal
  1655. interpretation of the following character. However 'as' has no
  1656. other interpretation, so 'as' knows it is giving you the wrong code
  1657. and warns you of the fact.
  1658. Which characters are escapable, and what those escapes represent,
  1659. varies widely among assemblers. The current set is what we think the
  1660. BSD 4.2 assembler recognizes, and is a subset of what most C compilers
  1661. recognize. If you are in doubt, do not use an escape sequence.
  1662. 
  1663. File: as.info, Node: Chars, Prev: Strings, Up: Characters
  1664. 3.6.1.2 Characters
  1665. ..................
  1666. A single character may be written as a single quote immediately followed
  1667. by that character. Some backslash escapes apply to characters, '\b',
  1668. '\f', '\n', '\r', '\t', and '\"' with the same meaning as for strings,
  1669. plus '\'' for a single quote. So if you want to write the character
  1670. backslash, you must write ''\\' where the first '\' escapes the second
  1671. '\'. As you can see, the quote is an acute accent, not a grave accent.
  1672. A newline immediately following an acute accent is taken as a literal
  1673. character and does not count as the end of a statement. The value of a
  1674. character constant in a numeric expression is the machine's byte-wide
  1675. code for that character. 'as' assumes your character code is ASCII:
  1676. ''A' means 65, ''B' means 66, and so on.
  1677. 
  1678. File: as.info, Node: Numbers, Prev: Characters, Up: Constants
  1679. 3.6.2 Number Constants
  1680. ----------------------
  1681. 'as' distinguishes three kinds of numbers according to how they are
  1682. stored in the target machine. _Integers_ are numbers that would fit
  1683. into an 'int' in the C language. _Bignums_ are integers, but they are
  1684. stored in more than 32 bits. _Flonums_ are floating point numbers,
  1685. described below.
  1686. * Menu:
  1687. * Integers:: Integers
  1688. * Bignums:: Bignums
  1689. * Flonums:: Flonums
  1690. 
  1691. File: as.info, Node: Integers, Next: Bignums, Up: Numbers
  1692. 3.6.2.1 Integers
  1693. ................
  1694. A binary integer is '0b' or '0B' followed by zero or more of the binary
  1695. digits '01'.
  1696. An octal integer is '0' followed by zero or more of the octal digits
  1697. ('01234567').
  1698. A decimal integer starts with a non-zero digit followed by zero or
  1699. more digits ('0123456789').
  1700. A hexadecimal integer is '0x' or '0X' followed by one or more
  1701. hexadecimal digits chosen from '0123456789abcdefABCDEF'.
  1702. Integers have the usual values. To denote a negative integer, use
  1703. the prefix operator '-' discussed under expressions (*note Prefix
  1704. Operators: Prefix Ops.).
  1705. 
  1706. File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers
  1707. 3.6.2.2 Bignums
  1708. ...............
  1709. A "bignum" has the same syntax and semantics as an integer except that
  1710. the number (or its negative) takes more than 32 bits to represent in
  1711. binary. The distinction is made because in some places integers are
  1712. permitted while bignums are not.
  1713. 
  1714. File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers
  1715. 3.6.2.3 Flonums
  1716. ...............
  1717. A "flonum" represents a floating point number. The translation is
  1718. indirect: a decimal floating point number from the text is converted by
  1719. 'as' to a generic binary floating point number of more than sufficient
  1720. precision. This generic floating point number is converted to a
  1721. particular computer's floating point format (or formats) by a portion of
  1722. 'as' specialized to that computer.
  1723. A flonum is written by writing (in order)
  1724. * The digit '0'. ('0' is optional on the HPPA.)
  1725. * A letter, to tell 'as' the rest of the number is a flonum. 'e' is
  1726. recommended. Case is not important.
  1727. On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
  1728. letter must be one of the letters 'DFPRSX' (in upper or lower
  1729. case).
  1730. On the ARC, the letter must be one of the letters 'DFRS' (in upper
  1731. or lower case).
  1732. On the Intel 960 architecture, the letter must be one of the
  1733. letters 'DFT' (in upper or lower case).
  1734. On the HPPA architecture, the letter must be 'E' (upper case only).
  1735. * An optional sign: either '+' or '-'.
  1736. * An optional "integer part": zero or more decimal digits.
  1737. * An optional "fractional part": '.' followed by zero or more decimal
  1738. digits.
  1739. * An optional exponent, consisting of:
  1740. * An 'E' or 'e'.
  1741. * Optional sign: either '+' or '-'.
  1742. * One or more decimal digits.
  1743. At least one of the integer part or the fractional part must be
  1744. present. The floating point number has the usual base-10 value.
  1745. 'as' does all processing using integers. Flonums are computed
  1746. independently of any floating point hardware in the computer running
  1747. 'as'.
  1748. 
  1749. File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top
  1750. 4 Sections and Relocation
  1751. *************************
  1752. * Menu:
  1753. * Secs Background:: Background
  1754. * Ld Sections:: Linker Sections
  1755. * As Sections:: Assembler Internal Sections
  1756. * Sub-Sections:: Sub-Sections
  1757. * bss:: bss Section
  1758. 
  1759. File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections
  1760. 4.1 Background
  1761. ==============
  1762. Roughly, a section is a range of addresses, with no gaps; all data "in"
  1763. those addresses is treated the same for some particular purpose. For
  1764. example there may be a "read only" section.
  1765. The linker 'ld' reads many object files (partial programs) and
  1766. combines their contents to form a runnable program. When 'as' emits an
  1767. object file, the partial program is assumed to start at address 0. 'ld'
  1768. assigns the final addresses for the partial program, so that different
  1769. partial programs do not overlap. This is actually an
  1770. oversimplification, but it suffices to explain how 'as' uses sections.
  1771. 'ld' moves blocks of bytes of your program to their run-time
  1772. addresses. These blocks slide to their run-time addresses as rigid
  1773. units; their length does not change and neither does the order of bytes
  1774. within them. Such a rigid unit is called a _section_. Assigning
  1775. run-time addresses to sections is called "relocation". It includes the
  1776. task of adjusting mentions of object-file addresses so they refer to the
  1777. proper run-time addresses. For the H8/300, and for the Renesas / SuperH
  1778. SH, 'as' pads sections if needed to ensure they end on a word (sixteen
  1779. bit) boundary.
  1780. An object file written by 'as' has at least three sections, any of
  1781. which may be empty. These are named "text", "data" and "bss" sections.
  1782. When it generates COFF or ELF output, 'as' can also generate whatever
  1783. other named sections you specify using the '.section' directive (*note
  1784. '.section': Section.). If you do not use any directives that place
  1785. output in the '.text' or '.data' sections, these sections still exist,
  1786. but are empty.
  1787. When 'as' generates SOM or ELF output for the HPPA, 'as' can also
  1788. generate whatever other named sections you specify using the '.space'
  1789. and '.subspace' directives. See 'HP9000 Series 800 Assembly Language
  1790. Reference Manual' (HP 92432-90001) for details on the '.space' and
  1791. '.subspace' assembler directives.
  1792. Additionally, 'as' uses different names for the standard text, data,
  1793. and bss sections when generating SOM output. Program text is placed
  1794. into the '$CODE$' section, data into '$DATA$', and BSS into '$BSS$'.
  1795. Within the object file, the text section starts at address '0', the
  1796. data section follows, and the bss section follows the data section.
  1797. When generating either SOM or ELF output files on the HPPA, the text
  1798. section starts at address '0', the data section at address '0x4000000',
  1799. and the bss section follows the data section.
  1800. To let 'ld' know which data changes when the sections are relocated,
  1801. and how to change that data, 'as' also writes to the object file details
  1802. of the relocation needed. To perform relocation 'ld' must know, each
  1803. time an address in the object file is mentioned:
  1804. * Where in the object file is the beginning of this reference to an
  1805. address?
  1806. * How long (in bytes) is this reference?
  1807. * Which section does the address refer to? What is the numeric value
  1808. of
  1809. (ADDRESS) - (START-ADDRESS OF SECTION)?
  1810. * Is the reference to an address "Program-Counter relative"?
  1811. In fact, every address 'as' ever uses is expressed as
  1812. (SECTION) + (OFFSET INTO SECTION)
  1813. Further, most expressions 'as' computes have this section-relative
  1814. nature. (For some object formats, such as SOM for the HPPA, some
  1815. expressions are symbol-relative instead.)
  1816. In this manual we use the notation {SECNAME N} to mean "offset N into
  1817. section SECNAME."
  1818. Apart from text, data and bss sections you need to know about the
  1819. "absolute" section. When 'ld' mixes partial programs, addresses in the
  1820. absolute section remain unchanged. For example, address '{absolute 0}'
  1821. is "relocated" to run-time address 0 by 'ld'. Although the linker never
  1822. arranges two partial programs' data sections with overlapping addresses
  1823. after linking, _by definition_ their absolute sections must overlap.
  1824. Address '{absolute 239}' in one part of a program is always the same
  1825. address when the program is running as address '{absolute 239}' in any
  1826. other part of the program.
  1827. The idea of sections is extended to the "undefined" section. Any
  1828. address whose section is unknown at assembly time is by definition
  1829. rendered {undefined U}--where U is filled in later. Since numbers are
  1830. always defined, the only way to generate an undefined address is to
  1831. mention an undefined symbol. A reference to a named common block would
  1832. be such a symbol: its value is unknown at assembly time so it has
  1833. section _undefined_.
  1834. By analogy the word _section_ is used to describe groups of sections
  1835. in the linked program. 'ld' puts all partial programs' text sections in
  1836. contiguous addresses in the linked program. It is customary to refer to
  1837. the _text section_ of a program, meaning all the addresses of all
  1838. partial programs' text sections. Likewise for data and bss sections.
  1839. Some sections are manipulated by 'ld'; others are invented for use of
  1840. 'as' and have no meaning except during assembly.
  1841. 
  1842. File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections
  1843. 4.2 Linker Sections
  1844. ===================
  1845. 'ld' deals with just four kinds of sections, summarized below.
  1846. *named sections*
  1847. *text section*
  1848. *data section*
  1849. These sections hold your program. 'as' and 'ld' treat them as
  1850. separate but equal sections. Anything you can say of one section
  1851. is true of another. When the program is running, however, it is
  1852. customary for the text section to be unalterable. The text section
  1853. is often shared among processes: it contains instructions,
  1854. constants and the like. The data section of a running program is
  1855. usually alterable: for example, C variables would be stored in the
  1856. data section.
  1857. *bss section*
  1858. This section contains zeroed bytes when your program begins
  1859. running. It is used to hold uninitialized variables or common
  1860. storage. The length of each partial program's bss section is
  1861. important, but because it starts out containing zeroed bytes there
  1862. is no need to store explicit zero bytes in the object file. The
  1863. bss section was invented to eliminate those explicit zeros from
  1864. object files.
  1865. *absolute section*
  1866. Address 0 of this section is always "relocated" to runtime address
  1867. 0. This is useful if you want to refer to an address that 'ld'
  1868. must not change when relocating. In this sense we speak of
  1869. absolute addresses being "unrelocatable": they do not change during
  1870. relocation.
  1871. *undefined section*
  1872. This "section" is a catch-all for address references to objects not
  1873. in the preceding sections.
  1874. An idealized example of three relocatable sections follows. The
  1875. example uses the traditional section names '.text' and '.data'. Memory
  1876. addresses are on the horizontal axis.
  1877. +-----+----+--+
  1878. partial program # 1: |ttttt|dddd|00|
  1879. +-----+----+--+
  1880. text data bss
  1881. seg. seg. seg.
  1882. +---+---+---+
  1883. partial program # 2: |TTT|DDD|000|
  1884. +---+---+---+
  1885. +--+---+-----+--+----+---+-----+~~
  1886. linked program: | |TTT|ttttt| |dddd|DDD|00000|
  1887. +--+---+-----+--+----+---+-----+~~
  1888. addresses: 0 ...
  1889. 
  1890. File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections
  1891. 4.3 Assembler Internal Sections
  1892. ===============================
  1893. These sections are meant only for the internal use of 'as'. They have
  1894. no meaning at run-time. You do not really need to know about these
  1895. sections for most purposes; but they can be mentioned in 'as' warning
  1896. messages, so it might be helpful to have an idea of their meanings to
  1897. 'as'. These sections are used to permit the value of every expression
  1898. in your assembly language program to be a section-relative address.
  1899. ASSEMBLER-INTERNAL-LOGIC-ERROR!
  1900. An internal assembler logic error has been found. This means there
  1901. is a bug in the assembler.
  1902. expr section
  1903. The assembler stores complex expression internally as combinations
  1904. of symbols. When it needs to represent an expression as a symbol,
  1905. it puts it in the expr section.
  1906. 
  1907. File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections
  1908. 4.4 Sub-Sections
  1909. ================
  1910. Assembled bytes conventionally fall into two sections: text and data.
  1911. You may have separate groups of data in named sections that you want to
  1912. end up near to each other in the object file, even though they are not
  1913. contiguous in the assembler source. 'as' allows you to use
  1914. "subsections" for this purpose. Within each section, there can be
  1915. numbered subsections with values from 0 to 8192. Objects assembled into
  1916. the same subsection go into the object file together with other objects
  1917. in the same subsection. For example, a compiler might want to store
  1918. constants in the text section, but might not want to have them
  1919. interspersed with the program being assembled. In this case, the
  1920. compiler could issue a '.text 0' before each section of code being
  1921. output, and a '.text 1' before each group of constants being output.
  1922. Subsections are optional. If you do not use subsections, everything
  1923. goes in subsection number zero.
  1924. Each subsection is zero-padded up to a multiple of four bytes.
  1925. (Subsections may be padded a different amount on different flavors of
  1926. 'as'.)
  1927. Subsections appear in your object file in numeric order, lowest
  1928. numbered to highest. (All this to be compatible with other people's
  1929. assemblers.) The object file contains no representation of subsections;
  1930. 'ld' and other programs that manipulate object files see no trace of
  1931. them. They just see all your text subsections as a text section, and
  1932. all your data subsections as a data section.
  1933. To specify which subsection you want subsequent statements assembled
  1934. into, use a numeric argument to specify it, in a '.text EXPRESSION' or a
  1935. '.data EXPRESSION' statement. When generating COFF output, you can also
  1936. use an extra subsection argument with arbitrary named sections:
  1937. '.section NAME, EXPRESSION'. When generating ELF output, you can also
  1938. use the '.subsection' directive (*note SubSection::) to specify a
  1939. subsection: '.subsection EXPRESSION'. EXPRESSION should be an absolute
  1940. expression (*note Expressions::). If you just say '.text' then '.text
  1941. 0' is assumed. Likewise '.data' means '.data 0'. Assembly begins in
  1942. 'text 0'. For instance:
  1943. .text 0 # The default subsection is text 0 anyway.
  1944. .ascii "This lives in the first text subsection. *"
  1945. .text 1
  1946. .ascii "But this lives in the second text subsection."
  1947. .data 0
  1948. .ascii "This lives in the data section,"
  1949. .ascii "in the first data subsection."
  1950. .text 0
  1951. .ascii "This lives in the first text section,"
  1952. .ascii "immediately following the asterisk (*)."
  1953. Each section has a "location counter" incremented by one for every
  1954. byte assembled into that section. Because subsections are merely a
  1955. convenience restricted to 'as' there is no concept of a subsection
  1956. location counter. There is no way to directly manipulate a location
  1957. counter--but the '.align' directive changes it, and any label definition
  1958. captures its current value. The location counter of the section where
  1959. statements are being assembled is said to be the "active" location
  1960. counter.
  1961. 
  1962. File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections
  1963. 4.5 bss Section
  1964. ===============
  1965. The bss section is used for local common variable storage. You may
  1966. allocate address space in the bss section, but you may not dictate data
  1967. to load into it before your program executes. When your program starts
  1968. running, all the contents of the bss section are zeroed bytes.
  1969. The '.lcomm' pseudo-op defines a symbol in the bss section; see *note
  1970. '.lcomm': Lcomm.
  1971. The '.comm' pseudo-op may be used to declare a common symbol, which
  1972. is another form of uninitialized symbol; see *note '.comm': Comm.
  1973. When assembling for a target which supports multiple sections, such
  1974. as ELF or COFF, you may switch into the '.bss' section and define
  1975. symbols as usual; see *note '.section': Section. You may only assemble
  1976. zero values into the section. Typically the section will only contain
  1977. symbol definitions and '.skip' directives (*note '.skip': Skip.).
  1978. 
  1979. File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top
  1980. 5 Symbols
  1981. *********
  1982. Symbols are a central concept: the programmer uses symbols to name
  1983. things, the linker uses symbols to link, and the debugger uses symbols
  1984. to debug.
  1985. _Warning:_ 'as' does not place symbols in the object file in the
  1986. same order they were declared. This may break some debuggers.
  1987. * Menu:
  1988. * Labels:: Labels
  1989. * Setting Symbols:: Giving Symbols Other Values
  1990. * Symbol Names:: Symbol Names
  1991. * Dot:: The Special Dot Symbol
  1992. * Symbol Attributes:: Symbol Attributes
  1993. 
  1994. File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols
  1995. 5.1 Labels
  1996. ==========
  1997. A "label" is written as a symbol immediately followed by a colon ':'.
  1998. The symbol then represents the current value of the active location
  1999. counter, and is, for example, a suitable instruction operand. You are
  2000. warned if you use the same symbol to represent two different locations:
  2001. the first definition overrides any other definitions.
  2002. On the HPPA, the usual form for a label need not be immediately
  2003. followed by a colon, but instead must start in column zero. Only one
  2004. label may be defined on a single line. To work around this, the HPPA
  2005. version of 'as' also provides a special directive '.label' for defining
  2006. labels more flexibly.
  2007. 
  2008. File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols
  2009. 5.2 Giving Symbols Other Values
  2010. ===============================
  2011. A symbol can be given an arbitrary value by writing a symbol, followed
  2012. by an equals sign '=', followed by an expression (*note Expressions::).
  2013. This is equivalent to using the '.set' directive. *Note '.set': Set.
  2014. In the same way, using a double equals sign '=''=' here represents an
  2015. equivalent of the '.eqv' directive. *Note '.eqv': Eqv.
  2016. Blackfin does not support symbol assignment with '='.
  2017. 
  2018. File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols
  2019. 5.3 Symbol Names
  2020. ================
  2021. Symbol names begin with a letter or with one of '._'. On most machines,
  2022. you can also use '$' in symbol names; exceptions are noted in *note
  2023. Machine Dependencies::. That character may be followed by any string of
  2024. digits, letters, dollar signs (unless otherwise noted for a particular
  2025. target machine), and underscores.
  2026. Case of letters is significant: 'foo' is a different symbol name than
  2027. 'Foo'.
  2028. Symbol names do not start with a digit. An exception to this rule is
  2029. made for Local Labels. See below.
  2030. Multibyte characters are supported. To generate a symbol name
  2031. containing multibyte characters enclose it within double quotes and use
  2032. escape codes. cf *Note Strings::. Generating a multibyte symbol name
  2033. from a label is not currently supported.
  2034. Each symbol has exactly one name. Each name in an assembly language
  2035. program refers to exactly one symbol. You may use that symbol name any
  2036. number of times in a program.
  2037. Local Symbol Names
  2038. ------------------
  2039. A local symbol is any symbol beginning with certain local label
  2040. prefixes. By default, the local label prefix is '.L' for ELF systems or
  2041. 'L' for traditional a.out systems, but each target may have its own set
  2042. of local label prefixes. On the HPPA local symbols begin with 'L$'.
  2043. Local symbols are defined and used within the assembler, but they are
  2044. normally not saved in object files. Thus, they are not visible when
  2045. debugging. You may use the '-L' option (*note Include Local Symbols:
  2046. L.) to retain the local symbols in the object files.
  2047. Local Labels
  2048. ------------
  2049. Local labels are different from local symbols. Local labels help
  2050. compilers and programmers use names temporarily. They create symbols
  2051. which are guaranteed to be unique over the entire scope of the input
  2052. source code and which can be referred to by a simple notation. To
  2053. define a local label, write a label of the form 'N:' (where N represents
  2054. any non-negative integer). To refer to the most recent previous
  2055. definition of that label write 'Nb', using the same number as when you
  2056. defined the label. To refer to the next definition of a local label,
  2057. write 'Nf'. The 'b' stands for "backwards" and the 'f' stands for
  2058. "forwards".
  2059. There is no restriction on how you can use these labels, and you can
  2060. reuse them too. So that it is possible to repeatedly define the same
  2061. local label (using the same number 'N'), although you can only refer to
  2062. the most recently defined local label of that number (for a backwards
  2063. reference) or the next definition of a specific local label for a
  2064. forward reference. It is also worth noting that the first 10 local
  2065. labels ('0:'...'9:') are implemented in a slightly more efficient manner
  2066. than the others.
  2067. Here is an example:
  2068. 1: branch 1f
  2069. 2: branch 1b
  2070. 1: branch 2f
  2071. 2: branch 1b
  2072. Which is the equivalent of:
  2073. label_1: branch label_3
  2074. label_2: branch label_1
  2075. label_3: branch label_4
  2076. label_4: branch label_3
  2077. Local label names are only a notational device. They are immediately
  2078. transformed into more conventional symbol names before the assembler
  2079. uses them. The symbol names are stored in the symbol table, appear in
  2080. error messages, and are optionally emitted to the object file. The
  2081. names are constructed using these parts:
  2082. '_local label prefix_'
  2083. All local symbols begin with the system-specific local label
  2084. prefix. Normally both 'as' and 'ld' forget symbols that start with
  2085. the local label prefix. These labels are used for symbols you are
  2086. never intended to see. If you use the '-L' option then 'as'
  2087. retains these symbols in the object file. If you also instruct
  2088. 'ld' to retain these symbols, you may use them in debugging.
  2089. 'NUMBER'
  2090. This is the number that was used in the local label definition. So
  2091. if the label is written '55:' then the number is '55'.
  2092. 'C-B'
  2093. This unusual character is included so you do not accidentally
  2094. invent a symbol of the same name. The character has ASCII value of
  2095. '\002' (control-B).
  2096. '_ordinal number_'
  2097. This is a serial number to keep the labels distinct. The first
  2098. definition of '0:' gets the number '1'. The 15th definition of
  2099. '0:' gets the number '15', and so on. Likewise the first
  2100. definition of '1:' gets the number '1' and its 15th definition gets
  2101. '15' as well.
  2102. So for example, the first '1:' may be named '.L1C-B1', and the 44th
  2103. '3:' may be named '.L3C-B44'.
  2104. Dollar Local Labels
  2105. -------------------
  2106. On some targets 'as' also supports an even more local form of local
  2107. labels called dollar labels. These labels go out of scope (i.e., they
  2108. become undefined) as soon as a non-local label is defined. Thus they
  2109. remain valid for only a small region of the input source code. Normal
  2110. local labels, by contrast, remain in scope for the entire file, or until
  2111. they are redefined by another occurrence of the same local label.
  2112. Dollar labels are defined in exactly the same way as ordinary local
  2113. labels, except that they have a dollar sign suffix to their numeric
  2114. value, e.g., '55$:'.
  2115. They can also be distinguished from ordinary local labels by their
  2116. transformed names which use ASCII character '\001' (control-A) as the
  2117. magic character to distinguish them from ordinary labels. For example,
  2118. the fifth definition of '6$' may be named '.L6'C-A'5'.
  2119. 
  2120. File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols
  2121. 5.4 The Special Dot Symbol
  2122. ==========================
  2123. The special symbol '.' refers to the current address that 'as' is
  2124. assembling into. Thus, the expression 'melvin: .long .' defines
  2125. 'melvin' to contain its own address. Assigning a value to '.' is
  2126. treated the same as a '.org' directive. Thus, the expression '.=.+4' is
  2127. the same as saying '.space 4'.
  2128. 
  2129. File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols
  2130. 5.5 Symbol Attributes
  2131. =====================
  2132. Every symbol has, as well as its name, the attributes "Value" and
  2133. "Type". Depending on output format, symbols can also have auxiliary
  2134. attributes.
  2135. If you use a symbol without defining it, 'as' assumes zero for all
  2136. these attributes, and probably won't warn you. This makes the symbol an
  2137. externally defined symbol, which is generally what you would want.
  2138. * Menu:
  2139. * Symbol Value:: Value
  2140. * Symbol Type:: Type
  2141. * a.out Symbols:: Symbol Attributes: 'a.out'
  2142. * COFF Symbols:: Symbol Attributes for COFF
  2143. * SOM Symbols:: Symbol Attributes for SOM
  2144. 
  2145. File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes
  2146. 5.5.1 Value
  2147. -----------
  2148. The value of a symbol is (usually) 32 bits. For a symbol which labels a
  2149. location in the text, data, bss or absolute sections the value is the
  2150. number of addresses from the start of that section to the label.
  2151. Naturally for text, data and bss sections the value of a symbol changes
  2152. as 'ld' changes section base addresses during linking. Absolute
  2153. symbols' values do not change during linking: that is why they are
  2154. called absolute.
  2155. The value of an undefined symbol is treated in a special way. If it
  2156. is 0 then the symbol is not defined in this assembler source file, and
  2157. 'ld' tries to determine its value from other files linked into the same
  2158. program. You make this kind of symbol simply by mentioning a symbol
  2159. name without defining it. A non-zero value represents a '.comm' common
  2160. declaration. The value is how much common storage to reserve, in bytes
  2161. (addresses). The symbol refers to the first address of the allocated
  2162. storage.
  2163. 
  2164. File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes
  2165. 5.5.2 Type
  2166. ----------
  2167. The type attribute of a symbol contains relocation (section)
  2168. information, any flag settings indicating that a symbol is external, and
  2169. (optionally), other information for linkers and debuggers. The exact
  2170. format depends on the object-code output format in use.
  2171. 
  2172. File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes
  2173. 5.5.3 Symbol Attributes: 'a.out'
  2174. --------------------------------
  2175. * Menu:
  2176. * Symbol Desc:: Descriptor
  2177. * Symbol Other:: Other
  2178. 
  2179. File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols
  2180. 5.5.3.1 Descriptor
  2181. ..................
  2182. This is an arbitrary 16-bit value. You may establish a symbol's
  2183. descriptor value by using a '.desc' statement (*note '.desc': Desc.). A
  2184. descriptor value means nothing to 'as'.
  2185. 
  2186. File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols
  2187. 5.5.3.2 Other
  2188. .............
  2189. This is an arbitrary 8-bit value. It means nothing to 'as'.
  2190. 
  2191. File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes
  2192. 5.5.4 Symbol Attributes for COFF
  2193. --------------------------------
  2194. The COFF format supports a multitude of auxiliary symbol attributes;
  2195. like the primary symbol attributes, they are set between '.def' and
  2196. '.endef' directives.
  2197. 5.5.4.1 Primary Attributes
  2198. ..........................
  2199. The symbol name is set with '.def'; the value and type, respectively,
  2200. with '.val' and '.type'.
  2201. 5.5.4.2 Auxiliary Attributes
  2202. ............................
  2203. The 'as' directives '.dim', '.line', '.scl', '.size', '.tag', and
  2204. '.weak' can generate auxiliary symbol table information for COFF.
  2205. 
  2206. File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes
  2207. 5.5.5 Symbol Attributes for SOM
  2208. -------------------------------
  2209. The SOM format for the HPPA supports a multitude of symbol attributes
  2210. set with the '.EXPORT' and '.IMPORT' directives.
  2211. The attributes are described in 'HP9000 Series 800 Assembly Language
  2212. Reference Manual' (HP 92432-90001) under the 'IMPORT' and 'EXPORT'
  2213. assembler directive documentation.
  2214. 
  2215. File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top
  2216. 6 Expressions
  2217. *************
  2218. An "expression" specifies an address or numeric value. Whitespace may
  2219. precede and/or follow an expression.
  2220. The result of an expression must be an absolute number, or else an
  2221. offset into a particular section. If an expression is not absolute, and
  2222. there is not enough information when 'as' sees the expression to know
  2223. its section, a second pass over the source program might be necessary to
  2224. interpret the expression--but the second pass is currently not
  2225. implemented. 'as' aborts with an error message in this situation.
  2226. * Menu:
  2227. * Empty Exprs:: Empty Expressions
  2228. * Integer Exprs:: Integer Expressions
  2229. 
  2230. File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions
  2231. 6.1 Empty Expressions
  2232. =====================
  2233. An empty expression has no value: it is just whitespace or null.
  2234. Wherever an absolute expression is required, you may omit the
  2235. expression, and 'as' assumes a value of (absolute) 0. This is
  2236. compatible with other assemblers.
  2237. 
  2238. File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions
  2239. 6.2 Integer Expressions
  2240. =======================
  2241. An "integer expression" is one or more _arguments_ delimited by
  2242. _operators_.
  2243. * Menu:
  2244. * Arguments:: Arguments
  2245. * Operators:: Operators
  2246. * Prefix Ops:: Prefix Operators
  2247. * Infix Ops:: Infix Operators
  2248. 
  2249. File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs
  2250. 6.2.1 Arguments
  2251. ---------------
  2252. "Arguments" are symbols, numbers or subexpressions. In other contexts
  2253. arguments are sometimes called "arithmetic operands". In this manual,
  2254. to avoid confusing them with the "instruction operands" of the machine
  2255. language, we use the term "argument" to refer to parts of expressions
  2256. only, reserving the word "operand" to refer only to machine instruction
  2257. operands.
  2258. Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
  2259. text, data, bss, absolute, or undefined. NNN is a signed, 2's
  2260. complement 32 bit integer.
  2261. Numbers are usually integers.
  2262. A number can be a flonum or bignum. In this case, you are warned
  2263. that only the low order 32 bits are used, and 'as' pretends these 32
  2264. bits are an integer. You may write integer-manipulating instructions
  2265. that act on exotic constants, compatible with other assemblers.
  2266. Subexpressions are a left parenthesis '(' followed by an integer
  2267. expression, followed by a right parenthesis ')'; or a prefix operator
  2268. followed by an argument.
  2269. 
  2270. File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs
  2271. 6.2.2 Operators
  2272. ---------------
  2273. "Operators" are arithmetic functions, like '+' or '%'. Prefix operators
  2274. are followed by an argument. Infix operators appear between their
  2275. arguments. Operators may be preceded and/or followed by whitespace.
  2276. 
  2277. File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs
  2278. 6.2.3 Prefix Operator
  2279. ---------------------
  2280. 'as' has the following "prefix operators". They each take one argument,
  2281. which must be absolute.
  2282. '-'
  2283. "Negation". Two's complement negation.
  2284. '~'
  2285. "Complementation". Bitwise not.
  2286. 
  2287. File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs
  2288. 6.2.4 Infix Operators
  2289. ---------------------
  2290. "Infix operators" take two arguments, one on either side. Operators
  2291. have precedence, but operations with equal precedence are performed left
  2292. to right. Apart from '+' or '-', both arguments must be absolute, and
  2293. the result is absolute.
  2294. 1. Highest Precedence
  2295. '*'
  2296. "Multiplication".
  2297. '/'
  2298. "Division". Truncation is the same as the C operator '/'
  2299. '%'
  2300. "Remainder".
  2301. '<<'
  2302. "Shift Left". Same as the C operator '<<'.
  2303. '>>'
  2304. "Shift Right". Same as the C operator '>>'.
  2305. 2. Intermediate precedence
  2306. '|'
  2307. "Bitwise Inclusive Or".
  2308. '&'
  2309. "Bitwise And".
  2310. '^'
  2311. "Bitwise Exclusive Or".
  2312. '!'
  2313. "Bitwise Or Not".
  2314. 3. Low Precedence
  2315. '+'
  2316. "Addition". If either argument is absolute, the result has
  2317. the section of the other argument. You may not add together
  2318. arguments from different sections.
  2319. '-'
  2320. "Subtraction". If the right argument is absolute, the result
  2321. has the section of the left argument. If both arguments are
  2322. in the same section, the result is absolute. You may not
  2323. subtract arguments from different sections.
  2324. '=='
  2325. "Is Equal To"
  2326. '<>'
  2327. '!='
  2328. "Is Not Equal To"
  2329. '<'
  2330. "Is Less Than"
  2331. '>'
  2332. "Is Greater Than"
  2333. '>='
  2334. "Is Greater Than Or Equal To"
  2335. '<='
  2336. "Is Less Than Or Equal To"
  2337. The comparison operators can be used as infix operators. A
  2338. true results has a value of -1 whereas a false result has a
  2339. value of 0. Note, these operators perform signed comparisons.
  2340. 4. Lowest Precedence
  2341. '&&'
  2342. "Logical And".
  2343. '||'
  2344. "Logical Or".
  2345. These two logical operations can be used to combine the
  2346. results of sub expressions. Note, unlike the comparison
  2347. operators a true result returns a value of 1 but a false
  2348. results does still return 0. Also note that the logical or
  2349. operator has a slightly lower precedence than logical and.
  2350. In short, it's only meaningful to add or subtract the _offsets_ in an
  2351. address; you can only have a defined section in one of the two
  2352. arguments.
  2353. 
  2354. File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top
  2355. 7 Assembler Directives
  2356. **********************
  2357. All assembler directives have names that begin with a period ('.'). The
  2358. names are case insensitive for most targets, and usually written in
  2359. lower case.
  2360. This chapter discusses directives that are available regardless of
  2361. the target machine configuration for the GNU assembler. Some machine
  2362. configurations provide additional directives. *Note Machine
  2363. Dependencies::.
  2364. * Menu:
  2365. * Abort:: '.abort'
  2366. * ABORT (COFF):: '.ABORT'
  2367. * Align:: '.align ABS-EXPR , ABS-EXPR'
  2368. * Altmacro:: '.altmacro'
  2369. * Ascii:: '.ascii "STRING"'...
  2370. * Asciz:: '.asciz "STRING"'...
  2371. * Balign:: '.balign ABS-EXPR , ABS-EXPR'
  2372. * Bundle directives:: '.bundle_align_mode ABS-EXPR', etc
  2373. * Byte:: '.byte EXPRESSIONS'
  2374. * CFI directives:: '.cfi_startproc [simple]', '.cfi_endproc', etc.
  2375. * Comm:: '.comm SYMBOL , LENGTH '
  2376. * Data:: '.data SUBSECTION'
  2377. * Def:: '.def NAME'
  2378. * Desc:: '.desc SYMBOL, ABS-EXPRESSION'
  2379. * Dim:: '.dim'
  2380. * Double:: '.double FLONUMS'
  2381. * Eject:: '.eject'
  2382. * Else:: '.else'
  2383. * Elseif:: '.elseif'
  2384. * End:: '.end'
  2385. * Endef:: '.endef'
  2386. * Endfunc:: '.endfunc'
  2387. * Endif:: '.endif'
  2388. * Equ:: '.equ SYMBOL, EXPRESSION'
  2389. * Equiv:: '.equiv SYMBOL, EXPRESSION'
  2390. * Eqv:: '.eqv SYMBOL, EXPRESSION'
  2391. * Err:: '.err'
  2392. * Error:: '.error STRING'
  2393. * Exitm:: '.exitm'
  2394. * Extern:: '.extern'
  2395. * Fail:: '.fail'
  2396. * File:: '.file'
  2397. * Fill:: '.fill REPEAT , SIZE , VALUE'
  2398. * Float:: '.float FLONUMS'
  2399. * Func:: '.func'
  2400. * Global:: '.global SYMBOL', '.globl SYMBOL'
  2401. * Gnu_attribute:: '.gnu_attribute TAG,VALUE'
  2402. * Hidden:: '.hidden NAMES'
  2403. * hword:: '.hword EXPRESSIONS'
  2404. * Ident:: '.ident'
  2405. * If:: '.if ABSOLUTE EXPRESSION'
  2406. * Incbin:: '.incbin "FILE"[,SKIP[,COUNT]]'
  2407. * Include:: '.include "FILE"'
  2408. * Int:: '.int EXPRESSIONS'
  2409. * Internal:: '.internal NAMES'
  2410. * Irp:: '.irp SYMBOL,VALUES'...
  2411. * Irpc:: '.irpc SYMBOL,VALUES'...
  2412. * Lcomm:: '.lcomm SYMBOL , LENGTH'
  2413. * Lflags:: '.lflags'
  2414. * Line:: '.line LINE-NUMBER'
  2415. * Linkonce:: '.linkonce [TYPE]'
  2416. * List:: '.list'
  2417. * Ln:: '.ln LINE-NUMBER'
  2418. * Loc:: '.loc FILENO LINENO'
  2419. * Loc_mark_labels:: '.loc_mark_labels ENABLE'
  2420. * Local:: '.local NAMES'
  2421. * Long:: '.long EXPRESSIONS'
  2422. * Macro:: '.macro NAME ARGS'...
  2423. * MRI:: '.mri VAL'
  2424. * Noaltmacro:: '.noaltmacro'
  2425. * Nolist:: '.nolist'
  2426. * Octa:: '.octa BIGNUMS'
  2427. * Offset:: '.offset LOC'
  2428. * Org:: '.org NEW-LC, FILL'
  2429. * P2align:: '.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR'
  2430. * PopSection:: '.popsection'
  2431. * Previous:: '.previous'
  2432. * Print:: '.print STRING'
  2433. * Protected:: '.protected NAMES'
  2434. * Psize:: '.psize LINES, COLUMNS'
  2435. * Purgem:: '.purgem NAME'
  2436. * PushSection:: '.pushsection NAME'
  2437. * Quad:: '.quad BIGNUMS'
  2438. * Reloc:: '.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
  2439. * Rept:: '.rept COUNT'
  2440. * Sbttl:: '.sbttl "SUBHEADING"'
  2441. * Scl:: '.scl CLASS'
  2442. * Section:: '.section NAME[, FLAGS]'
  2443. * Set:: '.set SYMBOL, EXPRESSION'
  2444. * Short:: '.short EXPRESSIONS'
  2445. * Single:: '.single FLONUMS'
  2446. * Size:: '.size [NAME , EXPRESSION]'
  2447. * Skip:: '.skip SIZE , FILL'
  2448. * Sleb128:: '.sleb128 EXPRESSIONS'
  2449. * Space:: '.space SIZE , FILL'
  2450. * Stab:: '.stabd, .stabn, .stabs'
  2451. * String:: '.string "STR"', '.string8 "STR"', '.string16 "STR"', '.string32 "STR"', '.string64 "STR"'
  2452. * Struct:: '.struct EXPRESSION'
  2453. * SubSection:: '.subsection'
  2454. * Symver:: '.symver NAME,NAME2@NODENAME'
  2455. * Tag:: '.tag STRUCTNAME'
  2456. * Text:: '.text SUBSECTION'
  2457. * Title:: '.title "HEADING"'
  2458. * Type:: '.type <INT | NAME , TYPE DESCRIPTION>'
  2459. * Uleb128:: '.uleb128 EXPRESSIONS'
  2460. * Val:: '.val ADDR'
  2461. * Version:: '.version "STRING"'
  2462. * VTableEntry:: '.vtable_entry TABLE, OFFSET'
  2463. * VTableInherit:: '.vtable_inherit CHILD, PARENT'
  2464. * Warning:: '.warning STRING'
  2465. * Weak:: '.weak NAMES'
  2466. * Weakref:: '.weakref ALIAS, SYMBOL'
  2467. * Word:: '.word EXPRESSIONS'
  2468. * Zero:: '.zero SIZE'
  2469. * Deprecated:: Deprecated Directives
  2470. 
  2471. File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops
  2472. 7.1 '.abort'
  2473. ============
  2474. This directive stops the assembly immediately. It is for compatibility
  2475. with other assemblers. The original idea was that the assembly language
  2476. source would be piped into the assembler. If the sender of the source
  2477. quit, it could use this directive tells 'as' to quit also. One day
  2478. '.abort' will not be supported.
  2479. 
  2480. File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops
  2481. 7.2 '.ABORT' (COFF)
  2482. ===================
  2483. When producing COFF output, 'as' accepts this directive as a synonym for
  2484. '.abort'.
  2485. 
  2486. File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops
  2487. 7.3 '.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
  2488. =========================================
  2489. Pad the location counter (in the current subsection) to a particular
  2490. storage boundary. The first expression (which must be absolute) is the
  2491. alignment required, as described below.
  2492. The second expression (also absolute) gives the fill value to be
  2493. stored in the padding bytes. It (and the comma) may be omitted. If it
  2494. is omitted, the padding bytes are normally zero. However, on some
  2495. systems, if the section is marked as containing code and the fill value
  2496. is omitted, the space is filled with no-op instructions.
  2497. The third expression is also absolute, and is also optional. If it
  2498. is present, it is the maximum number of bytes that should be skipped by
  2499. this alignment directive. If doing the alignment would require skipping
  2500. more bytes than the specified maximum, then the alignment is not done at
  2501. all. You can omit the fill value (the second argument) entirely by
  2502. simply using two commas after the required alignment; this can be useful
  2503. if you want the alignment to be filled with no-op instructions when
  2504. appropriate.
  2505. The way the required alignment is specified varies from system to
  2506. system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k,
  2507. s390, sparc, tic4x, tic80 and xtensa, the first expression is the
  2508. alignment request in bytes. For example '.align 8' advances the
  2509. location counter until it is a multiple of 8. If the location counter
  2510. is already a multiple of 8, no change is needed. For the tic54x, the
  2511. first expression is the alignment request in words.
  2512. For other systems, including ppc, i386 using a.out format, arm and
  2513. strongarm, it is the number of low-order zero bits the location counter
  2514. must have after advancement. For example '.align 3' advances the
  2515. location counter until it a multiple of 8. If the location counter is
  2516. already a multiple of 8, no change is needed.
  2517. This inconsistency is due to the different behaviors of the various
  2518. native assemblers for these systems which GAS must emulate. GAS also
  2519. provides '.balign' and '.p2align' directives, described later, which
  2520. have a consistent behavior across all architectures (but are specific to
  2521. GAS).
  2522. 
  2523. File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops
  2524. 7.4 '.altmacro'
  2525. ===============
  2526. Enable alternate macro mode, enabling:
  2527. 'LOCAL NAME [ , ... ]'
  2528. One additional directive, 'LOCAL', is available. It is used to
  2529. generate a string replacement for each of the NAME arguments, and
  2530. replace any instances of NAME in each macro expansion. The
  2531. replacement string is unique in the assembly, and different for
  2532. each separate macro expansion. 'LOCAL' allows you to write macros
  2533. that define symbols, without fear of conflict between separate
  2534. macro expansions.
  2535. 'String delimiters'
  2536. You can write strings delimited in these other ways besides
  2537. '"STRING"':
  2538. ''STRING''
  2539. You can delimit strings with single-quote characters.
  2540. '<STRING>'
  2541. You can delimit strings with matching angle brackets.
  2542. 'single-character string escape'
  2543. To include any single character literally in a string (even if the
  2544. character would otherwise have some special meaning), you can
  2545. prefix the character with '!' (an exclamation mark). For example,
  2546. you can write '<4.3 !> 5.4!!>' to get the literal text '4.3 >
  2547. 5.4!'.
  2548. 'Expression results as strings'
  2549. You can write '%EXPR' to evaluate the expression EXPR and use the
  2550. result as a string.
  2551. 
  2552. File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops
  2553. 7.5 '.ascii "STRING"'...
  2554. ========================
  2555. '.ascii' expects zero or more string literals (*note Strings::)
  2556. separated by commas. It assembles each string (with no automatic
  2557. trailing zero byte) into consecutive addresses.
  2558. 
  2559. File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops
  2560. 7.6 '.asciz "STRING"'...
  2561. ========================
  2562. '.asciz' is just like '.ascii', but each string is followed by a zero
  2563. byte. The "z" in '.asciz' stands for "zero".
  2564. 
  2565. File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops
  2566. 7.7 '.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
  2567. ==============================================
  2568. Pad the location counter (in the current subsection) to a particular
  2569. storage boundary. The first expression (which must be absolute) is the
  2570. alignment request in bytes. For example '.balign 8' advances the
  2571. location counter until it is a multiple of 8. If the location counter
  2572. is already a multiple of 8, no change is needed.
  2573. The second expression (also absolute) gives the fill value to be
  2574. stored in the padding bytes. It (and the comma) may be omitted. If it
  2575. is omitted, the padding bytes are normally zero. However, on some
  2576. systems, if the section is marked as containing code and the fill value
  2577. is omitted, the space is filled with no-op instructions.
  2578. The third expression is also absolute, and is also optional. If it
  2579. is present, it is the maximum number of bytes that should be skipped by
  2580. this alignment directive. If doing the alignment would require skipping
  2581. more bytes than the specified maximum, then the alignment is not done at
  2582. all. You can omit the fill value (the second argument) entirely by
  2583. simply using two commas after the required alignment; this can be useful
  2584. if you want the alignment to be filled with no-op instructions when
  2585. appropriate.
  2586. The '.balignw' and '.balignl' directives are variants of the
  2587. '.balign' directive. The '.balignw' directive treats the fill pattern
  2588. as a two byte word value. The '.balignl' directives treats the fill
  2589. pattern as a four byte longword value. For example, '.balignw 4,0x368d'
  2590. will align to a multiple of 4. If it skips two bytes, they will be
  2591. filled in with the value 0x368d (the exact placement of the bytes
  2592. depends upon the endianness of the processor). If it skips 1 or 3
  2593. bytes, the fill value is undefined.
  2594. 
  2595. File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops
  2596. 7.8 Bundle directives
  2597. =====================
  2598. 7.8.1 '.bundle_align_mode ABS-EXPR'
  2599. -----------------------------------
  2600. '.bundle_align_mode' enables or disables "aligned instruction bundle"
  2601. mode. In this mode, sequences of adjacent instructions are grouped into
  2602. fixed-sized "bundles". If the argument is zero, this mode is disabled
  2603. (which is the default state). If the argument it not zero, it gives the
  2604. size of an instruction bundle as a power of two (as for the '.p2align'
  2605. directive, *note P2align::).
  2606. For some targets, it's an ABI requirement that no instruction may
  2607. span a certain aligned boundary. A "bundle" is simply a sequence of
  2608. instructions that starts on an aligned boundary. For example, if
  2609. ABS-EXPR is '5' then the bundle size is 32, so each aligned chunk of 32
  2610. bytes is a bundle. When aligned instruction bundle mode is in effect,
  2611. no single instruction may span a boundary between bundles. If an
  2612. instruction would start too close to the end of a bundle for the length
  2613. of that particular instruction to fit within the bundle, then the space
  2614. at the end of that bundle is filled with no-op instructions so the
  2615. instruction starts in the next bundle. As a corollary, it's an error if
  2616. any single instruction's encoding is longer than the bundle size.
  2617. 7.8.2 '.bundle_lock' and '.bundle_unlock'
  2618. -----------------------------------------
  2619. The '.bundle_lock' and directive '.bundle_unlock' directives allow
  2620. explicit control over instruction bundle padding. These directives are
  2621. only valid when '.bundle_align_mode' has been used to enable aligned
  2622. instruction bundle mode. It's an error if they appear when
  2623. '.bundle_align_mode' has not been used at all, or when the last
  2624. directive was '.bundle_align_mode 0'.
  2625. For some targets, it's an ABI requirement that certain instructions
  2626. may appear only as part of specified permissible sequences of multiple
  2627. instructions, all within the same bundle. A pair of '.bundle_lock' and
  2628. '.bundle_unlock' directives define a "bundle-locked" instruction
  2629. sequence. For purposes of aligned instruction bundle mode, a sequence
  2630. starting with '.bundle_lock' and ending with '.bundle_unlock' is treated
  2631. as a single instruction. That is, the entire sequence must fit into a
  2632. single bundle and may not span a bundle boundary. If necessary, no-op
  2633. instructions will be inserted before the first instruction of the
  2634. sequence so that the whole sequence starts on an aligned bundle
  2635. boundary. It's an error if the sequence is longer than the bundle size.
  2636. For convenience when using '.bundle_lock' and '.bundle_unlock' inside
  2637. assembler macros (*note Macro::), bundle-locked sequences may be nested.
  2638. That is, a second '.bundle_lock' directive before the next
  2639. '.bundle_unlock' directive has no effect except that it must be matched
  2640. by another closing '.bundle_unlock' so that there is the same number of
  2641. '.bundle_lock' and '.bundle_unlock' directives.
  2642. 
  2643. File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops
  2644. 7.9 '.byte EXPRESSIONS'
  2645. =======================
  2646. '.byte' expects zero or more expressions, separated by commas. Each
  2647. expression is assembled into the next byte.
  2648. 
  2649. File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops
  2650. 7.10 CFI directives
  2651. ===================
  2652. 7.10.1 '.cfi_sections SECTION_LIST'
  2653. -----------------------------------
  2654. '.cfi_sections' may be used to specify whether CFI directives should
  2655. emit '.eh_frame' section and/or '.debug_frame' section. If SECTION_LIST
  2656. is '.eh_frame', '.eh_frame' is emitted, if SECTION_LIST is
  2657. '.debug_frame', '.debug_frame' is emitted. To emit both use '.eh_frame,
  2658. .debug_frame'. The default if this directive is not used is
  2659. '.cfi_sections .eh_frame'.
  2660. On targets that support compact unwinding tables these can be
  2661. generated by specifying '.eh_frame_entry' instead of '.eh_frame'.
  2662. Some targets may support an additional name, such as '.c6xabi.exidx'
  2663. which is used by the target.
  2664. The '.cfi_sections' directive can be repeated, with the same or
  2665. different arguments, provided that CFI generation has not yet started.
  2666. Once CFI generation has started however the section list is fixed and
  2667. any attempts to redefine it will result in an error.
  2668. 7.10.2 '.cfi_startproc [simple]'
  2669. --------------------------------
  2670. '.cfi_startproc' is used at the beginning of each function that should
  2671. have an entry in '.eh_frame'. It initializes some internal data
  2672. structures. Don't forget to close the function by '.cfi_endproc'.
  2673. Unless '.cfi_startproc' is used along with parameter 'simple' it also
  2674. emits some architecture dependent initial CFI instructions.
  2675. 7.10.3 '.cfi_endproc'
  2676. ---------------------
  2677. '.cfi_endproc' is used at the end of a function where it closes its
  2678. unwind entry previously opened by '.cfi_startproc', and emits it to
  2679. '.eh_frame'.
  2680. 7.10.4 '.cfi_personality ENCODING [, EXP]'
  2681. ------------------------------------------
  2682. '.cfi_personality' defines personality routine and its encoding.
  2683. ENCODING must be a constant determining how the personality should be
  2684. encoded. If it is 255 ('DW_EH_PE_omit'), second argument is not
  2685. present, otherwise second argument should be a constant or a symbol
  2686. name. When using indirect encodings, the symbol provided should be the
  2687. location where personality can be loaded from, not the personality
  2688. routine itself. The default after '.cfi_startproc' is '.cfi_personality
  2689. 0xff', no personality routine.
  2690. 7.10.5 '.cfi_personality_id ID'
  2691. -------------------------------
  2692. 'cfi_personality_id' defines a personality routine by its index as
  2693. defined in a compact unwinding format. Only valid when generating
  2694. compact EH frames (i.e. with '.cfi_sections eh_frame_entry'.
  2695. 7.10.6 '.cfi_fde_data [OPCODE1 [, ...]]'
  2696. ----------------------------------------
  2697. 'cfi_fde_data' is used to describe the compact unwind opcodes to be used
  2698. for the current function. These are emitted inline in the
  2699. '.eh_frame_entry' section if small enough and there is no LSDA, or in
  2700. the '.gnu.extab' section otherwise. Only valid when generating compact
  2701. EH frames (i.e. with '.cfi_sections eh_frame_entry'.
  2702. 7.10.7 '.cfi_lsda ENCODING [, EXP]'
  2703. -----------------------------------
  2704. '.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant
  2705. determining how the LSDA should be encoded. If it is 255
  2706. ('DW_EH_PE_omit'), the second argument is not present, otherwise the
  2707. second argument should be a constant or a symbol name. The default
  2708. after '.cfi_startproc' is '.cfi_lsda 0xff', meaning that no LSDA is
  2709. present.
  2710. 7.10.8 '.cfi_inline_lsda' [ALIGN]
  2711. ---------------------------------
  2712. '.cfi_inline_lsda' marks the start of a LSDA data section and switches
  2713. to the corresponding '.gnu.extab' section. Must be preceded by a CFI
  2714. block containing a '.cfi_lsda' directive. Only valid when generating
  2715. compact EH frames (i.e. with '.cfi_sections eh_frame_entry'.
  2716. The table header and unwinding opcodes will be generated at this
  2717. point, so that they are immediately followed by the LSDA data. The
  2718. symbol referenced by the '.cfi_lsda' directive should still be defined
  2719. in case a fallback FDE based encoding is used. The LSDA data is
  2720. terminated by a section directive.
  2721. The optional ALIGN argument specifies the alignment required. The
  2722. alignment is specified as a power of two, as with the '.p2align'
  2723. directive.
  2724. 7.10.9 '.cfi_def_cfa REGISTER, OFFSET'
  2725. --------------------------------------
  2726. '.cfi_def_cfa' defines a rule for computing CFA as: take address from
  2727. REGISTER and add OFFSET to it.
  2728. 7.10.10 '.cfi_def_cfa_register REGISTER'
  2729. ----------------------------------------
  2730. '.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
  2731. REGISTER will be used instead of the old one. Offset remains the same.
  2732. 7.10.11 '.cfi_def_cfa_offset OFFSET'
  2733. ------------------------------------
  2734. '.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
  2735. remains the same, but OFFSET is new. Note that it is the absolute
  2736. offset that will be added to a defined register to compute CFA address.
  2737. 7.10.12 '.cfi_adjust_cfa_offset OFFSET'
  2738. ---------------------------------------
  2739. Same as '.cfi_def_cfa_offset' but OFFSET is a relative value that is
  2740. added/substracted from the previous offset.
  2741. 7.10.13 '.cfi_offset REGISTER, OFFSET'
  2742. --------------------------------------
  2743. Previous value of REGISTER is saved at offset OFFSET from CFA.
  2744. 7.10.14 '.cfi_val_offset REGISTER, OFFSET'
  2745. ------------------------------------------
  2746. Previous value of REGISTER is CFA + OFFSET.
  2747. 7.10.15 '.cfi_rel_offset REGISTER, OFFSET'
  2748. ------------------------------------------
  2749. Previous value of REGISTER is saved at offset OFFSET from the current
  2750. CFA register. This is transformed to '.cfi_offset' using the known
  2751. displacement of the CFA register from the CFA. This is often easier to
  2752. use, because the number will match the code it's annotating.
  2753. 7.10.16 '.cfi_register REGISTER1, REGISTER2'
  2754. --------------------------------------------
  2755. Previous value of REGISTER1 is saved in register REGISTER2.
  2756. 7.10.17 '.cfi_restore REGISTER'
  2757. -------------------------------
  2758. '.cfi_restore' says that the rule for REGISTER is now the same as it was
  2759. at the beginning of the function, after all initial instruction added by
  2760. '.cfi_startproc' were executed.
  2761. 7.10.18 '.cfi_undefined REGISTER'
  2762. ---------------------------------
  2763. From now on the previous value of REGISTER can't be restored anymore.
  2764. 7.10.19 '.cfi_same_value REGISTER'
  2765. ----------------------------------
  2766. Current value of REGISTER is the same like in the previous frame, i.e.
  2767. no restoration needed.
  2768. 7.10.20 '.cfi_remember_state' and '.cfi_restore_state'
  2769. ------------------------------------------------------
  2770. '.cfi_remember_state' pushes the set of rules for every register onto an
  2771. implicit stack, while '.cfi_restore_state' pops them off the stack and
  2772. places them in the current row. This is useful for situations where you
  2773. have multiple '.cfi_*' directives that need to be undone due to the
  2774. control flow of the program. For example, we could have something like
  2775. this (assuming the CFA is the value of 'rbp'):
  2776. je label
  2777. popq %rbx
  2778. .cfi_restore %rbx
  2779. popq %r12
  2780. .cfi_restore %r12
  2781. popq %rbp
  2782. .cfi_restore %rbp
  2783. .cfi_def_cfa %rsp, 8
  2784. ret
  2785. label:
  2786. /* Do something else */
  2787. Here, we want the '.cfi' directives to affect only the rows
  2788. corresponding to the instructions before 'label'. This means we'd have
  2789. to add multiple '.cfi' directives after 'label' to recreate the original
  2790. save locations of the registers, as well as setting the CFA back to the
  2791. value of 'rbp'. This would be clumsy, and result in a larger binary
  2792. size. Instead, we can write:
  2793. je label
  2794. popq %rbx
  2795. .cfi_remember_state
  2796. .cfi_restore %rbx
  2797. popq %r12
  2798. .cfi_restore %r12
  2799. popq %rbp
  2800. .cfi_restore %rbp
  2801. .cfi_def_cfa %rsp, 8
  2802. ret
  2803. label:
  2804. .cfi_restore_state
  2805. /* Do something else */
  2806. That way, the rules for the instructions after 'label' will be the
  2807. same as before the first '.cfi_restore' without having to use multiple
  2808. '.cfi' directives.
  2809. 7.10.21 '.cfi_return_column REGISTER'
  2810. -------------------------------------
  2811. Change return column REGISTER, i.e. the return address is either
  2812. directly in REGISTER or can be accessed by rules for REGISTER.
  2813. 7.10.22 '.cfi_signal_frame'
  2814. ---------------------------
  2815. Mark current function as signal trampoline.
  2816. 7.10.23 '.cfi_window_save'
  2817. --------------------------
  2818. SPARC register window has been saved.
  2819. 7.10.24 '.cfi_escape' EXPRESSION[, ...]
  2820. ---------------------------------------
  2821. Allows the user to add arbitrary bytes to the unwind info. One might
  2822. use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS
  2823. does not yet support.
  2824. 7.10.25 '.cfi_val_encoded_addr REGISTER, ENCODING, LABEL'
  2825. ---------------------------------------------------------
  2826. The current value of REGISTER is LABEL. The value of LABEL will be
  2827. encoded in the output file according to ENCODING; see the description of
  2828. '.cfi_personality' for details on this encoding.
  2829. The usefulness of equating a register to a fixed label is probably
  2830. limited to the return address register. Here, it can be useful to mark
  2831. a code segment that has only one return address which is reached by a
  2832. direct branch and no copy of the return address exists in memory or
  2833. another register.
  2834. 
  2835. File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops
  2836. 7.11 '.comm SYMBOL , LENGTH '
  2837. =============================
  2838. '.comm' declares a common symbol named SYMBOL. When linking, a common
  2839. symbol in one object file may be merged with a defined or common symbol
  2840. of the same name in another object file. If 'ld' does not see a
  2841. definition for the symbol-just one or more common symbols-then it will
  2842. allocate LENGTH bytes of uninitialized memory. LENGTH must be an
  2843. absolute expression. If 'ld' sees multiple common symbols with the same
  2844. name, and they do not all have the same size, it will allocate space
  2845. using the largest size.
  2846. When using ELF or (as a GNU extension) PE, the '.comm' directive
  2847. takes an optional third argument. This is the desired alignment of the
  2848. symbol, specified for ELF as a byte boundary (for example, an alignment
  2849. of 16 means that the least significant 4 bits of the address should be
  2850. zero), and for PE as a power of two (for example, an alignment of 5
  2851. means aligned to a 32-byte boundary). The alignment must be an absolute
  2852. expression, and it must be a power of two. If 'ld' allocates
  2853. uninitialized memory for the common symbol, it will use the alignment
  2854. when placing the symbol. If no alignment is specified, 'as' will set
  2855. the alignment to the largest power of two less than or equal to the size
  2856. of the symbol, up to a maximum of 16 on ELF, or the default section
  2857. alignment of 4 on PE(1).
  2858. The syntax for '.comm' differs slightly on the HPPA. The syntax is
  2859. 'SYMBOL .comm, LENGTH'; SYMBOL is optional.
  2860. ---------- Footnotes ----------
  2861. (1) This is not the same as the executable image file alignment
  2862. controlled by 'ld''s '--section-alignment' option; image file sections
  2863. in PE are aligned to multiples of 4096, which is far too large an
  2864. alignment for ordinary variables. It is rather the default alignment
  2865. for (non-debug) sections within object ('*.o') files, which are less
  2866. strictly aligned.
  2867. 
  2868. File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops
  2869. 7.12 '.data SUBSECTION'
  2870. =======================
  2871. '.data' tells 'as' to assemble the following statements onto the end of
  2872. the data subsection numbered SUBSECTION (which is an absolute
  2873. expression). If SUBSECTION is omitted, it defaults to zero.
  2874. 
  2875. File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops
  2876. 7.13 '.def NAME'
  2877. ================
  2878. Begin defining debugging information for a symbol NAME; the definition
  2879. extends until the '.endef' directive is encountered.
  2880. 
  2881. File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops
  2882. 7.14 '.desc SYMBOL, ABS-EXPRESSION'
  2883. ===================================
  2884. This directive sets the descriptor of the symbol (*note Symbol
  2885. Attributes::) to the low 16 bits of an absolute expression.
  2886. The '.desc' directive is not available when 'as' is configured for
  2887. COFF output; it is only for 'a.out' or 'b.out' object format. For the
  2888. sake of compatibility, 'as' accepts it, but produces no output, when
  2889. configured for COFF.
  2890. 
  2891. File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops
  2892. 7.15 '.dim'
  2893. ===========
  2894. This directive is generated by compilers to include auxiliary debugging
  2895. information in the symbol table. It is only permitted inside
  2896. '.def'/'.endef' pairs.
  2897. 
  2898. File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops
  2899. 7.16 '.double FLONUMS'
  2900. ======================
  2901. '.double' expects zero or more flonums, separated by commas. It
  2902. assembles floating point numbers. The exact kind of floating point
  2903. numbers emitted depends on how 'as' is configured. *Note Machine
  2904. Dependencies::.
  2905. 
  2906. File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops
  2907. 7.17 '.eject'
  2908. =============
  2909. Force a page break at this point, when generating assembly listings.
  2910. 
  2911. File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops
  2912. 7.18 '.else'
  2913. ============
  2914. '.else' is part of the 'as' support for conditional assembly; see *note
  2915. '.if': If. It marks the beginning of a section of code to be assembled
  2916. if the condition for the preceding '.if' was false.
  2917. 
  2918. File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops
  2919. 7.19 '.elseif'
  2920. ==============
  2921. '.elseif' is part of the 'as' support for conditional assembly; see
  2922. *note '.if': If. It is shorthand for beginning a new '.if' block that
  2923. would otherwise fill the entire '.else' section.
  2924. 
  2925. File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops
  2926. 7.20 '.end'
  2927. ===========
  2928. '.end' marks the end of the assembly file. 'as' does not process
  2929. anything in the file past the '.end' directive.
  2930. 
  2931. File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops
  2932. 7.21 '.endef'
  2933. =============
  2934. This directive flags the end of a symbol definition begun with '.def'.
  2935. 
  2936. File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops
  2937. 7.22 '.endfunc'
  2938. ===============
  2939. '.endfunc' marks the end of a function specified with '.func'.
  2940. 
  2941. File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops
  2942. 7.23 '.endif'
  2943. =============
  2944. '.endif' is part of the 'as' support for conditional assembly; it marks
  2945. the end of a block of code that is only assembled conditionally. *Note
  2946. '.if': If.
  2947. 
  2948. File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops
  2949. 7.24 '.equ SYMBOL, EXPRESSION'
  2950. ==============================
  2951. This directive sets the value of SYMBOL to EXPRESSION. It is synonymous
  2952. with '.set'; see *note '.set': Set.
  2953. The syntax for 'equ' on the HPPA is 'SYMBOL .equ EXPRESSION'.
  2954. The syntax for 'equ' on the Z80 is 'SYMBOL equ EXPRESSION'. On the
  2955. Z80 it is an eror if SYMBOL is already defined, but the symbol is not
  2956. protected from later redefinition. Compare *note Equiv::.
  2957. 
  2958. File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops
  2959. 7.25 '.equiv SYMBOL, EXPRESSION'
  2960. ================================
  2961. The '.equiv' directive is like '.equ' and '.set', except that the
  2962. assembler will signal an error if SYMBOL is already defined. Note a
  2963. symbol which has been referenced but not actually defined is considered
  2964. to be undefined.
  2965. Except for the contents of the error message, this is roughly
  2966. equivalent to
  2967. .ifdef SYM
  2968. .err
  2969. .endif
  2970. .equ SYM,VAL
  2971. plus it protects the symbol from later redefinition.
  2972. 
  2973. File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops
  2974. 7.26 '.eqv SYMBOL, EXPRESSION'
  2975. ==============================
  2976. The '.eqv' directive is like '.equiv', but no attempt is made to
  2977. evaluate the expression or any part of it immediately. Instead each
  2978. time the resulting symbol is used in an expression, a snapshot of its
  2979. current value is taken.
  2980. 
  2981. File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops
  2982. 7.27 '.err'
  2983. ===========
  2984. If 'as' assembles a '.err' directive, it will print an error message
  2985. and, unless the '-Z' option was used, it will not generate an object
  2986. file. This can be used to signal an error in conditionally compiled
  2987. code.
  2988. 
  2989. File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops
  2990. 7.28 '.error "STRING"'
  2991. ======================
  2992. Similarly to '.err', this directive emits an error, but you can specify
  2993. a string that will be emitted as the error message. If you don't
  2994. specify the message, it defaults to '".error directive invoked in source
  2995. file"'. *Note Error and Warning Messages: Errors.
  2996. .error "This code has not been assembled and tested."
  2997. 
  2998. File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops
  2999. 7.29 '.exitm'
  3000. =============
  3001. Exit early from the current macro definition. *Note Macro::.
  3002. 
  3003. File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops
  3004. 7.30 '.extern'
  3005. ==============
  3006. '.extern' is accepted in the source program--for compatibility with
  3007. other assemblers--but it is ignored. 'as' treats all undefined symbols
  3008. as external.
  3009. 
  3010. File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops
  3011. 7.31 '.fail EXPRESSION'
  3012. =======================
  3013. Generates an error or a warning. If the value of the EXPRESSION is 500
  3014. or more, 'as' will print a warning message. If the value is less than
  3015. 500, 'as' will print an error message. The message will include the
  3016. value of EXPRESSION. This can occasionally be useful inside complex
  3017. nested macros or conditional assembly.
  3018. 
  3019. File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops
  3020. 7.32 '.file'
  3021. ============
  3022. There are two different versions of the '.file' directive. Targets that
  3023. support DWARF2 line number information use the DWARF2 version of
  3024. '.file'. Other targets use the default version.
  3025. Default Version
  3026. ---------------
  3027. This version of the '.file' directive tells 'as' that we are about to
  3028. start a new logical file. The syntax is:
  3029. .file STRING
  3030. STRING is the new file name. In general, the filename is recognized
  3031. whether or not it is surrounded by quotes '"'; but if you wish to
  3032. specify an empty file name, you must give the quotes-'""'. This
  3033. statement may go away in future: it is only recognized to be compatible
  3034. with old 'as' programs.
  3035. DWARF2 Version
  3036. --------------
  3037. When emitting DWARF2 line number information, '.file' assigns filenames
  3038. to the '.debug_line' file name table. The syntax is:
  3039. .file FILENO FILENAME
  3040. The FILENO operand should be a unique positive integer to use as the
  3041. index of the entry in the table. The FILENAME operand is a C string
  3042. literal.
  3043. The detail of filename indices is exposed to the user because the
  3044. filename table is shared with the '.debug_info' section of the DWARF2
  3045. debugging information, and thus the user must know the exact indices
  3046. that table entries will have.
  3047. 
  3048. File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops
  3049. 7.33 '.fill REPEAT , SIZE , VALUE'
  3050. ==================================
  3051. REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT
  3052. copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or
  3053. more, but if it is more than 8, then it is deemed to have the value 8,
  3054. compatible with other people's assemblers. The contents of each REPEAT
  3055. bytes is taken from an 8-byte number. The highest order 4 bytes are
  3056. zero. The lowest order 4 bytes are VALUE rendered in the byte-order of
  3057. an integer on the computer 'as' is assembling for. Each SIZE bytes in a
  3058. repetition is taken from the lowest order SIZE bytes of this number.
  3059. Again, this bizarre behavior is compatible with other people's
  3060. assemblers.
  3061. SIZE and VALUE are optional. If the second comma and VALUE are
  3062. absent, VALUE is assumed zero. If the first comma and following tokens
  3063. are absent, SIZE is assumed to be 1.
  3064. 
  3065. File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops
  3066. 7.34 '.float FLONUMS'
  3067. =====================
  3068. This directive assembles zero or more flonums, separated by commas. It
  3069. has the same effect as '.single'. The exact kind of floating point
  3070. numbers emitted depends on how 'as' is configured. *Note Machine
  3071. Dependencies::.
  3072. 
  3073. File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops
  3074. 7.35 '.func NAME[,LABEL]'
  3075. =========================
  3076. '.func' emits debugging information to denote function NAME, and is
  3077. ignored unless the file is assembled with debugging enabled. Only
  3078. '--gstabs[+]' is currently supported. LABEL is the entry point of the
  3079. function and if omitted NAME prepended with the 'leading char' is used.
  3080. 'leading char' is usually '_' or nothing, depending on the target. All
  3081. functions are currently defined to have 'void' return type. The
  3082. function must be terminated with '.endfunc'.
  3083. 
  3084. File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops
  3085. 7.36 '.global SYMBOL', '.globl SYMBOL'
  3086. ======================================
  3087. '.global' makes the symbol visible to 'ld'. If you define SYMBOL in
  3088. your partial program, its value is made available to other partial
  3089. programs that are linked with it. Otherwise, SYMBOL takes its
  3090. attributes from a symbol of the same name from another file linked into
  3091. the same program.
  3092. Both spellings ('.globl' and '.global') are accepted, for
  3093. compatibility with other assemblers.
  3094. On the HPPA, '.global' is not always enough to make it accessible to
  3095. other partial programs. You may need the HPPA-only '.EXPORT' directive
  3096. as well. *Note HPPA Assembler Directives: HPPA Directives.
  3097. 
  3098. File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops
  3099. 7.37 '.gnu_attribute TAG,VALUE'
  3100. ===============================
  3101. Record a GNU object attribute for this file. *Note Object Attributes::.
  3102. 
  3103. File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops
  3104. 7.38 '.hidden NAMES'
  3105. ====================
  3106. This is one of the ELF visibility directives. The other two are
  3107. '.internal' (*note '.internal': Internal.) and '.protected' (*note
  3108. '.protected': Protected.).
  3109. This directive overrides the named symbols default visibility (which
  3110. is set by their binding: local, global or weak). The directive sets the
  3111. visibility to 'hidden' which means that the symbols are not visible to
  3112. other components. Such symbols are always considered to be 'protected'
  3113. as well.
  3114. 
  3115. File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops
  3116. 7.39 '.hword EXPRESSIONS'
  3117. =========================
  3118. This expects zero or more EXPRESSIONS, and emits a 16 bit number for
  3119. each.
  3120. This directive is a synonym for '.short'; depending on the target
  3121. architecture, it may also be a synonym for '.word'.
  3122. 
  3123. File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops
  3124. 7.40 '.ident'
  3125. =============
  3126. This directive is used by some assemblers to place tags in object files.
  3127. The behavior of this directive varies depending on the target. When
  3128. using the a.out object file format, 'as' simply accepts the directive
  3129. for source-file compatibility with existing assemblers, but does not
  3130. emit anything for it. When using COFF, comments are emitted to the
  3131. '.comment' or '.rdata' section, depending on the target. When using
  3132. ELF, comments are emitted to the '.comment' section.
  3133. 
  3134. File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops
  3135. 7.41 '.if ABSOLUTE EXPRESSION'
  3136. ==============================
  3137. '.if' marks the beginning of a section of code which is only considered
  3138. part of the source program being assembled if the argument (which must
  3139. be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional
  3140. section of code must be marked by '.endif' (*note '.endif': Endif.);
  3141. optionally, you may include code for the alternative condition, flagged
  3142. by '.else' (*note '.else': Else.). If you have several conditions to
  3143. check, '.elseif' may be used to avoid nesting blocks if/else within each
  3144. subsequent '.else' block.
  3145. The following variants of '.if' are also supported:
  3146. '.ifdef SYMBOL'
  3147. Assembles the following section of code if the specified SYMBOL has
  3148. been defined. Note a symbol which has been referenced but not yet
  3149. defined is considered to be undefined.
  3150. '.ifb TEXT'
  3151. Assembles the following section of code if the operand is blank
  3152. (empty).
  3153. '.ifc STRING1,STRING2'
  3154. Assembles the following section of code if the two strings are the
  3155. same. The strings may be optionally quoted with single quotes. If
  3156. they are not quoted, the first string stops at the first comma, and
  3157. the second string stops at the end of the line. Strings which
  3158. contain whitespace should be quoted. The string comparison is case
  3159. sensitive.
  3160. '.ifeq ABSOLUTE EXPRESSION'
  3161. Assembles the following section of code if the argument is zero.
  3162. '.ifeqs STRING1,STRING2'
  3163. Another form of '.ifc'. The strings must be quoted using double
  3164. quotes.
  3165. '.ifge ABSOLUTE EXPRESSION'
  3166. Assembles the following section of code if the argument is greater
  3167. than or equal to zero.
  3168. '.ifgt ABSOLUTE EXPRESSION'
  3169. Assembles the following section of code if the argument is greater
  3170. than zero.
  3171. '.ifle ABSOLUTE EXPRESSION'
  3172. Assembles the following section of code if the argument is less
  3173. than or equal to zero.
  3174. '.iflt ABSOLUTE EXPRESSION'
  3175. Assembles the following section of code if the argument is less
  3176. than zero.
  3177. '.ifnb TEXT'
  3178. Like '.ifb', but the sense of the test is reversed: this assembles
  3179. the following section of code if the operand is non-blank
  3180. (non-empty).
  3181. '.ifnc STRING1,STRING2.'
  3182. Like '.ifc', but the sense of the test is reversed: this assembles
  3183. the following section of code if the two strings are not the same.
  3184. '.ifndef SYMBOL'
  3185. '.ifnotdef SYMBOL'
  3186. Assembles the following section of code if the specified SYMBOL has
  3187. not been defined. Both spelling variants are equivalent. Note a
  3188. symbol which has been referenced but not yet defined is considered
  3189. to be undefined.
  3190. '.ifne ABSOLUTE EXPRESSION'
  3191. Assembles the following section of code if the argument is not
  3192. equal to zero (in other words, this is equivalent to '.if').
  3193. '.ifnes STRING1,STRING2'
  3194. Like '.ifeqs', but the sense of the test is reversed: this
  3195. assembles the following section of code if the two strings are not
  3196. the same.
  3197. 
  3198. File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops
  3199. 7.42 '.incbin "FILE"[,SKIP[,COUNT]]'
  3200. ====================================
  3201. The 'incbin' directive includes FILE verbatim at the current location.
  3202. You can control the search paths used with the '-I' command-line option
  3203. (*note Command-Line Options: Invoking.). Quotation marks are required
  3204. around FILE.
  3205. The SKIP argument skips a number of bytes from the start of the FILE.
  3206. The COUNT argument indicates the maximum number of bytes to read. Note
  3207. that the data is not aligned in any way, so it is the user's
  3208. responsibility to make sure that proper alignment is provided both
  3209. before and after the 'incbin' directive.
  3210. 
  3211. File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops
  3212. 7.43 '.include "FILE"'
  3213. ======================
  3214. This directive provides a way to include supporting files at specified
  3215. points in your source program. The code from FILE is assembled as if it
  3216. followed the point of the '.include'; when the end of the included file
  3217. is reached, assembly of the original file continues. You can control
  3218. the search paths used with the '-I' command-line option (*note
  3219. Command-Line Options: Invoking.). Quotation marks are required around
  3220. FILE.
  3221. 
  3222. File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops
  3223. 7.44 '.int EXPRESSIONS'
  3224. =======================
  3225. Expect zero or more EXPRESSIONS, of any section, separated by commas.
  3226. For each expression, emit a number that, at run time, is the value of
  3227. that expression. The byte order and bit size of the number depends on
  3228. what kind of target the assembly is for.
  3229. 
  3230. File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops
  3231. 7.45 '.internal NAMES'
  3232. ======================
  3233. This is one of the ELF visibility directives. The other two are
  3234. '.hidden' (*note '.hidden': Hidden.) and '.protected' (*note
  3235. '.protected': Protected.).
  3236. This directive overrides the named symbols default visibility (which
  3237. is set by their binding: local, global or weak). The directive sets the
  3238. visibility to 'internal' which means that the symbols are considered to
  3239. be 'hidden' (i.e., not visible to other components), and that some
  3240. extra, processor specific processing must also be performed upon the
  3241. symbols as well.
  3242. 
  3243. File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops
  3244. 7.46 '.irp SYMBOL,VALUES'...
  3245. ============================
  3246. Evaluate a sequence of statements assigning different values to SYMBOL.
  3247. The sequence of statements starts at the '.irp' directive, and is
  3248. terminated by an '.endr' directive. For each VALUE, SYMBOL is set to
  3249. VALUE, and the sequence of statements is assembled. If no VALUE is
  3250. listed, the sequence of statements is assembled once, with SYMBOL set to
  3251. the null string. To refer to SYMBOL within the sequence of statements,
  3252. use \SYMBOL.
  3253. For example, assembling
  3254. .irp param,1,2,3
  3255. move d\param,sp@-
  3256. .endr
  3257. is equivalent to assembling
  3258. move d1,sp@-
  3259. move d2,sp@-
  3260. move d3,sp@-
  3261. For some caveats with the spelling of SYMBOL, see also *note Macro::.
  3262. 
  3263. File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops
  3264. 7.47 '.irpc SYMBOL,VALUES'...
  3265. =============================
  3266. Evaluate a sequence of statements assigning different values to SYMBOL.
  3267. The sequence of statements starts at the '.irpc' directive, and is
  3268. terminated by an '.endr' directive. For each character in VALUE, SYMBOL
  3269. is set to the character, and the sequence of statements is assembled.
  3270. If no VALUE is listed, the sequence of statements is assembled once,
  3271. with SYMBOL set to the null string. To refer to SYMBOL within the
  3272. sequence of statements, use \SYMBOL.
  3273. For example, assembling
  3274. .irpc param,123
  3275. move d\param,sp@-
  3276. .endr
  3277. is equivalent to assembling
  3278. move d1,sp@-
  3279. move d2,sp@-
  3280. move d3,sp@-
  3281. For some caveats with the spelling of SYMBOL, see also the discussion
  3282. at *Note Macro::.
  3283. 
  3284. File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops
  3285. 7.48 '.lcomm SYMBOL , LENGTH'
  3286. =============================
  3287. Reserve LENGTH (an absolute expression) bytes for a local common denoted
  3288. by SYMBOL. The section and value of SYMBOL are those of the new local
  3289. common. The addresses are allocated in the bss section, so that at
  3290. run-time the bytes start off zeroed. SYMBOL is not declared global
  3291. (*note '.global': Global.), so is normally not visible to 'ld'.
  3292. Some targets permit a third argument to be used with '.lcomm'. This
  3293. argument specifies the desired alignment of the symbol in the bss
  3294. section.
  3295. The syntax for '.lcomm' differs slightly on the HPPA. The syntax is
  3296. 'SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
  3297. 
  3298. File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops
  3299. 7.49 '.lflags'
  3300. ==============
  3301. 'as' accepts this directive, for compatibility with other assemblers,
  3302. but ignores it.
  3303. 
  3304. File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops
  3305. 7.50 '.line LINE-NUMBER'
  3306. ========================
  3307. Change the logical line number. LINE-NUMBER must be an absolute
  3308. expression. The next line has that logical line number. Therefore any
  3309. other statements on the current line (after a statement separator
  3310. character) are reported as on logical line number LINE-NUMBER - 1. One
  3311. day 'as' will no longer support this directive: it is recognized only
  3312. for compatibility with existing assembler programs.
  3313. Even though this is a directive associated with the 'a.out' or
  3314. 'b.out' object-code formats, 'as' still recognizes it when producing
  3315. COFF output, and treats '.line' as though it were the COFF '.ln' _if_ it
  3316. is found outside a '.def'/'.endef' pair.
  3317. Inside a '.def', '.line' is, instead, one of the directives used by
  3318. compilers to generate auxiliary symbol information for debugging.
  3319. 
  3320. File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops
  3321. 7.51 '.linkonce [TYPE]'
  3322. =======================
  3323. Mark the current section so that the linker only includes a single copy
  3324. of it. This may be used to include the same section in several
  3325. different object files, but ensure that the linker will only include it
  3326. once in the final output file. The '.linkonce' pseudo-op must be used
  3327. for each instance of the section. Duplicate sections are detected based
  3328. on the section name, so it should be unique.
  3329. This directive is only supported by a few object file formats; as of
  3330. this writing, the only object file format which supports it is the
  3331. Portable Executable format used on Windows NT.
  3332. The TYPE argument is optional. If specified, it must be one of the
  3333. following strings. For example:
  3334. .linkonce same_size
  3335. Not all types may be supported on all object file formats.
  3336. 'discard'
  3337. Silently discard duplicate sections. This is the default.
  3338. 'one_only'
  3339. Warn if there are duplicate sections, but still keep only one copy.
  3340. 'same_size'
  3341. Warn if any of the duplicates have different sizes.
  3342. 'same_contents'
  3343. Warn if any of the duplicates do not have exactly the same
  3344. contents.
  3345. 
  3346. File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops
  3347. 7.52 '.list'
  3348. ============
  3349. Control (in conjunction with the '.nolist' directive) whether or not
  3350. assembly listings are generated. These two directives maintain an
  3351. internal counter (which is zero initially). '.list' increments the
  3352. counter, and '.nolist' decrements it. Assembly listings are generated
  3353. whenever the counter is greater than zero.
  3354. By default, listings are disabled. When you enable them (with the
  3355. '-a' command line option; *note Command-Line Options: Invoking.), the
  3356. initial value of the listing counter is one.
  3357. 
  3358. File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops
  3359. 7.53 '.ln LINE-NUMBER'
  3360. ======================
  3361. '.ln' is a synonym for '.line'.
  3362. 
  3363. File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops
  3364. 7.54 '.loc FILENO LINENO [COLUMN] [OPTIONS]'
  3365. ============================================
  3366. When emitting DWARF2 line number information, the '.loc' directive will
  3367. add a row to the '.debug_line' line number matrix corresponding to the
  3368. immediately following assembly instruction. The FILENO, LINENO, and
  3369. optional COLUMN arguments will be applied to the '.debug_line' state
  3370. machine before the row is added.
  3371. The OPTIONS are a sequence of the following tokens in any order:
  3372. 'basic_block'
  3373. This option will set the 'basic_block' register in the
  3374. '.debug_line' state machine to 'true'.
  3375. 'prologue_end'
  3376. This option will set the 'prologue_end' register in the
  3377. '.debug_line' state machine to 'true'.
  3378. 'epilogue_begin'
  3379. This option will set the 'epilogue_begin' register in the
  3380. '.debug_line' state machine to 'true'.
  3381. 'is_stmt VALUE'
  3382. This option will set the 'is_stmt' register in the '.debug_line'
  3383. state machine to 'value', which must be either 0 or 1.
  3384. 'isa VALUE'
  3385. This directive will set the 'isa' register in the '.debug_line'
  3386. state machine to VALUE, which must be an unsigned integer.
  3387. 'discriminator VALUE'
  3388. This directive will set the 'discriminator' register in the
  3389. '.debug_line' state machine to VALUE, which must be an unsigned
  3390. integer.
  3391. 
  3392. File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops
  3393. 7.55 '.loc_mark_labels ENABLE'
  3394. ==============================
  3395. When emitting DWARF2 line number information, the '.loc_mark_labels'
  3396. directive makes the assembler emit an entry to the '.debug_line' line
  3397. number matrix with the 'basic_block' register in the state machine set
  3398. whenever a code label is seen. The ENABLE argument should be either 1
  3399. or 0, to enable or disable this function respectively.
  3400. 
  3401. File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops
  3402. 7.56 '.local NAMES'
  3403. ===================
  3404. This directive, which is available for ELF targets, marks each symbol in
  3405. the comma-separated list of 'names' as a local symbol so that it will
  3406. not be externally visible. If the symbols do not already exist, they
  3407. will be created.
  3408. For targets where the '.lcomm' directive (*note Lcomm::) does not
  3409. accept an alignment argument, which is the case for most ELF targets,
  3410. the '.local' directive can be used in combination with '.comm' (*note
  3411. Comm::) to define aligned local common data.
  3412. 
  3413. File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops
  3414. 7.57 '.long EXPRESSIONS'
  3415. ========================
  3416. '.long' is the same as '.int'. *Note '.int': Int.
  3417. 
  3418. File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops
  3419. 7.58 '.macro'
  3420. =============
  3421. The commands '.macro' and '.endm' allow you to define macros that
  3422. generate assembly output. For example, this definition specifies a
  3423. macro 'sum' that puts a sequence of numbers into memory:
  3424. .macro sum from=0, to=5
  3425. .long \from
  3426. .if \to-\from
  3427. sum "(\from+1)",\to
  3428. .endif
  3429. .endm
  3430. With that definition, 'SUM 0,5' is equivalent to this assembly input:
  3431. .long 0
  3432. .long 1
  3433. .long 2
  3434. .long 3
  3435. .long 4
  3436. .long 5
  3437. '.macro MACNAME'
  3438. '.macro MACNAME MACARGS ...'
  3439. Begin the definition of a macro called MACNAME. If your macro
  3440. definition requires arguments, specify their names after the macro
  3441. name, separated by commas or spaces. You can qualify the macro
  3442. argument to indicate whether all invocations must specify a
  3443. non-blank value (through ':'req''), or whether it takes all of the
  3444. remaining arguments (through ':'vararg''). You can supply a
  3445. default value for any macro argument by following the name with
  3446. '=DEFLT'. You cannot define two macros with the same MACNAME
  3447. unless it has been subject to the '.purgem' directive (*note
  3448. Purgem::) between the two definitions. For example, these are all
  3449. valid '.macro' statements:
  3450. '.macro comm'
  3451. Begin the definition of a macro called 'comm', which takes no
  3452. arguments.
  3453. '.macro plus1 p, p1'
  3454. '.macro plus1 p p1'
  3455. Either statement begins the definition of a macro called
  3456. 'plus1', which takes two arguments; within the macro
  3457. definition, write '\p' or '\p1' to evaluate the arguments.
  3458. '.macro reserve_str p1=0 p2'
  3459. Begin the definition of a macro called 'reserve_str', with two
  3460. arguments. The first argument has a default value, but not
  3461. the second. After the definition is complete, you can call
  3462. the macro either as 'reserve_str A,B' (with '\p1' evaluating
  3463. to A and '\p2' evaluating to B), or as 'reserve_str ,B' (with
  3464. '\p1' evaluating as the default, in this case '0', and '\p2'
  3465. evaluating to B).
  3466. '.macro m p1:req, p2=0, p3:vararg'
  3467. Begin the definition of a macro called 'm', with at least
  3468. three arguments. The first argument must always have a value
  3469. specified, but not the second, which instead has a default
  3470. value. The third formal will get assigned all remaining
  3471. arguments specified at invocation time.
  3472. When you call a macro, you can specify the argument values
  3473. either by position, or by keyword. For example, 'sum 9,17' is
  3474. equivalent to 'sum to=17, from=9'.
  3475. Note that since each of the MACARGS can be an identifier exactly as
  3476. any other one permitted by the target architecture, there may be
  3477. occasional problems if the target hand-crafts special meanings to
  3478. certain characters when they occur in a special position. For
  3479. example, if the colon (':') is generally permitted to be part of a
  3480. symbol name, but the architecture specific code special-cases it
  3481. when occurring as the final character of a symbol (to denote a
  3482. label), then the macro parameter replacement code will have no way
  3483. of knowing that and consider the whole construct (including the
  3484. colon) an identifier, and check only this identifier for being the
  3485. subject to parameter substitution. So for example this macro
  3486. definition:
  3487. .macro label l
  3488. \l:
  3489. .endm
  3490. might not work as expected. Invoking 'label foo' might not create
  3491. a label called 'foo' but instead just insert the text '\l:' into
  3492. the assembler source, probably generating an error about an
  3493. unrecognised identifier.
  3494. Similarly problems might occur with the period character ('.')
  3495. which is often allowed inside opcode names (and hence identifier
  3496. names). So for example constructing a macro to build an opcode
  3497. from a base name and a length specifier like this:
  3498. .macro opcode base length
  3499. \base.\length
  3500. .endm
  3501. and invoking it as 'opcode store l' will not create a 'store.l'
  3502. instruction but instead generate some kind of error as the
  3503. assembler tries to interpret the text '\base.\length'.
  3504. There are several possible ways around this problem:
  3505. 'Insert white space'
  3506. If it is possible to use white space characters then this is
  3507. the simplest solution. eg:
  3508. .macro label l
  3509. \l :
  3510. .endm
  3511. 'Use '\()''
  3512. The string '\()' can be used to separate the end of a macro
  3513. argument from the following text. eg:
  3514. .macro opcode base length
  3515. \base\().\length
  3516. .endm
  3517. 'Use the alternate macro syntax mode'
  3518. In the alternative macro syntax mode the ampersand character
  3519. ('&') can be used as a separator. eg:
  3520. .altmacro
  3521. .macro label l
  3522. l&:
  3523. .endm
  3524. Note: this problem of correctly identifying string parameters to
  3525. pseudo ops also applies to the identifiers used in '.irp' (*note
  3526. Irp::) and '.irpc' (*note Irpc::) as well.
  3527. '.endm'
  3528. Mark the end of a macro definition.
  3529. '.exitm'
  3530. Exit early from the current macro definition.
  3531. '\@'
  3532. 'as' maintains a counter of how many macros it has executed in this
  3533. pseudo-variable; you can copy that number to your output with '\@',
  3534. but _only within a macro definition_.
  3535. 'LOCAL NAME [ , ... ]'
  3536. _Warning: 'LOCAL' is only available if you select "alternate macro
  3537. syntax" with '--alternate' or '.altmacro'._ *Note '.altmacro':
  3538. Altmacro.
  3539. 
  3540. File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops
  3541. 7.59 '.mri VAL'
  3542. ===============
  3543. If VAL is non-zero, this tells 'as' to enter MRI mode. If VAL is zero,
  3544. this tells 'as' to exit MRI mode. This change affects code assembled
  3545. until the next '.mri' directive, or until the end of the file. *Note
  3546. MRI mode: M.
  3547. 
  3548. File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops
  3549. 7.60 '.noaltmacro'
  3550. ==================
  3551. Disable alternate macro mode. *Note Altmacro::.
  3552. 
  3553. File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops
  3554. 7.61 '.nolist'
  3555. ==============
  3556. Control (in conjunction with the '.list' directive) whether or not
  3557. assembly listings are generated. These two directives maintain an
  3558. internal counter (which is zero initially). '.list' increments the
  3559. counter, and '.nolist' decrements it. Assembly listings are generated
  3560. whenever the counter is greater than zero.
  3561. 
  3562. File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops
  3563. 7.62 '.octa BIGNUMS'
  3564. ====================
  3565. This directive expects zero or more bignums, separated by commas. For
  3566. each bignum, it emits a 16-byte integer.
  3567. The term "octa" comes from contexts in which a "word" is two bytes;
  3568. hence _octa_-word for 16 bytes.
  3569. 
  3570. File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops
  3571. 7.63 '.offset LOC'
  3572. ==================
  3573. Set the location counter to LOC in the absolute section. LOC must be an
  3574. absolute expression. This directive may be useful for defining symbols
  3575. with absolute values. Do not confuse it with the '.org' directive.
  3576. 
  3577. File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops
  3578. 7.64 '.org NEW-LC , FILL'
  3579. =========================
  3580. Advance the location counter of the current section to NEW-LC. NEW-LC
  3581. is either an absolute expression or an expression with the same section
  3582. as the current subsection. That is, you can't use '.org' to cross
  3583. sections: if NEW-LC has the wrong section, the '.org' directive is
  3584. ignored. To be compatible with former assemblers, if the section of
  3585. NEW-LC is absolute, 'as' issues a warning, then pretends the section of
  3586. NEW-LC is the same as the current subsection.
  3587. '.org' may only increase the location counter, or leave it unchanged;
  3588. you cannot use '.org' to move the location counter backwards.
  3589. Because 'as' tries to assemble programs in one pass, NEW-LC may not
  3590. be undefined. If you really detest this restriction we eagerly await a
  3591. chance to share your improved assembler.
  3592. Beware that the origin is relative to the start of the section, not
  3593. to the start of the subsection. This is compatible with other people's
  3594. assemblers.
  3595. When the location counter (of the current subsection) is advanced,
  3596. the intervening bytes are filled with FILL which should be an absolute
  3597. expression. If the comma and FILL are omitted, FILL defaults to zero.
  3598. 
  3599. File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops
  3600. 7.65 '.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
  3601. ================================================
  3602. Pad the location counter (in the current subsection) to a particular
  3603. storage boundary. The first expression (which must be absolute) is the
  3604. number of low-order zero bits the location counter must have after
  3605. advancement. For example '.p2align 3' advances the location counter
  3606. until it a multiple of 8. If the location counter is already a multiple
  3607. of 8, no change is needed.
  3608. The second expression (also absolute) gives the fill value to be
  3609. stored in the padding bytes. It (and the comma) may be omitted. If it
  3610. is omitted, the padding bytes are normally zero. However, on some
  3611. systems, if the section is marked as containing code and the fill value
  3612. is omitted, the space is filled with no-op instructions.
  3613. The third expression is also absolute, and is also optional. If it
  3614. is present, it is the maximum number of bytes that should be skipped by
  3615. this alignment directive. If doing the alignment would require skipping
  3616. more bytes than the specified maximum, then the alignment is not done at
  3617. all. You can omit the fill value (the second argument) entirely by
  3618. simply using two commas after the required alignment; this can be useful
  3619. if you want the alignment to be filled with no-op instructions when
  3620. appropriate.
  3621. The '.p2alignw' and '.p2alignl' directives are variants of the
  3622. '.p2align' directive. The '.p2alignw' directive treats the fill pattern
  3623. as a two byte word value. The '.p2alignl' directives treats the fill
  3624. pattern as a four byte longword value. For example, '.p2alignw
  3625. 2,0x368d' will align to a multiple of 4. If it skips two bytes, they
  3626. will be filled in with the value 0x368d (the exact placement of the
  3627. bytes depends upon the endianness of the processor). If it skips 1 or 3
  3628. bytes, the fill value is undefined.
  3629. 
  3630. File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops
  3631. 7.66 '.popsection'
  3632. ==================
  3633. This is one of the ELF section stack manipulation directives. The
  3634. others are '.section' (*note Section::), '.subsection' (*note
  3635. SubSection::), '.pushsection' (*note PushSection::), and '.previous'
  3636. (*note Previous::).
  3637. This directive replaces the current section (and subsection) with the
  3638. top section (and subsection) on the section stack. This section is
  3639. popped off the stack.
  3640. 
  3641. File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops
  3642. 7.67 '.previous'
  3643. ================
  3644. This is one of the ELF section stack manipulation directives. The
  3645. others are '.section' (*note Section::), '.subsection' (*note
  3646. SubSection::), '.pushsection' (*note PushSection::), and '.popsection'
  3647. (*note PopSection::).
  3648. This directive swaps the current section (and subsection) with most
  3649. recently referenced section/subsection pair prior to this one. Multiple
  3650. '.previous' directives in a row will flip between two sections (and
  3651. their subsections). For example:
  3652. .section A
  3653. .subsection 1
  3654. .word 0x1234
  3655. .subsection 2
  3656. .word 0x5678
  3657. .previous
  3658. .word 0x9abc
  3659. Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into
  3660. subsection 2 of section A. Whilst:
  3661. .section A
  3662. .subsection 1
  3663. # Now in section A subsection 1
  3664. .word 0x1234
  3665. .section B
  3666. .subsection 0
  3667. # Now in section B subsection 0
  3668. .word 0x5678
  3669. .subsection 1
  3670. # Now in section B subsection 1
  3671. .word 0x9abc
  3672. .previous
  3673. # Now in section B subsection 0
  3674. .word 0xdef0
  3675. Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0
  3676. of section B and 0x9abc into subsection 1 of section B.
  3677. In terms of the section stack, this directive swaps the current
  3678. section with the top section on the section stack.
  3679. 
  3680. File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops
  3681. 7.68 '.print STRING'
  3682. ====================
  3683. 'as' will print STRING on the standard output during assembly. You must
  3684. put STRING in double quotes.
  3685. 
  3686. File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops
  3687. 7.69 '.protected NAMES'
  3688. =======================
  3689. This is one of the ELF visibility directives. The other two are
  3690. '.hidden' (*note Hidden::) and '.internal' (*note Internal::).
  3691. This directive overrides the named symbols default visibility (which
  3692. is set by their binding: local, global or weak). The directive sets the
  3693. visibility to 'protected' which means that any references to the symbols
  3694. from within the components that defines them must be resolved to the
  3695. definition in that component, even if a definition in another component
  3696. would normally preempt this.
  3697. 
  3698. File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops
  3699. 7.70 '.psize LINES , COLUMNS'
  3700. =============================
  3701. Use this directive to declare the number of lines--and, optionally, the
  3702. number of columns--to use for each page, when generating listings.
  3703. If you do not use '.psize', listings use a default line-count of 60.
  3704. You may omit the comma and COLUMNS specification; the default width is
  3705. 200 columns.
  3706. 'as' generates formfeeds whenever the specified number of lines is
  3707. exceeded (or whenever you explicitly request one, using '.eject').
  3708. If you specify LINES as '0', no formfeeds are generated save those
  3709. explicitly specified with '.eject'.
  3710. 
  3711. File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops
  3712. 7.71 '.purgem NAME'
  3713. ===================
  3714. Undefine the macro NAME, so that later uses of the string will not be
  3715. expanded. *Note Macro::.
  3716. 
  3717. File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops
  3718. 7.72 '.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]'
  3719. ========================================================================
  3720. This is one of the ELF section stack manipulation directives. The
  3721. others are '.section' (*note Section::), '.subsection' (*note
  3722. SubSection::), '.popsection' (*note PopSection::), and '.previous'
  3723. (*note Previous::).
  3724. This directive pushes the current section (and subsection) onto the
  3725. top of the section stack, and then replaces the current section and
  3726. subsection with 'name' and 'subsection'. The optional 'flags', 'type'
  3727. and 'arguments' are treated the same as in the '.section' (*note
  3728. Section::) directive.
  3729. 
  3730. File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops
  3731. 7.73 '.quad BIGNUMS'
  3732. ====================
  3733. '.quad' expects zero or more bignums, separated by commas. For each
  3734. bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes,
  3735. it prints a warning message; and just takes the lowest order 8 bytes of
  3736. the bignum.
  3737. The term "quad" comes from contexts in which a "word" is two bytes;
  3738. hence _quad_-word for 8 bytes.
  3739. 
  3740. File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops
  3741. 7.74 '.reloc OFFSET, RELOC_NAME[, EXPRESSION]'
  3742. ==============================================
  3743. Generate a relocation at OFFSET of type RELOC_NAME with value
  3744. EXPRESSION. If OFFSET is a number, the relocation is generated in the
  3745. current section. If OFFSET is an expression that resolves to a symbol
  3746. plus offset, the relocation is generated in the given symbol's section.
  3747. EXPRESSION, if present, must resolve to a symbol plus addend or to an
  3748. absolute value, but note that not all targets support an addend. e.g.
  3749. ELF REL targets such as i386 store an addend in the section contents
  3750. rather than in the relocation. This low level interface does not
  3751. support addends stored in the section.
  3752. 
  3753. File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops
  3754. 7.75 '.rept COUNT'
  3755. ==================
  3756. Repeat the sequence of lines between the '.rept' directive and the next
  3757. '.endr' directive COUNT times.
  3758. For example, assembling
  3759. .rept 3
  3760. .long 0
  3761. .endr
  3762. is equivalent to assembling
  3763. .long 0
  3764. .long 0
  3765. .long 0
  3766. 
  3767. File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops
  3768. 7.76 '.sbttl "SUBHEADING"'
  3769. ==========================
  3770. Use SUBHEADING as the title (third line, immediately after the title
  3771. line) when generating assembly listings.
  3772. This directive affects subsequent pages, as well as the current page
  3773. if it appears within ten lines of the top of a page.
  3774. 
  3775. File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops
  3776. 7.77 '.scl CLASS'
  3777. =================
  3778. Set the storage-class value for a symbol. This directive may only be
  3779. used inside a '.def'/'.endef' pair. Storage class may flag whether a
  3780. symbol is static or external, or it may record further symbolic
  3781. debugging information.
  3782. 
  3783. File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops
  3784. 7.78 '.section NAME'
  3785. ====================
  3786. Use the '.section' directive to assemble the following code into a
  3787. section named NAME.
  3788. This directive is only supported for targets that actually support
  3789. arbitrarily named sections; on 'a.out' targets, for example, it is not
  3790. accepted, even with a standard 'a.out' section name.
  3791. COFF Version
  3792. ------------
  3793. For COFF targets, the '.section' directive is used in one of the
  3794. following ways:
  3795. .section NAME[, "FLAGS"]
  3796. .section NAME[, SUBSECTION]
  3797. If the optional argument is quoted, it is taken as flags to use for
  3798. the section. Each flag is a single character. The following flags are
  3799. recognized:
  3800. 'b'
  3801. bss section (uninitialized data)
  3802. 'n'
  3803. section is not loaded
  3804. 'w'
  3805. writable section
  3806. 'd'
  3807. data section
  3808. 'e'
  3809. exclude section from linking
  3810. 'r'
  3811. read-only section
  3812. 'x'
  3813. executable section
  3814. 's'
  3815. shared section (meaningful for PE targets)
  3816. 'a'
  3817. ignored. (For compatibility with the ELF version)
  3818. 'y'
  3819. section is not readable (meaningful for PE targets)
  3820. '0-9'
  3821. single-digit power-of-two section alignment (GNU extension)
  3822. If no flags are specified, the default flags depend upon the section
  3823. name. If the section name is not recognized, the default will be for
  3824. the section to be loaded and writable. Note the 'n' and 'w' flags
  3825. remove attributes from the section, rather than adding them, so if they
  3826. are used on their own it will be as if no flags had been specified at
  3827. all.
  3828. If the optional argument to the '.section' directive is not quoted,
  3829. it is taken as a subsection number (*note Sub-Sections::).
  3830. ELF Version
  3831. -----------
  3832. This is one of the ELF section stack manipulation directives. The
  3833. others are '.subsection' (*note SubSection::), '.pushsection' (*note
  3834. PushSection::), '.popsection' (*note PopSection::), and '.previous'
  3835. (*note Previous::).
  3836. For ELF targets, the '.section' directive is used like this:
  3837. .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
  3838. If the '--sectname-subst' command-line option is provided, the NAME
  3839. argument may contain a substitution sequence. Only '%S' is supported at
  3840. the moment, and substitutes the current section name. For example:
  3841. .macro exception_code
  3842. .section %S.exception
  3843. [exception code here]
  3844. .previous
  3845. .endm
  3846. .text
  3847. [code]
  3848. exception_code
  3849. [...]
  3850. .section .init
  3851. [init code]
  3852. exception_code
  3853. [...]
  3854. The two 'exception_code' invocations above would create the
  3855. '.text.exception' and '.init.exception' sections respectively. This is
  3856. useful e.g. to discriminate between anciliary sections that are tied to
  3857. setup code to be discarded after use from anciliary sections that need
  3858. to stay resident without having to define multiple 'exception_code'
  3859. macros just for that purpose.
  3860. The optional FLAGS argument is a quoted string which may contain any
  3861. combination of the following characters:
  3862. 'a'
  3863. section is allocatable
  3864. 'e'
  3865. section is excluded from executable and shared library.
  3866. 'w'
  3867. section is writable
  3868. 'x'
  3869. section is executable
  3870. 'M'
  3871. section is mergeable
  3872. 'S'
  3873. section contains zero terminated strings
  3874. 'G'
  3875. section is a member of a section group
  3876. 'T'
  3877. section is used for thread-local-storage
  3878. '?'
  3879. section is a member of the previously-current section's group, if
  3880. any
  3881. '<number>'
  3882. a numeric value indicating the bits to be set in the ELF section
  3883. header's flags field. Note - if one or more of the alphabetic
  3884. characters described above is also included in the flags field,
  3885. their bit values will be ORed into the resulting value.
  3886. '<target specific>'
  3887. some targets extend this list with their own flag characters
  3888. Note - once a section's flags have been set they cannot be changed.
  3889. There are a few exceptions to this rule however. Processor and
  3890. application specific flags can be added to an already defined section.
  3891. The '.interp', '.strtab' and '.symtab' sections can have the allocate
  3892. flag ('a') set after they are initially defined, and the
  3893. '.note-GNU-stack' section may have the executable ('x') flag added.
  3894. The optional TYPE argument may contain one of the following
  3895. constants:
  3896. '@progbits'
  3897. section contains data
  3898. '@nobits'
  3899. section does not contain data (i.e., section only occupies space)
  3900. '@note'
  3901. section contains data which is used by things other than the
  3902. program
  3903. '@init_array'
  3904. section contains an array of pointers to init functions
  3905. '@fini_array'
  3906. section contains an array of pointers to finish functions
  3907. '@preinit_array'
  3908. section contains an array of pointers to pre-init functions
  3909. '@<number>'
  3910. a numeric value to be set as the ELF section header's type field.
  3911. '@<target specific>'
  3912. some targets extend this list with their own types
  3913. Many targets only support the first three section types. The type
  3914. may be enclosed in double quotes if necessary.
  3915. Note on targets where the '@' character is the start of a comment (eg
  3916. ARM) then another character is used instead. For example the ARM port
  3917. uses the '%' character.
  3918. Note - some sections, eg '.text' and '.data' are considered to be
  3919. special and have fixed types. Any attempt to declare them with a
  3920. different type will generate an error from the assembler.
  3921. If FLAGS contains the 'M' symbol then the TYPE argument must be
  3922. specified as well as an extra argument--ENTSIZE--like this:
  3923. .section NAME , "FLAGS"M, @TYPE, ENTSIZE
  3924. Sections with the 'M' flag but not 'S' flag must contain fixed size
  3925. constants, each ENTSIZE octets long. Sections with both 'M' and 'S'
  3926. must contain zero terminated strings where each character is ENTSIZE
  3927. bytes long. The linker may remove duplicates within sections with the
  3928. same name, same entity size and same flags. ENTSIZE must be an absolute
  3929. expression. For sections with both 'M' and 'S', a string which is a
  3930. suffix of a larger string is considered a duplicate. Thus '"def"' will
  3931. be merged with '"abcdef"'; A reference to the first '"def"' will be
  3932. changed to a reference to '"abcdef"+3'.
  3933. If FLAGS contains the 'G' symbol then the TYPE argument must be
  3934. present along with an additional field like this:
  3935. .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
  3936. The GROUPNAME field specifies the name of the section group to which
  3937. this particular section belongs. The optional linkage field can
  3938. contain:
  3939. 'comdat'
  3940. indicates that only one copy of this section should be retained
  3941. '.gnu.linkonce'
  3942. an alias for comdat
  3943. Note: if both the M and G flags are present then the fields for the
  3944. Merge flag should come first, like this:
  3945. .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
  3946. If FLAGS contains the '?' symbol then it may not also contain the 'G'
  3947. symbol and the GROUPNAME or LINKAGE fields should not be present.
  3948. Instead, '?' says to consider the section that's current before this
  3949. directive. If that section used 'G', then the new section will use 'G'
  3950. with those same GROUPNAME and LINKAGE fields implicitly. If not, then
  3951. the '?' symbol has no effect.
  3952. If no flags are specified, the default flags depend upon the section
  3953. name. If the section name is not recognized, the default will be for
  3954. the section to have none of the above flags: it will not be allocated in
  3955. memory, nor writable, nor executable. The section will contain data.
  3956. For ELF targets, the assembler supports another type of '.section'
  3957. directive for compatibility with the Solaris assembler:
  3958. .section "NAME"[, FLAGS...]
  3959. Note that the section name is quoted. There may be a sequence of
  3960. comma separated flags:
  3961. '#alloc'
  3962. section is allocatable
  3963. '#write'
  3964. section is writable
  3965. '#execinstr'
  3966. section is executable
  3967. '#exclude'
  3968. section is excluded from executable and shared library.
  3969. '#tls'
  3970. section is used for thread local storage
  3971. This directive replaces the current section and subsection. See the
  3972. contents of the gas testsuite directory 'gas/testsuite/gas/elf' for some
  3973. examples of how this directive and the other section stack directives
  3974. work.
  3975. 
  3976. File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops
  3977. 7.79 '.set SYMBOL, EXPRESSION'
  3978. ==============================
  3979. Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and
  3980. type to conform to EXPRESSION. If SYMBOL was flagged as external, it
  3981. remains flagged (*note Symbol Attributes::).
  3982. You may '.set' a symbol many times in the same assembly provided that
  3983. the values given to the symbol are constants. Values that are based on
  3984. expressions involving other symbols are allowed, but some targets may
  3985. restrict this to only being done once per assembly. This is because
  3986. those targets do not set the addresses of symbols at assembly time, but
  3987. rather delay the assignment until a final link is performed. This
  3988. allows the linker a chance to change the code in the files, changing the
  3989. location of, and the relative distance between, various different
  3990. symbols.
  3991. If you '.set' a global symbol, the value stored in the object file is
  3992. the last value stored into it.
  3993. On Z80 'set' is a real instruction, use 'SYMBOL defl EXPRESSION'
  3994. instead.
  3995. 
  3996. File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops
  3997. 7.80 '.short EXPRESSIONS'
  3998. =========================
  3999. '.short' is normally the same as '.word'. *Note '.word': Word.
  4000. In some configurations, however, '.short' and '.word' generate
  4001. numbers of different lengths. *Note Machine Dependencies::.
  4002. 
  4003. File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops
  4004. 7.81 '.single FLONUMS'
  4005. ======================
  4006. This directive assembles zero or more flonums, separated by commas. It
  4007. has the same effect as '.float'. The exact kind of floating point
  4008. numbers emitted depends on how 'as' is configured. *Note Machine
  4009. Dependencies::.
  4010. 
  4011. File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops
  4012. 7.82 '.size'
  4013. ============
  4014. This directive is used to set the size associated with a symbol.
  4015. COFF Version
  4016. ------------
  4017. For COFF targets, the '.size' directive is only permitted inside
  4018. '.def'/'.endef' pairs. It is used like this:
  4019. .size EXPRESSION
  4020. ELF Version
  4021. -----------
  4022. For ELF targets, the '.size' directive is used like this:
  4023. .size NAME , EXPRESSION
  4024. This directive sets the size associated with a symbol NAME. The size
  4025. in bytes is computed from EXPRESSION which can make use of label
  4026. arithmetic. This directive is typically used to set the size of
  4027. function symbols.
  4028. 
  4029. File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops
  4030. 7.83 '.skip SIZE , FILL'
  4031. ========================
  4032. This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL
  4033. are absolute expressions. If the comma and FILL are omitted, FILL is
  4034. assumed to be zero. This is the same as '.space'.
  4035. 
  4036. File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops
  4037. 7.84 '.sleb128 EXPRESSIONS'
  4038. ===========================
  4039. SLEB128 stands for "signed little endian base 128." This is a compact,
  4040. variable length representation of numbers used by the DWARF symbolic
  4041. debugging format. *Note '.uleb128': Uleb128.
  4042. 
  4043. File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops
  4044. 7.85 '.space SIZE , FILL'
  4045. =========================
  4046. This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL
  4047. are absolute expressions. If the comma and FILL are omitted, FILL is
  4048. assumed to be zero. This is the same as '.skip'.
  4049. _Warning:_ '.space' has a completely different meaning for HPPA
  4050. targets; use '.block' as a substitute. See 'HP9000 Series 800
  4051. Assembly Language Reference Manual' (HP 92432-90001) for the
  4052. meaning of the '.space' directive. *Note HPPA Assembler
  4053. Directives: HPPA Directives, for a summary.
  4054. 
  4055. File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops
  4056. 7.86 '.stabd, .stabn, .stabs'
  4057. =============================
  4058. There are three directives that begin '.stab'. All emit symbols (*note
  4059. Symbols::), for use by symbolic debuggers. The symbols are not entered
  4060. in the 'as' hash table: they cannot be referenced elsewhere in the
  4061. source file. Up to five fields are required:
  4062. STRING
  4063. This is the symbol's name. It may contain any character except
  4064. '\000', so is more general than ordinary symbol names. Some
  4065. debuggers used to code arbitrarily complex structures into symbol
  4066. names using this field.
  4067. TYPE
  4068. An absolute expression. The symbol's type is set to the low 8 bits
  4069. of this expression. Any bit pattern is permitted, but 'ld' and
  4070. debuggers choke on silly bit patterns.
  4071. OTHER
  4072. An absolute expression. The symbol's "other" attribute is set to
  4073. the low 8 bits of this expression.
  4074. DESC
  4075. An absolute expression. The symbol's descriptor is set to the low
  4076. 16 bits of this expression.
  4077. VALUE
  4078. An absolute expression which becomes the symbol's value.
  4079. If a warning is detected while reading a '.stabd', '.stabn', or
  4080. '.stabs' statement, the symbol has probably already been created; you
  4081. get a half-formed symbol in your object file. This is compatible with
  4082. earlier assemblers!
  4083. '.stabd TYPE , OTHER , DESC'
  4084. The "name" of the symbol generated is not even an empty string. It
  4085. is a null pointer, for compatibility. Older assemblers used a null
  4086. pointer so they didn't waste space in object files with empty
  4087. strings.
  4088. The symbol's value is set to the location counter, relocatably.
  4089. When your program is linked, the value of this symbol is the
  4090. address of the location counter when the '.stabd' was assembled.
  4091. '.stabn TYPE , OTHER , DESC , VALUE'
  4092. The name of the symbol is set to the empty string '""'.
  4093. '.stabs STRING , TYPE , OTHER , DESC , VALUE'
  4094. All five fields are specified.
  4095. 
  4096. File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops
  4097. 7.87 '.string' "STR", '.string8' "STR", '.string16'
  4098. ===================================================
  4099. "STR", '.string32' "STR", '.string64' "STR"
  4100. Copy the characters in STR to the object file. You may specify more
  4101. than one string to copy, separated by commas. Unless otherwise
  4102. specified for a particular machine, the assembler marks the end of each
  4103. string with a 0 byte. You can use any of the escape sequences described
  4104. in *note Strings: Strings.
  4105. The variants 'string16', 'string32' and 'string64' differ from the
  4106. 'string' pseudo opcode in that each 8-bit character from STR is copied
  4107. and expanded to 16, 32 or 64 bits respectively. The expanded characters
  4108. are stored in target endianness byte order.
  4109. Example:
  4110. .string32 "BYE"
  4111. expands to:
  4112. .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */
  4113. .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */
  4114. 
  4115. File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops
  4116. 7.88 '.struct EXPRESSION'
  4117. =========================
  4118. Switch to the absolute section, and set the section offset to
  4119. EXPRESSION, which must be an absolute expression. You might use this as
  4120. follows:
  4121. .struct 0
  4122. field1:
  4123. .struct field1 + 4
  4124. field2:
  4125. .struct field2 + 4
  4126. field3:
  4127. This would define the symbol 'field1' to have the value 0, the symbol
  4128. 'field2' to have the value 4, and the symbol 'field3' to have the value
  4129. 8. Assembly would be left in the absolute section, and you would need
  4130. to use a '.section' directive of some sort to change to some other
  4131. section before further assembly.
  4132. 
  4133. File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops
  4134. 7.89 '.subsection NAME'
  4135. =======================
  4136. This is one of the ELF section stack manipulation directives. The
  4137. others are '.section' (*note Section::), '.pushsection' (*note
  4138. PushSection::), '.popsection' (*note PopSection::), and '.previous'
  4139. (*note Previous::).
  4140. This directive replaces the current subsection with 'name'. The
  4141. current section is not changed. The replaced subsection is put onto the
  4142. section stack in place of the then current top of stack subsection.
  4143. 
  4144. File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops
  4145. 7.90 '.symver'
  4146. ==============
  4147. Use the '.symver' directive to bind symbols to specific version nodes
  4148. within a source file. This is only supported on ELF platforms, and is
  4149. typically used when assembling files to be linked into a shared library.
  4150. There are cases where it may make sense to use this in objects to be
  4151. bound into an application itself so as to override a versioned symbol
  4152. from a shared library.
  4153. For ELF targets, the '.symver' directive can be used like this:
  4154. .symver NAME, NAME2@NODENAME
  4155. If the symbol NAME is defined within the file being assembled, the
  4156. '.symver' directive effectively creates a symbol alias with the name
  4157. NAME2@NODENAME, and in fact the main reason that we just don't try and
  4158. create a regular alias is that the @ character isn't permitted in symbol
  4159. names. The NAME2 part of the name is the actual name of the symbol by
  4160. which it will be externally referenced. The name NAME itself is merely
  4161. a name of convenience that is used so that it is possible to have
  4162. definitions for multiple versions of a function within a single source
  4163. file, and so that the compiler can unambiguously know which version of a
  4164. function is being mentioned. The NODENAME portion of the alias should
  4165. be the name of a node specified in the version script supplied to the
  4166. linker when building a shared library. If you are attempting to
  4167. override a versioned symbol from a shared library, then NODENAME should
  4168. correspond to the nodename of the symbol you are trying to override.
  4169. If the symbol NAME is not defined within the file being assembled,
  4170. all references to NAME will be changed to NAME2@NODENAME. If no
  4171. reference to NAME is made, NAME2@NODENAME will be removed from the
  4172. symbol table.
  4173. Another usage of the '.symver' directive is:
  4174. .symver NAME, NAME2@@NODENAME
  4175. In this case, the symbol NAME must exist and be defined within the
  4176. file being assembled. It is similar to NAME2@NODENAME. The difference
  4177. is NAME2@@NODENAME will also be used to resolve references to NAME2 by
  4178. the linker.
  4179. The third usage of the '.symver' directive is:
  4180. .symver NAME, NAME2@@@NODENAME
  4181. When NAME is not defined within the file being assembled, it is
  4182. treated as NAME2@NODENAME. When NAME is defined within the file being
  4183. assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
  4184. 
  4185. File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops
  4186. 7.91 '.tag STRUCTNAME'
  4187. ======================
  4188. This directive is generated by compilers to include auxiliary debugging
  4189. information in the symbol table. It is only permitted inside
  4190. '.def'/'.endef' pairs. Tags are used to link structure definitions in
  4191. the symbol table with instances of those structures.
  4192. 
  4193. File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops
  4194. 7.92 '.text SUBSECTION'
  4195. =======================
  4196. Tells 'as' to assemble the following statements onto the end of the text
  4197. subsection numbered SUBSECTION, which is an absolute expression. If
  4198. SUBSECTION is omitted, subsection number zero is used.
  4199. 
  4200. File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops
  4201. 7.93 '.title "HEADING"'
  4202. =======================
  4203. Use HEADING as the title (second line, immediately after the source file
  4204. name and pagenumber) when generating assembly listings.
  4205. This directive affects subsequent pages, as well as the current page
  4206. if it appears within ten lines of the top of a page.
  4207. 
  4208. File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops
  4209. 7.94 '.type'
  4210. ============
  4211. This directive is used to set the type of a symbol.
  4212. COFF Version
  4213. ------------
  4214. For COFF targets, this directive is permitted only within
  4215. '.def'/'.endef' pairs. It is used like this:
  4216. .type INT
  4217. This records the integer INT as the type attribute of a symbol table
  4218. entry.
  4219. ELF Version
  4220. -----------
  4221. For ELF targets, the '.type' directive is used like this:
  4222. .type NAME , TYPE DESCRIPTION
  4223. This sets the type of symbol NAME to be either a function symbol or
  4224. an object symbol. There are five different syntaxes supported for the
  4225. TYPE DESCRIPTION field, in order to provide compatibility with various
  4226. other assemblers.
  4227. Because some of the characters used in these syntaxes (such as '@'
  4228. and '#') are comment characters for some architectures, some of the
  4229. syntaxes below do not work on all architectures. The first variant will
  4230. be accepted by the GNU assembler on all architectures so that variant
  4231. should be used for maximum portability, if you do not need to assemble
  4232. your code with other assemblers.
  4233. The syntaxes supported are:
  4234. .type <name> STT_<TYPE_IN_UPPER_CASE>
  4235. .type <name>,#<type>
  4236. .type <name>,@<type>
  4237. .type <name>,%<type>
  4238. .type <name>,"<type>"
  4239. The types supported are:
  4240. 'STT_FUNC'
  4241. 'function'
  4242. Mark the symbol as being a function name.
  4243. 'STT_GNU_IFUNC'
  4244. 'gnu_indirect_function'
  4245. Mark the symbol as an indirect function when evaluated during reloc
  4246. processing. (This is only supported on assemblers targeting GNU
  4247. systems).
  4248. 'STT_OBJECT'
  4249. 'object'
  4250. Mark the symbol as being a data object.
  4251. 'STT_TLS'
  4252. 'tls_object'
  4253. Mark the symbol as being a thead-local data object.
  4254. 'STT_COMMON'
  4255. 'common'
  4256. Mark the symbol as being a common data object.
  4257. 'STT_NOTYPE'
  4258. 'notype'
  4259. Does not mark the symbol in any way. It is supported just for
  4260. completeness.
  4261. 'gnu_unique_object'
  4262. Marks the symbol as being a globally unique data object. The
  4263. dynamic linker will make sure that in the entire process there is
  4264. just one symbol with this name and type in use. (This is only
  4265. supported on assemblers targeting GNU systems).
  4266. Note: Some targets support extra types in addition to those listed
  4267. above.
  4268. 
  4269. File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops
  4270. 7.95 '.uleb128 EXPRESSIONS'
  4271. ===========================
  4272. ULEB128 stands for "unsigned little endian base 128." This is a
  4273. compact, variable length representation of numbers used by the DWARF
  4274. symbolic debugging format. *Note '.sleb128': Sleb128.
  4275. 
  4276. File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops
  4277. 7.96 '.val ADDR'
  4278. ================
  4279. This directive, permitted only within '.def'/'.endef' pairs, records the
  4280. address ADDR as the value attribute of a symbol table entry.
  4281. 
  4282. File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops
  4283. 7.97 '.version "STRING"'
  4284. ========================
  4285. This directive creates a '.note' section and places into it an ELF
  4286. formatted note of type NT_VERSION. The note's name is set to 'string'.
  4287. 
  4288. File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops
  4289. 7.98 '.vtable_entry TABLE, OFFSET'
  4290. ==================================
  4291. This directive finds or creates a symbol 'table' and creates a
  4292. 'VTABLE_ENTRY' relocation for it with an addend of 'offset'.
  4293. 
  4294. File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops
  4295. 7.99 '.vtable_inherit CHILD, PARENT'
  4296. ====================================
  4297. This directive finds the symbol 'child' and finds or creates the symbol
  4298. 'parent' and then creates a 'VTABLE_INHERIT' relocation for the parent
  4299. whose addend is the value of the child symbol. As a special case the
  4300. parent name of '0' is treated as referring to the '*ABS*' section.
  4301. 
  4302. File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops
  4303. 7.100 '.warning "STRING"'
  4304. =========================
  4305. Similar to the directive '.error' (*note '.error "STRING"': Error.), but
  4306. just emits a warning.
  4307. 
  4308. File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops
  4309. 7.101 '.weak NAMES'
  4310. ===================
  4311. This directive sets the weak attribute on the comma separated list of
  4312. symbol 'names'. If the symbols do not already exist, they will be
  4313. created.
  4314. On COFF targets other than PE, weak symbols are a GNU extension.
  4315. This directive sets the weak attribute on the comma separated list of
  4316. symbol 'names'. If the symbols do not already exist, they will be
  4317. created.
  4318. On the PE target, weak symbols are supported natively as weak
  4319. aliases. When a weak symbol is created that is not an alias, GAS
  4320. creates an alternate symbol to hold the default value.
  4321. 
  4322. File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops
  4323. 7.102 '.weakref ALIAS, TARGET'
  4324. ==============================
  4325. This directive creates an alias to the target symbol that enables the
  4326. symbol to be referenced with weak-symbol semantics, but without actually
  4327. making it weak. If direct references or definitions of the symbol are
  4328. present, then the symbol will not be weak, but if all references to it
  4329. are through weak references, the symbol will be marked as weak in the
  4330. symbol table.
  4331. The effect is equivalent to moving all references to the alias to a
  4332. separate assembly source file, renaming the alias to the symbol in it,
  4333. declaring the symbol as weak there, and running a reloadable link to
  4334. merge the object files resulting from the assembly of the new source
  4335. file and the old source file that had the references to the alias
  4336. removed.
  4337. The alias itself never makes to the symbol table, and is entirely
  4338. handled within the assembler.
  4339. 
  4340. File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops
  4341. 7.103 '.word EXPRESSIONS'
  4342. =========================
  4343. This directive expects zero or more EXPRESSIONS, of any section,
  4344. separated by commas.
  4345. The size of the number emitted, and its byte order, depend on what
  4346. target computer the assembly is for.
  4347. _Warning: Special Treatment to support Compilers_
  4348. Machines with a 32-bit address space, but that do less than 32-bit
  4349. addressing, require the following special treatment. If the machine of
  4350. interest to you does 32-bit addressing (or doesn't require it; *note
  4351. Machine Dependencies::), you can ignore this issue.
  4352. In order to assemble compiler output into something that works, 'as'
  4353. occasionally does strange things to '.word' directives. Directives of
  4354. the form '.word sym1-sym2' are often emitted by compilers as part of
  4355. jump tables. Therefore, when 'as' assembles a directive of the form
  4356. '.word sym1-sym2', and the difference between 'sym1' and 'sym2' does not
  4357. fit in 16 bits, 'as' creates a "secondary jump table", immediately
  4358. before the next label. This secondary jump table is preceded by a
  4359. short-jump to the first byte after the secondary table. This short-jump
  4360. prevents the flow of control from accidentally falling into the new
  4361. table. Inside the table is a long-jump to 'sym2'. The original '.word'
  4362. contains 'sym1' minus the address of the long-jump to 'sym2'.
  4363. If there were several occurrences of '.word sym1-sym2' before the
  4364. secondary jump table, all of them are adjusted. If there was a '.word
  4365. sym3-sym4', that also did not fit in sixteen bits, a long-jump to 'sym4'
  4366. is included in the secondary jump table, and the '.word' directives are
  4367. adjusted to contain 'sym3' minus the address of the long-jump to 'sym4';
  4368. and so on, for as many entries in the original jump table as necessary.
  4369. 
  4370. File: as.info, Node: Zero, Next: Deprecated, Prev: Word, Up: Pseudo Ops
  4371. 7.104 '.zero SIZE'
  4372. ==================
  4373. This directive emits SIZE 0-valued bytes. SIZE must be an absolute
  4374. expression. This directive is actually an alias for the '.skip'
  4375. directive so in can take an optional second argument of the value to
  4376. store in the bytes instead of zero. Using '.zero' in this way would be
  4377. confusing however.
  4378. 
  4379. File: as.info, Node: Deprecated, Prev: Zero, Up: Pseudo Ops
  4380. 7.105 Deprecated Directives
  4381. ===========================
  4382. One day these directives won't work. They are included for
  4383. compatibility with older assemblers.
  4384. .abort
  4385. .line
  4386. 
  4387. File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top
  4388. 8 Object Attributes
  4389. *******************
  4390. 'as' assembles source files written for a specific architecture into
  4391. object files for that architecture. But not all object files are alike.
  4392. Many architectures support incompatible variations. For instance,
  4393. floating point arguments might be passed in floating point registers if
  4394. the object file requires hardware floating point support--or floating
  4395. point arguments might be passed in integer registers if the object file
  4396. supports processors with no hardware floating point unit. Or, if two
  4397. objects are built for different generations of the same architecture,
  4398. the combination may require the newer generation at run-time.
  4399. This information is useful during and after linking. At link time,
  4400. 'ld' can warn about incompatible object files. After link time, tools
  4401. like 'gdb' can use it to process the linked file correctly.
  4402. Compatibility information is recorded as a series of object
  4403. attributes. Each attribute has a "vendor", "tag", and "value". The
  4404. vendor is a string, and indicates who sets the meaning of the tag. The
  4405. tag is an integer, and indicates what property the attribute describes.
  4406. The value may be a string or an integer, and indicates how the property
  4407. affects this object. Missing attributes are the same as attributes with
  4408. a zero value or empty string value.
  4409. Object attributes were developed as part of the ABI for the ARM
  4410. Architecture. The file format is documented in 'ELF for the ARM
  4411. Architecture'.
  4412. * Menu:
  4413. * GNU Object Attributes:: GNU Object Attributes
  4414. * Defining New Object Attributes:: Defining New Object Attributes
  4415. 
  4416. File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes
  4417. 8.1 GNU Object Attributes
  4418. =========================
  4419. The '.gnu_attribute' directive records an object attribute with vendor
  4420. 'gnu'.
  4421. Except for 'Tag_compatibility', which has both an integer and a
  4422. string for its value, GNU attributes have a string value if the tag
  4423. number is odd and an integer value if the tag number is even. The
  4424. second bit ('TAG & 2' is set for architecture-independent attributes and
  4425. clear for architecture-dependent ones.
  4426. 8.1.1 Common GNU attributes
  4427. ---------------------------
  4428. These attributes are valid on all architectures.
  4429. Tag_compatibility (32)
  4430. The compatibility attribute takes an integer flag value and a
  4431. vendor name. If the flag value is 0, the file is compatible with
  4432. other toolchains. If it is 1, then the file is only compatible
  4433. with the named toolchain. If it is greater than 1, the file can
  4434. only be processed by other toolchains under some private
  4435. arrangement indicated by the flag value and the vendor name.
  4436. 8.1.2 MIPS Attributes
  4437. ---------------------
  4438. Tag_GNU_MIPS_ABI_FP (4)
  4439. The floating-point ABI used by this object file. The value will
  4440. be:
  4441. * 0 for files not affected by the floating-point ABI.
  4442. * 1 for files using the hardware floating-point ABI with a
  4443. standard double-precision FPU.
  4444. * 2 for files using the hardware floating-point ABI with a
  4445. single-precision FPU.
  4446. * 3 for files using the software floating-point ABI.
  4447. * 4 for files using the deprecated hardware floating-point ABI
  4448. which used 64-bit floating-point registers, 32-bit
  4449. general-purpose registers and increased the number of
  4450. callee-saved floating-point registers.
  4451. * 5 for files using the hardware floating-point ABI with a
  4452. double-precision FPU with either 32-bit or 64-bit
  4453. floating-point registers and 32-bit general-purpose registers.
  4454. * 6 for files using the hardware floating-point ABI with 64-bit
  4455. floating-point registers and 32-bit general-purpose registers.
  4456. * 7 for files using the hardware floating-point ABI with 64-bit
  4457. floating-point registers, 32-bit general-purpose registers and
  4458. a rule that forbids the direct use of odd-numbered
  4459. single-precision floating-point registers.
  4460. 8.1.3 PowerPC Attributes
  4461. ------------------------
  4462. Tag_GNU_Power_ABI_FP (4)
  4463. The floating-point ABI used by this object file. The value will
  4464. be:
  4465. * 0 for files not affected by the floating-point ABI.
  4466. * 1 for files using double-precision hardware floating-point
  4467. ABI.
  4468. * 2 for files using the software floating-point ABI.
  4469. * 3 for files using single-precision hardware floating-point
  4470. ABI.
  4471. Tag_GNU_Power_ABI_Vector (8)
  4472. The vector ABI used by this object file. The value will be:
  4473. * 0 for files not affected by the vector ABI.
  4474. * 1 for files using general purpose registers to pass vectors.
  4475. * 2 for files using AltiVec registers to pass vectors.
  4476. * 3 for files using SPE registers to pass vectors.
  4477. 8.1.4 IBM z Systems Attributes
  4478. ------------------------------
  4479. Tag_GNU_S390_ABI_Vector (8)
  4480. The vector ABI used by this object file. The value will be:
  4481. * 0 for files not affected by the vector ABI.
  4482. * 1 for files using software vector ABI.
  4483. * 2 for files using hardware vector ABI.
  4484. 
  4485. File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes
  4486. 8.2 Defining New Object Attributes
  4487. ==================================
  4488. If you want to define a new GNU object attribute, here are the places
  4489. you will need to modify. New attributes should be discussed on the
  4490. 'binutils' mailing list.
  4491. * This manual, which is the official register of attributes.
  4492. * The header for your architecture 'include/elf', to define the tag.
  4493. * The 'bfd' support file for your architecture, to merge the
  4494. attribute and issue any appropriate link warnings.
  4495. * Test cases in 'ld/testsuite' for merging and link warnings.
  4496. * 'binutils/readelf.c' to display your attribute.
  4497. * GCC, if you want the compiler to mark the attribute automatically.
  4498. 
  4499. File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top
  4500. 9 Machine Dependent Features
  4501. ****************************
  4502. The machine instruction sets are (almost by definition) different on
  4503. each machine where 'as' runs. Floating point representations vary as
  4504. well, and 'as' often supports a few additional directives or
  4505. command-line options for compatibility with other assemblers on a
  4506. particular platform. Finally, some versions of 'as' support special
  4507. pseudo-instructions for branch optimization.
  4508. This chapter discusses most of these differences, though it does not
  4509. include details on any machine's instruction set. For details on that
  4510. subject, see the hardware manufacturer's manual.
  4511. * Menu:
  4512. * AArch64-Dependent:: AArch64 Dependent Features
  4513. * Alpha-Dependent:: Alpha Dependent Features
  4514. * ARC-Dependent:: ARC Dependent Features
  4515. * ARM-Dependent:: ARM Dependent Features
  4516. * AVR-Dependent:: AVR Dependent Features
  4517. * Blackfin-Dependent:: Blackfin Dependent Features
  4518. * CR16-Dependent:: CR16 Dependent Features
  4519. * CRIS-Dependent:: CRIS Dependent Features
  4520. * D10V-Dependent:: D10V Dependent Features
  4521. * D30V-Dependent:: D30V Dependent Features
  4522. * Epiphany-Dependent:: EPIPHANY Dependent Features
  4523. * H8/300-Dependent:: Renesas H8/300 Dependent Features
  4524. * HPPA-Dependent:: HPPA Dependent Features
  4525. * ESA/390-Dependent:: IBM ESA/390 Dependent Features
  4526. * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
  4527. * i860-Dependent:: Intel 80860 Dependent Features
  4528. * i960-Dependent:: Intel 80960 Dependent Features
  4529. * IA-64-Dependent:: Intel IA-64 Dependent Features
  4530. * IP2K-Dependent:: IP2K Dependent Features
  4531. * LM32-Dependent:: LM32 Dependent Features
  4532. * M32C-Dependent:: M32C Dependent Features
  4533. * M32R-Dependent:: M32R Dependent Features
  4534. * M68K-Dependent:: M680x0 Dependent Features
  4535. * M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
  4536. * Meta-Dependent :: Meta Dependent Features
  4537. * MicroBlaze-Dependent:: MICROBLAZE Dependent Features
  4538. * MIPS-Dependent:: MIPS Dependent Features
  4539. * MMIX-Dependent:: MMIX Dependent Features
  4540. * MSP430-Dependent:: MSP430 Dependent Features
  4541. * NDS32-Dependent:: Andes NDS32 Dependent Features
  4542. * NiosII-Dependent:: Altera Nios II Dependent Features
  4543. * NS32K-Dependent:: NS32K Dependent Features
  4544. * PDP-11-Dependent:: PDP-11 Dependent Features
  4545. * PJ-Dependent:: picoJava Dependent Features
  4546. * PPC-Dependent:: PowerPC Dependent Features
  4547. * RL78-Dependent:: RL78 Dependent Features
  4548. * RISC-V-Dependent:: RISC-V Dependent Features
  4549. * RX-Dependent:: RX Dependent Features
  4550. * S/390-Dependent:: IBM S/390 Dependent Features
  4551. * SCORE-Dependent:: SCORE Dependent Features
  4552. * SH-Dependent:: Renesas / SuperH SH Dependent Features
  4553. * SH64-Dependent:: SuperH SH64 Dependent Features
  4554. * Sparc-Dependent:: SPARC Dependent Features
  4555. * TIC54X-Dependent:: TI TMS320C54x Dependent Features
  4556. * TIC6X-Dependent :: TI TMS320C6x Dependent Features
  4557. * TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features
  4558. * TILEPro-Dependent :: Tilera TILEPro Dependent Features
  4559. * V850-Dependent:: V850 Dependent Features
  4560. * Vax-Dependent:: VAX Dependent Features
  4561. * Visium-Dependent:: Visium Dependent Features
  4562. * XGATE-Dependent:: XGATE Features
  4563. * XSTORMY16-Dependent:: XStormy16 Dependent Features
  4564. * Xtensa-Dependent:: Xtensa Dependent Features
  4565. * Z80-Dependent:: Z80 Dependent Features
  4566. * Z8000-Dependent:: Z8000 Dependent Features
  4567. 
  4568. File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies
  4569. 9.1 AArch64 Dependent Features
  4570. ==============================
  4571. * Menu:
  4572. * AArch64 Options:: Options
  4573. * AArch64 Extensions:: Extensions
  4574. * AArch64 Syntax:: Syntax
  4575. * AArch64 Floating Point:: Floating Point
  4576. * AArch64 Directives:: AArch64 Machine Directives
  4577. * AArch64 Opcodes:: Opcodes
  4578. * AArch64 Mapping Symbols:: Mapping Symbols
  4579. 
  4580. File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent
  4581. 9.1.1 Options
  4582. -------------
  4583. '-EB'
  4584. This option specifies that the output generated by the assembler
  4585. should be marked as being encoded for a big-endian processor.
  4586. '-EL'
  4587. This option specifies that the output generated by the assembler
  4588. should be marked as being encoded for a little-endian processor.
  4589. '-mabi=ABI'
  4590. Specify which ABI the source code uses. The recognized arguments
  4591. are: 'ilp32' and 'lp64', which decides the generated object file in
  4592. ELF32 and ELF64 format respectively. The default is 'lp64'.
  4593. '-mcpu=PROCESSOR[+EXTENSION...]'
  4594. This option specifies the target processor. The assembler will
  4595. issue an error message if an attempt is made to assemble an
  4596. instruction which will not execute on the target processor. The
  4597. following processor names are recognized: 'cortex-a35',
  4598. 'cortex-a53', 'cortex-a57', 'cortex-a72', 'cortex-a73',
  4599. 'exynos-m1', 'falkor', 'qdf24xx', 'thunderx', 'vulcan', 'xgene1'
  4600. and 'xgene2'. The special name 'all' may be used to allow the
  4601. assembler to accept instructions valid for any supported processor,
  4602. including all optional extensions.
  4603. In addition to the basic instruction set, the assembler can be told
  4604. to accept, or restrict, various extension mnemonics that extend the
  4605. processor. *Note AArch64 Extensions::.
  4606. If some implementations of a particular processor can have an
  4607. extension, then then those extensions are automatically enabled.
  4608. Consequently, you will not normally have to specify any additional
  4609. extensions.
  4610. '-march=ARCHITECTURE[+EXTENSION...]'
  4611. This option specifies the target architecture. The assembler will
  4612. issue an error message if an attempt is made to assemble an
  4613. instruction which will not execute on the target architecture. The
  4614. following architecture names are recognized: 'armv8-a',
  4615. 'armv8.1-a', 'armv8.2-a' and 'armv8.3-a'.
  4616. If both '-mcpu' and '-march' are specified, the assembler will use
  4617. the setting for '-mcpu'. If neither are specified, the assembler
  4618. will default to '-mcpu=all'.
  4619. The architecture option can be extended with the same instruction
  4620. set extension options as the '-mcpu' option. Unlike '-mcpu',
  4621. extensions are not always enabled by default, *Note AArch64
  4622. Extensions::.
  4623. '-mverbose-error'
  4624. This option enables verbose error messages for AArch64 gas. This
  4625. option is enabled by default.
  4626. '-mno-verbose-error'
  4627. This option disables verbose error messages in AArch64 gas.
  4628. 
  4629. File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent
  4630. 9.1.2 Architecture Extensions
  4631. -----------------------------
  4632. The table below lists the permitted architecture extensions that are
  4633. supported by the assembler and the conditions under which they are
  4634. automatically enabled.
  4635. Multiple extensions may be specified, separated by a '+'. Extension
  4636. mnemonics may also be removed from those the assembler accepts. This is
  4637. done by prepending 'no' to the option that adds the extension.
  4638. Extensions that are removed must be listed after all extensions that
  4639. have been added.
  4640. Enabling an extension that requires other extensions will
  4641. automatically cause those extensions to be enabled. Similarly,
  4642. disabling an extension that is required by other extensions will
  4643. automatically cause those extensions to be disabled.
  4644. Extension Minimum Enabled by Description
  4645. Architecture default
  4646. ----------------------------------------------------------------------------
  4647. 'compnum' ARMv8.2-A ARMv8.3-A Enable the complex number SIMD
  4648. or later extensions. This implies 'fp16' and
  4649. 'simd'.
  4650. 'crc' ARMv8-A ARMv8.1-A Enable CRC instructions.
  4651. or later
  4652. 'crypto' ARMv8-A No Enable cryptographic extensions.
  4653. This implies 'fp' and 'simd'.
  4654. 'fp' ARMv8-A ARMv8-A or Enable floating-point extensions.
  4655. later
  4656. 'fp16' ARMv8.2-A ARMv8.2-A Enable ARMv8.2 16-bit floating-point
  4657. or later support. This implies 'fp'.
  4658. 'lor' ARMv8-A ARMv8.1-A Enable Limited Ordering Regions
  4659. or later extensions.
  4660. 'lse' ARMv8-A ARMv8.1-A Enable Large System extensions.
  4661. or later
  4662. 'pan' ARMv8-A ARMv8.1-A Enable Privileged Access Never
  4663. or later support.
  4664. 'profile' ARMv8.2-A No Enable statistical profiling
  4665. extensions.
  4666. 'ras' ARMv8-A ARMv8.2-A Enable the Reliability, Availability
  4667. or later and Serviceability extension.
  4668. 'rdma' ARMv8-A ARMv8.1-A Enable ARMv8.1 Advanced SIMD
  4669. or later extensions. This implies 'simd'.
  4670. 'simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions.
  4671. later This implies 'fp'.
  4672. 'sve' ARMv8.2-A No Enable the Scalable Vector
  4673. Extensions. This implies 'fp16',
  4674. 'simd' and 'compnum'.
  4675. 'dotprod' ARMv8.2-A No Enable the Dot Product extension.
  4676. This implies 'simd'.
  4677. 
  4678. File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent
  4679. 9.1.3 Syntax
  4680. ------------
  4681. * Menu:
  4682. * AArch64-Chars:: Special Characters
  4683. * AArch64-Regs:: Register Names
  4684. * AArch64-Relocations:: Relocations
  4685. 
  4686. File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax
  4687. 9.1.3.1 Special Characters
  4688. ..........................
  4689. The presence of a '//' on a line indicates the start of a comment that
  4690. extends to the end of the current line. If a '#' appears as the first
  4691. character of a line, the whole line is treated as a comment.
  4692. The ';' character can be used instead of a newline to separate
  4693. statements.
  4694. The '#' can be optionally used to indicate immediate operands.
  4695. 
  4696. File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax
  4697. 9.1.3.2 Register Names
  4698. ......................
  4699. Please refer to the section '4.4 Register Names' of 'ARMv8 Instruction
  4700. Set Overview', which is available at <http://infocenter.arm.com>.
  4701. 
  4702. File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax
  4703. 9.1.3.3 Relocations
  4704. ...................
  4705. Relocations for 'MOVZ' and 'MOVK' instructions can be generated by
  4706. prefixing the label with '#:abs_g2:' etc. For example to load the
  4707. 48-bit absolute address of FOO into x0:
  4708. movz x0, #:abs_g2:foo // bits 32-47, overflow check
  4709. movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
  4710. movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
  4711. Relocations for 'ADRP', and 'ADD', 'LDR' or 'STR' instructions can be
  4712. generated by prefixing the label with ':pg_hi21:' and '#:lo12:'
  4713. respectively.
  4714. For example to use 33-bit (+/-4GB) pc-relative addressing to load the
  4715. address of FOO into x0:
  4716. adrp x0, :pg_hi21:foo
  4717. add x0, x0, #:lo12:foo
  4718. Or to load the value of FOO into x0:
  4719. adrp x0, :pg_hi21:foo
  4720. ldr x0, [x0, #:lo12:foo]
  4721. Note that ':pg_hi21:' is optional.
  4722. adrp x0, foo
  4723. is equivalent to
  4724. adrp x0, :pg_hi21:foo
  4725. 
  4726. File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent
  4727. 9.1.4 Floating Point
  4728. --------------------
  4729. The AArch64 architecture uses IEEE floating-point numbers.
  4730. 
  4731. File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent
  4732. 9.1.5 AArch64 Machine Directives
  4733. --------------------------------
  4734. '.arch NAME'
  4735. Select the target architecture. Valid values for NAME are the same
  4736. as for the '-march' commandline option.
  4737. Specifying '.arch' clears any previously selected architecture
  4738. extensions.
  4739. '.arch_extension NAME'
  4740. Add or remove an architecture extension to the target architecture.
  4741. Valid values for NAME are the same as those accepted as
  4742. architectural extensions by the '-mcpu' commandline option.
  4743. '.arch_extension' may be used multiple times to add or remove
  4744. extensions incrementally to the architecture being compiled for.
  4745. '.bss'
  4746. This directive switches to the '.bss' section.
  4747. '.cpu NAME'
  4748. Set the target processor. Valid values for NAME are the same as
  4749. those accepted by the '-mcpu=' command line option.
  4750. '.dword EXPRESSIONS'
  4751. The '.dword' directive produces 64 bit values.
  4752. '.even'
  4753. The '.even' directive aligns the output on the next even byte
  4754. boundary.
  4755. '.inst EXPRESSIONS'
  4756. Inserts the expressions into the output as if they were
  4757. instructions, rather than data.
  4758. '.ltorg'
  4759. This directive causes the current contents of the literal pool to
  4760. be dumped into the current section (which is assumed to be the
  4761. .text section) at the current location (aligned to a word
  4762. boundary). GAS maintains a separate literal pool for each section
  4763. and each sub-section. The '.ltorg' directive will only affect the
  4764. literal pool of the current section and sub-section. At the end of
  4765. assembly all remaining, un-empty literal pools will automatically
  4766. be dumped.
  4767. Note - older versions of GAS would dump the current literal pool
  4768. any time a section change occurred. This is no longer done, since
  4769. it prevents accurate control of the placement of literal pools.
  4770. '.pool'
  4771. This is a synonym for .ltorg.
  4772. 'NAME .req REGISTER NAME'
  4773. This creates an alias for REGISTER NAME called NAME. For example:
  4774. foo .req w0
  4775. '.tlsdescadd'
  4776. Emits a TLSDESC_ADD reloc on the next instruction.
  4777. '.tlsdesccall'
  4778. Emits a TLSDESC_CALL reloc on the next instruction.
  4779. '.tlsdescldr'
  4780. Emits a TLSDESC_LDR reloc on the next instruction.
  4781. '.unreq ALIAS-NAME'
  4782. This undefines a register alias which was previously defined using
  4783. the 'req' directive. For example:
  4784. foo .req w0
  4785. .unreq foo
  4786. An error occurs if the name is undefined. Note - this pseudo op
  4787. can be used to delete builtin in register name aliases (eg 'w0').
  4788. This should only be done if it is really necessary.
  4789. '.xword EXPRESSIONS'
  4790. The '.xword' directive produces 64 bit values. This is the same as
  4791. the '.dword' directive.
  4792. 
  4793. File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent
  4794. 9.1.6 Opcodes
  4795. -------------
  4796. GAS implements all the standard AArch64 opcodes. It also implements
  4797. several pseudo opcodes, including several synthetic load instructions.
  4798. 'LDR ='
  4799. ldr <register> , =<expression>
  4800. The constant expression will be placed into the nearest literal
  4801. pool (if it not already there) and a PC-relative LDR instruction
  4802. will be generated.
  4803. For more information on the AArch64 instruction set and assembly
  4804. language notation, see 'ARMv8 Instruction Set Overview' available at
  4805. <http://infocenter.arm.com>.
  4806. 
  4807. File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent
  4808. 9.1.7 Mapping Symbols
  4809. ---------------------
  4810. The AArch64 ELF specification requires that special symbols be inserted
  4811. into object files to mark certain features:
  4812. '$x'
  4813. At the start of a region of code containing AArch64 instructions.
  4814. '$d'
  4815. At the start of a region of data.
  4816. 
  4817. File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies
  4818. 9.2 Alpha Dependent Features
  4819. ============================
  4820. * Menu:
  4821. * Alpha Notes:: Notes
  4822. * Alpha Options:: Options
  4823. * Alpha Syntax:: Syntax
  4824. * Alpha Floating Point:: Floating Point
  4825. * Alpha Directives:: Alpha Machine Directives
  4826. * Alpha Opcodes:: Opcodes
  4827. 
  4828. File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent
  4829. 9.2.1 Notes
  4830. -----------
  4831. The documentation here is primarily for the ELF object format. 'as'
  4832. also supports the ECOFF and EVAX formats, but features specific to these
  4833. formats are not yet documented.
  4834. 
  4835. File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent
  4836. 9.2.2 Options
  4837. -------------
  4838. '-mCPU'
  4839. This option specifies the target processor. If an attempt is made
  4840. to assemble an instruction which will not execute on the target
  4841. processor, the assembler may either expand the instruction as a
  4842. macro or issue an error message. This option is equivalent to the
  4843. '.arch' directive.
  4844. The following processor names are recognized: '21064', '21064a',
  4845. '21066', '21068', '21164', '21164a', '21164pc', '21264', '21264a',
  4846. '21264b', 'ev4', 'ev5', 'lca45', 'ev5', 'ev56', 'pca56', 'ev6',
  4847. 'ev67', 'ev68'. The special name 'all' may be used to allow the
  4848. assembler to accept instructions valid for any Alpha processor.
  4849. In order to support existing practice in OSF/1 with respect to
  4850. '.arch', and existing practice within 'MILO' (the Linux ARC
  4851. bootloader), the numbered processor names (e.g. 21064) enable the
  4852. processor-specific PALcode instructions, while the "electro-vlasic"
  4853. names (e.g. 'ev4') do not.
  4854. '-mdebug'
  4855. '-no-mdebug'
  4856. Enables or disables the generation of '.mdebug' encapsulation for
  4857. stabs directives and procedure descriptors. The default is to
  4858. automatically enable '.mdebug' when the first stabs directive is
  4859. seen.
  4860. '-relax'
  4861. This option forces all relocations to be put into the object file,
  4862. instead of saving space and resolving some relocations at assembly
  4863. time. Note that this option does not propagate all symbol
  4864. arithmetic into the object file, because not all symbol arithmetic
  4865. can be represented. However, the option can still be useful in
  4866. specific applications.
  4867. '-replace'
  4868. '-noreplace'
  4869. Enables or disables the optimization of procedure calls, both at
  4870. assemblage and at link time. These options are only available for
  4871. VMS targets and '-replace' is the default. See section 1.4.1 of
  4872. the OpenVMS Linker Utility Manual.
  4873. '-g'
  4874. This option is used when the compiler generates debug information.
  4875. When 'gcc' is using 'mips-tfile' to generate debug information for
  4876. ECOFF, local labels must be passed through to the object file.
  4877. Otherwise this option has no effect.
  4878. '-GSIZE'
  4879. A local common symbol larger than SIZE is placed in '.bss', while
  4880. smaller symbols are placed in '.sbss'.
  4881. '-F'
  4882. '-32addr'
  4883. These options are ignored for backward compatibility.
  4884. 
  4885. File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent
  4886. 9.2.3 Syntax
  4887. ------------
  4888. The assembler syntax closely follow the Alpha Reference Manual;
  4889. assembler directives and general syntax closely follow the OSF/1 and
  4890. OpenVMS syntax, with a few differences for ELF.
  4891. * Menu:
  4892. * Alpha-Chars:: Special Characters
  4893. * Alpha-Regs:: Register Names
  4894. * Alpha-Relocs:: Relocations
  4895. 
  4896. File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax
  4897. 9.2.3.1 Special Characters
  4898. ..........................
  4899. '#' is the line comment character. Note that if '#' is the first
  4900. character on a line then it can also be a logical line number directive
  4901. (*note Comments::) or a preprocessor control command (*note
  4902. Preprocessing::).
  4903. ';' can be used instead of a newline to separate statements.
  4904. 
  4905. File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax
  4906. 9.2.3.2 Register Names
  4907. ......................
  4908. The 32 integer registers are referred to as '$N' or '$rN'. In addition,
  4909. registers 15, 28, 29, and 30 may be referred to by the symbols '$fp',
  4910. '$at', '$gp', and '$sp' respectively.
  4911. The 32 floating-point registers are referred to as '$fN'.
  4912. 
  4913. File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax
  4914. 9.2.3.3 Relocations
  4915. ...................
  4916. Some of these relocations are available for ECOFF, but mostly only for
  4917. ELF. They are modeled after the relocation format introduced in Digital
  4918. Unix 4.0, but there are additions.
  4919. The format is '!TAG' or '!TAG!NUMBER' where TAG is the name of the
  4920. relocation. In some cases NUMBER is used to relate specific
  4921. instructions.
  4922. The relocation is placed at the end of the instruction like so:
  4923. ldah $0,a($29) !gprelhigh
  4924. lda $0,a($0) !gprellow
  4925. ldq $1,b($29) !literal!100
  4926. ldl $2,0($1) !lituse_base!100
  4927. '!literal'
  4928. '!literal!N'
  4929. Used with an 'ldq' instruction to load the address of a symbol from
  4930. the GOT.
  4931. A sequence number N is optional, and if present is used to pair
  4932. 'lituse' relocations with this 'literal' relocation. The 'lituse'
  4933. relocations are used by the linker to optimize the code based on
  4934. the final location of the symbol.
  4935. Note that these optimizations are dependent on the data flow of the
  4936. program. Therefore, if _any_ 'lituse' is paired with a 'literal'
  4937. relocation, then _all_ uses of the register set by the 'literal'
  4938. instruction must also be marked with 'lituse' relocations. This is
  4939. because the original 'literal' instruction may be deleted or
  4940. transformed into another instruction.
  4941. Also note that there may be a one-to-many relationship between
  4942. 'literal' and 'lituse', but not a many-to-one. That is, if there
  4943. are two code paths that load up the same address and feed the value
  4944. to a single use, then the use may not use a 'lituse' relocation.
  4945. '!lituse_base!N'
  4946. Used with any memory format instruction (e.g. 'ldl') to indicate
  4947. that the literal is used for an address load. The offset field of
  4948. the instruction must be zero. During relaxation, the code may be
  4949. altered to use a gp-relative load.
  4950. '!lituse_jsr!N'
  4951. Used with a register branch format instruction (e.g. 'jsr') to
  4952. indicate that the literal is used for a call. During relaxation,
  4953. the code may be altered to use a direct branch (e.g. 'bsr').
  4954. '!lituse_jsrdirect!N'
  4955. Similar to 'lituse_jsr', but also that this call cannot be vectored
  4956. through a PLT entry. This is useful for functions with special
  4957. calling conventions which do not allow the normal call-clobbered
  4958. registers to be clobbered.
  4959. '!lituse_bytoff!N'
  4960. Used with a byte mask instruction (e.g. 'extbl') to indicate that
  4961. only the low 3 bits of the address are relevant. During
  4962. relaxation, the code may be altered to use an immediate instead of
  4963. a register shift.
  4964. '!lituse_addr!N'
  4965. Used with any other instruction to indicate that the original
  4966. address is in fact used, and the original 'ldq' instruction may not
  4967. be altered or deleted. This is useful in conjunction with
  4968. 'lituse_jsr' to test whether a weak symbol is defined.
  4969. ldq $27,foo($29) !literal!1
  4970. beq $27,is_undef !lituse_addr!1
  4971. jsr $26,($27),foo !lituse_jsr!1
  4972. '!lituse_tlsgd!N'
  4973. Used with a register branch format instruction to indicate that the
  4974. literal is the call to '__tls_get_addr' used to compute the address
  4975. of the thread-local storage variable whose descriptor was loaded
  4976. with '!tlsgd!N'.
  4977. '!lituse_tlsldm!N'
  4978. Used with a register branch format instruction to indicate that the
  4979. literal is the call to '__tls_get_addr' used to compute the address
  4980. of the base of the thread-local storage block for the current
  4981. module. The descriptor for the module must have been loaded with
  4982. '!tlsldm!N'.
  4983. '!gpdisp!N'
  4984. Used with 'ldah' and 'lda' to load the GP from the current address,
  4985. a-la the 'ldgp' macro. The source register for the 'ldah'
  4986. instruction must contain the address of the 'ldah' instruction.
  4987. There must be exactly one 'lda' instruction paired with the 'ldah'
  4988. instruction, though it may appear anywhere in the instruction
  4989. stream. The immediate operands must be zero.
  4990. bsr $26,foo
  4991. ldah $29,0($26) !gpdisp!1
  4992. lda $29,0($29) !gpdisp!1
  4993. '!gprelhigh'
  4994. Used with an 'ldah' instruction to add the high 16 bits of a 32-bit
  4995. displacement from the GP.
  4996. '!gprellow'
  4997. Used with any memory format instruction to add the low 16 bits of a
  4998. 32-bit displacement from the GP.
  4999. '!gprel'
  5000. Used with any memory format instruction to add a 16-bit
  5001. displacement from the GP.
  5002. '!samegp'
  5003. Used with any branch format instruction to skip the GP load at the
  5004. target address. The referenced symbol must have the same GP as the
  5005. source object file, and it must be declared to either not use '$27'
  5006. or perform a standard GP load in the first two instructions via the
  5007. '.prologue' directive.
  5008. '!tlsgd'
  5009. '!tlsgd!N'
  5010. Used with an 'lda' instruction to load the address of a TLS
  5011. descriptor for a symbol in the GOT.
  5012. The sequence number N is optional, and if present it used to pair
  5013. the descriptor load with both the 'literal' loading the address of
  5014. the '__tls_get_addr' function and the 'lituse_tlsgd' marking the
  5015. call to that function.
  5016. For proper relaxation, both the 'tlsgd', 'literal' and 'lituse'
  5017. relocations must be in the same extended basic block. That is, the
  5018. relocation with the lowest address must be executed first at
  5019. runtime.
  5020. '!tlsldm'
  5021. '!tlsldm!N'
  5022. Used with an 'lda' instruction to load the address of a TLS
  5023. descriptor for the current module in the GOT.
  5024. Similar in other respects to 'tlsgd'.
  5025. '!gotdtprel'
  5026. Used with an 'ldq' instruction to load the offset of the TLS symbol
  5027. within its module's thread-local storage block. Also known as the
  5028. dynamic thread pointer offset or dtp-relative offset.
  5029. '!dtprelhi'
  5030. '!dtprello'
  5031. '!dtprel'
  5032. Like 'gprel' relocations except they compute dtp-relative offsets.
  5033. '!gottprel'
  5034. Used with an 'ldq' instruction to load the offset of the TLS symbol
  5035. from the thread pointer. Also known as the tp-relative offset.
  5036. '!tprelhi'
  5037. '!tprello'
  5038. '!tprel'
  5039. Like 'gprel' relocations except they compute tp-relative offsets.
  5040. 
  5041. File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent
  5042. 9.2.4 Floating Point
  5043. --------------------
  5044. The Alpha family uses both IEEE and VAX floating-point numbers.
  5045. 
  5046. File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent
  5047. 9.2.5 Alpha Assembler Directives
  5048. --------------------------------
  5049. 'as' for the Alpha supports many additional directives for compatibility
  5050. with the native assembler. This section describes them only briefly.
  5051. These are the additional directives in 'as' for the Alpha:
  5052. '.arch CPU'
  5053. Specifies the target processor. This is equivalent to the '-mCPU'
  5054. command-line option. *Note Options: Alpha Options, for a list of
  5055. values for CPU.
  5056. '.ent FUNCTION[, N]'
  5057. Mark the beginning of FUNCTION. An optional number may follow for
  5058. compatibility with the OSF/1 assembler, but is ignored. When
  5059. generating '.mdebug' information, this will create a procedure
  5060. descriptor for the function. In ELF, it will mark the symbol as a
  5061. function a-la the generic '.type' directive.
  5062. '.end FUNCTION'
  5063. Mark the end of FUNCTION. In ELF, it will set the size of the
  5064. symbol a-la the generic '.size' directive.
  5065. '.mask MASK, OFFSET'
  5066. Indicate which of the integer registers are saved in the current
  5067. function's stack frame. MASK is interpreted a bit mask in which
  5068. bit N set indicates that register N is saved. The registers are
  5069. saved in a block located OFFSET bytes from the "canonical frame
  5070. address" (CFA) which is the value of the stack pointer on entry to
  5071. the function. The registers are saved sequentially, except that
  5072. the return address register (normally '$26') is saved first.
  5073. This and the other directives that describe the stack frame are
  5074. currently only used when generating '.mdebug' information. They
  5075. may in the future be used to generate DWARF2 '.debug_frame' unwind
  5076. information for hand written assembly.
  5077. '.fmask MASK, OFFSET'
  5078. Indicate which of the floating-point registers are saved in the
  5079. current stack frame. The MASK and OFFSET parameters are
  5080. interpreted as with '.mask'.
  5081. '.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
  5082. Describes the shape of the stack frame. The frame pointer in use
  5083. is FRAMEREG; normally this is either '$fp' or '$sp'. The frame
  5084. pointer is FRAMEOFFSET bytes below the CFA. The return address is
  5085. initially located in RETREG until it is saved as indicated in
  5086. '.mask'. For compatibility with OSF/1 an optional ARGOFFSET
  5087. parameter is accepted and ignored. It is believed to indicate the
  5088. offset from the CFA to the saved argument registers.
  5089. '.prologue N'
  5090. Indicate that the stack frame is set up and all registers have been
  5091. spilled. The argument N indicates whether and how the function
  5092. uses the incoming "procedure vector" (the address of the called
  5093. function) in '$27'. 0 indicates that '$27' is not used; 1
  5094. indicates that the first two instructions of the function use '$27'
  5095. to perform a load of the GP register; 2 indicates that '$27' is
  5096. used in some non-standard way and so the linker cannot elide the
  5097. load of the procedure vector during relaxation.
  5098. '.usepv FUNCTION, WHICH'
  5099. Used to indicate the use of the '$27' register, similar to
  5100. '.prologue', but without the other semantics of needing to be
  5101. inside an open '.ent'/'.end' block.
  5102. The WHICH argument should be either 'no', indicating that '$27' is
  5103. not used, or 'std', indicating that the first two instructions of
  5104. the function perform a GP load.
  5105. One might use this directive instead of '.prologue' if you are also
  5106. using dwarf2 CFI directives.
  5107. '.gprel32 EXPRESSION'
  5108. Computes the difference between the address in EXPRESSION and the
  5109. GP for the current object file, and stores it in 4 bytes. In
  5110. addition to being smaller than a full 8 byte address, this also
  5111. does not require a dynamic relocation when used in a shared
  5112. library.
  5113. '.t_floating EXPRESSION'
  5114. Stores EXPRESSION as an IEEE double precision value.
  5115. '.s_floating EXPRESSION'
  5116. Stores EXPRESSION as an IEEE single precision value.
  5117. '.f_floating EXPRESSION'
  5118. Stores EXPRESSION as a VAX F format value.
  5119. '.g_floating EXPRESSION'
  5120. Stores EXPRESSION as a VAX G format value.
  5121. '.d_floating EXPRESSION'
  5122. Stores EXPRESSION as a VAX D format value.
  5123. '.set FEATURE'
  5124. Enables or disables various assembler features. Using the positive
  5125. name of the feature enables while using 'noFEATURE' disables.
  5126. 'at'
  5127. Indicates that macro expansions may clobber the "assembler
  5128. temporary" ('$at' or '$28') register. Some macros may not be
  5129. expanded without this and will generate an error message if
  5130. 'noat' is in effect. When 'at' is in effect, a warning will
  5131. be generated if '$at' is used by the programmer.
  5132. 'macro'
  5133. Enables the expansion of macro instructions. Note that
  5134. variants of real instructions, such as 'br label' vs 'br
  5135. $31,label' are considered alternate forms and not macros.
  5136. 'move'
  5137. 'reorder'
  5138. 'volatile'
  5139. These control whether and how the assembler may re-order
  5140. instructions. Accepted for compatibility with the OSF/1
  5141. assembler, but 'as' does not do instruction scheduling, so
  5142. these features are ignored.
  5143. The following directives are recognized for compatibility with the
  5144. OSF/1 assembler but are ignored.
  5145. .proc .aproc
  5146. .reguse .livereg
  5147. .option .aent
  5148. .ugen .eflag
  5149. .alias .noalias
  5150. 
  5151. File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent
  5152. 9.2.6 Opcodes
  5153. -------------
  5154. For detailed information on the Alpha machine instruction set, see the
  5155. Alpha Architecture Handbook
  5156. (ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
  5157. 
  5158. File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies
  5159. 9.3 ARC Dependent Features
  5160. ==========================
  5161. * Menu:
  5162. * ARC Options:: Options
  5163. * ARC Syntax:: Syntax
  5164. * ARC Directives:: ARC Machine Directives
  5165. * ARC Modifiers:: ARC Assembler Modifiers
  5166. * ARC Symbols:: ARC Pre-defined Symbols
  5167. * ARC Opcodes:: Opcodes
  5168. 
  5169. File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent
  5170. 9.3.1 Options
  5171. -------------
  5172. The following options control the type of CPU for which code is
  5173. assembled, and generic constraints on the code generated:
  5174. '-mcpu=CPU'
  5175. Set architecture type and register usage for CPU. There are also
  5176. shortcut alias options available for backward compatibility and
  5177. convenience. Supported values for CPU are
  5178. 'arc600'
  5179. Assemble for ARC 600. Aliases: '-mA6', '-mARC600'.
  5180. 'arc600_norm'
  5181. Assemble for ARC 600 with norm instructions.
  5182. 'arc600_mul64'
  5183. Assemble for ARC 600 with mul64 instructions.
  5184. 'arc600_mul32x16'
  5185. Assemble for ARC 600 with mul32x16 instructions.
  5186. 'arc601'
  5187. Assemble for ARC 601. Alias: '-mARC601'.
  5188. 'arc601_norm'
  5189. Assemble for ARC 601 with norm instructions.
  5190. 'arc601_mul64'
  5191. Assemble for ARC 601 with mul64 instructions.
  5192. 'arc601_mul32x16'
  5193. Assemble for ARC 601 with mul32x16 instructions.
  5194. 'arc700'
  5195. Assemble for ARC 700. Aliases: '-mA7', '-mARC700'.
  5196. 'arcem'
  5197. Assemble for ARC EM. Aliases: '-mEM'
  5198. 'em'
  5199. Assemble for ARC EM, identical as arcem variant.
  5200. 'em4'
  5201. Assemble for ARC EM with code-density instructions.
  5202. 'em4_dmips'
  5203. Assemble for ARC EM with code-density instructions.
  5204. 'em4_fpus'
  5205. Assemble for ARC EM with code-density instructions.
  5206. 'em4_fpuda'
  5207. Assemble for ARC EM with code-density, and double-precision
  5208. assist instructions.
  5209. 'quarkse_em'
  5210. Assemble for QuarkSE-EM cpu.
  5211. 'archs'
  5212. Assemble for ARC HS. Aliases: '-mHS', '-mav2hs'.
  5213. 'hs'
  5214. Assemble for ARC HS.
  5215. 'hs34'
  5216. Assemble for ARC HS34.
  5217. 'hs38'
  5218. Assemble for ARC HS38.
  5219. 'hs38_linux'
  5220. Assemble for ARC HS38 with floating point support on.
  5221. 'nps400'
  5222. Assemble for ARC 700 with NPS-400 extended instructions.
  5223. Note: the '.cpu' directive (*note ARC Directives::) can to be used
  5224. to select a core variant from within assembly code.
  5225. '-EB'
  5226. This option specifies that the output generated by the assembler
  5227. should be marked as being encoded for a big-endian processor.
  5228. '-EL'
  5229. This option specifies that the output generated by the assembler
  5230. should be marked as being encoded for a little-endian processor -
  5231. this is the default.
  5232. '-mcode-density'
  5233. This option turns on Code Density instructions. Only valid for ARC
  5234. EM processors.
  5235. '-mrelax'
  5236. Enable support for assembly-time relaxation. The assembler will
  5237. replace a longer version of an instruction with a shorter one,
  5238. whenever it is possible.
  5239. '-mnps400'
  5240. Enable support for NPS-400 extended instructions.
  5241. '-mspfp'
  5242. Enable support for single-precision floating point instructions.
  5243. '-mdpfp'
  5244. Enable support for double-precision floating point instructions.
  5245. '-mfpuda'
  5246. Enable support for double-precision assist floating point
  5247. instructions. Only valid for ARC EM processors.
  5248. 
  5249. File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent
  5250. 9.3.2 Syntax
  5251. ------------
  5252. * Menu:
  5253. * ARC-Chars:: Special Characters
  5254. * ARC-Regs:: Register Names
  5255. 
  5256. File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax
  5257. 9.3.2.1 Special Characters
  5258. ..........................
  5259. '%'
  5260. A register name can optionally be prefixed by a '%' character. So
  5261. register '%r0' is equivalent to 'r0' in the assembly code.
  5262. '#'
  5263. The presence of a '#' character within a line (but not at the start
  5264. of a line) indicates the start of a comment that extends to the end
  5265. of the current line.
  5266. _Note:_ if a line starts with a '#' character then it can also be a
  5267. logical line number directive (*note Comments::) or a preprocessor
  5268. control command (*note Preprocessing::).
  5269. '@'
  5270. Prefixing an operand with an '@' specifies that the operand is a
  5271. symbol and not a register. This is how the assembler disambiguates
  5272. the use of an ARC register name as a symbol. So the instruction
  5273. mov r0, @r0
  5274. moves the address of symbol 'r0' into register 'r0'.
  5275. '`'
  5276. The '`' (backtick) character is used to separate statements on a
  5277. single line.
  5278. '-'
  5279. Used as a separator to obtain a sequence of commands from a C
  5280. preprocessor macro.
  5281. 
  5282. File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax
  5283. 9.3.2.2 Register Names
  5284. ......................
  5285. The ARC assembler uses the following register names for its core
  5286. registers:
  5287. 'r0-r31'
  5288. The core general registers. Registers 'r26' through 'r31' have
  5289. special functions, and are usually referred to by those synonyms.
  5290. 'gp'
  5291. The global pointer and a synonym for 'r26'.
  5292. 'fp'
  5293. The frame pointer and a synonym for 'r27'.
  5294. 'sp'
  5295. The stack pointer and a synonym for 'r28'.
  5296. 'ilink1'
  5297. For ARC 600 and ARC 700, the level 1 interrupt link register and a
  5298. synonym for 'r29'. Not supported for ARCv2.
  5299. 'ilink'
  5300. For ARCv2, the interrupt link register and a synonym for 'r29'.
  5301. Not supported for ARC 600 and ARC 700.
  5302. 'ilink2'
  5303. For ARC 600 and ARC 700, the level 2 interrupt link register and a
  5304. synonym for 'r30'. Not supported for ARC v2.
  5305. 'blink'
  5306. The link register and a synonym for 'r31'.
  5307. 'r32-r59'
  5308. The extension core registers.
  5309. 'lp_count'
  5310. The loop count register.
  5311. 'pcl'
  5312. The word aligned program counter.
  5313. In addition the ARC processor has a large number of _auxiliary
  5314. registers_. The precise set depends on the extensions being supported,
  5315. but the following baseline set are always defined:
  5316. 'identity'
  5317. Processor Identification register. Auxiliary register address 0x4.
  5318. 'pc'
  5319. Program Counter. Auxiliary register address 0x6.
  5320. 'status32'
  5321. Status register. Auxiliary register address 0x0a.
  5322. 'bta'
  5323. Branch Target Address. Auxiliary register address 0x412.
  5324. 'ecr'
  5325. Exception Cause Register. Auxiliary register address 0x403.
  5326. 'int_vector_base'
  5327. Interrupt Vector Base address. Auxiliary register address 0x25.
  5328. 'status32_p0'
  5329. Stored STATUS32 register on entry to level P0 interrupts.
  5330. Auxiliary register address 0xb.
  5331. 'aux_user_sp'
  5332. Saved User Stack Pointer. Auxiliary register address 0xd.
  5333. 'eret'
  5334. Exception Return Address. Auxiliary register address 0x400.
  5335. 'erbta'
  5336. BTA saved on exception entry. Auxiliary register address 0x401.
  5337. 'erstatus'
  5338. STATUS32 saved on exception. Auxiliary register address 0x402.
  5339. 'bcr_ver'
  5340. Build Configuration Registers Version. Auxiliary register address
  5341. 0x60.
  5342. 'bta_link_build'
  5343. Build configuration for: BTA Registers. Auxiliary register address
  5344. 0x63.
  5345. 'vecbase_ac_build'
  5346. Build configuration for: Interrupts. Auxiliary register address
  5347. 0x68.
  5348. 'rf_build'
  5349. Build configuration for: Core Registers. Auxiliary register
  5350. address 0x6e.
  5351. 'dccm_build'
  5352. DCCM RAM Configuration Register. Auxiliary register address 0xc1.
  5353. Additional auxiliary register names are defined according to the
  5354. processor architecture version and extensions selected by the options.
  5355. 
  5356. File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent
  5357. 9.3.3 ARC Machine Directives
  5358. ----------------------------
  5359. The ARC version of 'as' supports the following additional machine
  5360. directives:
  5361. '.lcomm SYMBOL, LENGTH[, ALIGNMENT]'
  5362. Reserve LENGTH (an absolute expression) bytes for a local common
  5363. denoted by SYMBOL. The section and value of SYMBOL are those of
  5364. the new local common. The addresses are allocated in the bss
  5365. section, so that at run-time the bytes start off zeroed. Since
  5366. SYMBOL is not declared global, it is normally not visible to 'ld'.
  5367. The optional third parameter, ALIGNMENT, specifies the desired
  5368. alignment of the symbol in the bss section, specified as a byte
  5369. boundary (for example, an alignment of 16 means that the least
  5370. significant 4 bits of the address should be zero). The alignment
  5371. must be an absolute expression, and it must be a power of two. If
  5372. no alignment is specified, as will set the alignment to the largest
  5373. power of two less than or equal to the size of the symbol, up to a
  5374. maximum of 16.
  5375. '.lcommon SYMBOL, LENGTH[, ALIGNMENT]'
  5376. The same as 'lcomm' directive.
  5377. '.cpu CPU'
  5378. The '.cpu' directive must be followed by the desired core version.
  5379. Permitted values for CPU are:
  5380. 'ARC600'
  5381. Assemble for the ARC600 instruction set.
  5382. 'arc600_norm'
  5383. Assemble for ARC 600 with norm instructions.
  5384. 'arc600_mul64'
  5385. Assemble for ARC 600 with mul64 instructions.
  5386. 'arc600_mul32x16'
  5387. Assemble for ARC 600 with mul32x16 instructions.
  5388. 'arc601'
  5389. Assemble for ARC 601 instruction set.
  5390. 'arc601_norm'
  5391. Assemble for ARC 601 with norm instructions.
  5392. 'arc601_mul64'
  5393. Assemble for ARC 601 with mul64 instructions.
  5394. 'arc601_mul32x16'
  5395. Assemble for ARC 601 with mul32x16 instructions.
  5396. 'ARC700'
  5397. Assemble for the ARC700 instruction set.
  5398. 'NPS400'
  5399. Assemble for the NPS400 instruction set.
  5400. 'EM'
  5401. Assemble for the ARC EM instruction set.
  5402. 'arcem'
  5403. Assemble for ARC EM instruction set
  5404. 'em4'
  5405. Assemble for ARC EM with code-density instructions.
  5406. 'em4_dmips'
  5407. Assemble for ARC EM with code-density instructions.
  5408. 'em4_fpus'
  5409. Assemble for ARC EM with code-density instructions.
  5410. 'em4_fpuda'
  5411. Assemble for ARC EM with code-density, and double-precision
  5412. assist instructions.
  5413. 'quarkse_em'
  5414. Assemble for QuarkSE-EM instruction set.
  5415. 'HS'
  5416. Assemble for the ARC HS instruction set.
  5417. 'archs'
  5418. Assemble for ARC HS instruction set.
  5419. 'hs'
  5420. Assemble for ARC HS instruction set.
  5421. 'hs34'
  5422. Assemble for ARC HS34 instruction set.
  5423. 'hs38'
  5424. Assemble for ARC HS38 instruction set.
  5425. 'hs38_linux'
  5426. Assemble for ARC HS38 with floating point support on.
  5427. Note: the '.cpu' directive overrides the command line option
  5428. '-mcpu=CPU'; a warning is emitted when the version is not
  5429. consistent between the two.
  5430. '.extAuxRegister NAME, ADDR, MODE'
  5431. Auxiliary registers can be defined in the assembler source code by
  5432. using this directive. The first parameter, NAME, is the name of
  5433. the new auxiliary register. The second parameter, ADDR, is address
  5434. the of the auxiliary register. The third parameter, MODE,
  5435. specifies whether the register is readable and/or writable and is
  5436. one of:
  5437. 'r'
  5438. Read only;
  5439. 'w'
  5440. Write only;
  5441. 'r|w'
  5442. Read and write.
  5443. For example:
  5444. .extAuxRegister mulhi, 0x12, w
  5445. specifies a write only extension auxiliary register, MULHI at
  5446. address 0x12.
  5447. '.extCondCode SUFFIX, VAL'
  5448. ARC supports extensible condition codes. This directive defines a
  5449. new condition code, to be known by the suffix, SUFFIX and will
  5450. depend on the value, VAL in the condition code.
  5451. For example:
  5452. .extCondCode is_busy,0x14
  5453. add.is_busy r1,r2,r3
  5454. will only execute the 'add' instruction if the condition code value
  5455. is 0x14.
  5456. '.extCoreRegister NAME, REGNUM, MODE, SHORTCUT'
  5457. Specifies an extension core register named NAME as a synonym for
  5458. the register numbered REGNUM. The register number must be between
  5459. 32 and 59. The third argument, MODE, indicates whether the
  5460. register is readable and/or writable and is one of:
  5461. 'r'
  5462. Read only;
  5463. 'w'
  5464. Write only;
  5465. 'r|w'
  5466. Read and write.
  5467. The final parameter, SHORTCUT indicates whether the register has a
  5468. short cut in the pipeline. The valid values are:
  5469. 'can_shortcut'
  5470. The register has a short cut in the pipeline;
  5471. 'cannot_shortcut'
  5472. The register does not have a short cut in the pipeline.
  5473. For example:
  5474. .extCoreRegister mlo, 57, r , can_shortcut
  5475. defines a read only extension core register, 'mlo', which is
  5476. register 57, and can short cut the pipeline.
  5477. '.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS'
  5478. ARC allows the user to specify extension instructions. These
  5479. extension instructions are not macros; the assembler creates
  5480. encodings for use of these instructions according to the
  5481. specification by the user.
  5482. The first argument, NAME, gives the name of the instruction.
  5483. The second argument, OPCODE, is the opcode to be used (bits 31:27
  5484. in the encoding).
  5485. The third argument, SUBOPCODE, is the sub-opcode to be used, but
  5486. the correct value also depends on the fifth argument, SYNTAXCLASS
  5487. The fourth argument, SUFFIXCLASS, determines the kinds of suffixes
  5488. to be allowed. Valid values are:
  5489. 'SUFFIX_NONE'
  5490. No suffixes are permitted;
  5491. 'SUFFIX_COND'
  5492. Conditional suffixes are permitted;
  5493. 'SUFFIX_FLAG'
  5494. Flag setting suffixes are permitted.
  5495. 'SUFFIX_COND|SUFFIX_FLAG'
  5496. Both conditional and flag setting suffices are permitted.
  5497. The fifth and final argument, SYNTAXCLASS, determines the syntax
  5498. class for the instruction. It can have the following values:
  5499. 'SYNTAX_2OP'
  5500. Two Operand Instruction;
  5501. 'SYNTAX_3OP'
  5502. Three Operand Instruction.
  5503. 'SYNTAX_1OP'
  5504. One Operand Instruction.
  5505. 'SYNTAX_NOP'
  5506. No Operand Instruction.
  5507. The syntax class may be followed by '|' and one of the following
  5508. modifiers.
  5509. 'OP1_MUST_BE_IMM'
  5510. Modifies syntax class 'SYNTAX_3OP', specifying that the first
  5511. operand of a three-operand instruction must be an immediate
  5512. (i.e., the result is discarded). This is usually used to set
  5513. the flags using specific instructions and not retain results.
  5514. 'OP1_IMM_IMPLIED'
  5515. Modifies syntax class 'SYNTAX_20P', specifying that there is
  5516. an implied immediate destination operand which does not appear
  5517. in the syntax.
  5518. For example, if the source code contains an instruction like:
  5519. inst r1,r2
  5520. the first argument is an implied immediate (that is, the
  5521. result is discarded). This is the same as though the source
  5522. code were: inst 0,r1,r2.
  5523. For example, defining a 64-bit multiplier with immediate operands:
  5524. .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
  5525. SYNTAX_3OP|OP1_MUST_BE_IMM
  5526. which specifies an extension instruction named 'mp64' with 3
  5527. operands. It sets the flags and can be used with a condition code,
  5528. for which the first operand is an immediate, i.e. equivalent to
  5529. discarding the result of the operation.
  5530. A two operands instruction variant would be:
  5531. .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
  5532. SYNTAX_2OP|OP1_IMM_IMPLIED
  5533. which describes a two operand instruction with an implicit first
  5534. immediate operand. The result of this operation would be
  5535. discarded.
  5536. 
  5537. File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent
  5538. 9.3.4 ARC Assembler Modifiers
  5539. -----------------------------
  5540. The following additional assembler modifiers have been added for
  5541. position-independent code. These modifiers are available only with the
  5542. ARC 700 and above processors and generate relocation entries, which are
  5543. interpreted by the linker as follows:
  5544. '@pcl(SYMBOL)'
  5545. Relative distance of SYMBOL's from the current program counter
  5546. location.
  5547. '@gotpc(SYMBOL)'
  5548. Relative distance of SYMBOL's Global Offset Table entry from the
  5549. current program counter location.
  5550. '@gotoff(SYMBOL)'
  5551. Distance of SYMBOL from the base of the Global Offset Table.
  5552. '@plt(SYMBOL)'
  5553. Distance of SYMBOL's Procedure Linkage Table entry from the current
  5554. program counter. This is valid only with branch and link
  5555. instructions and PC-relative calls.
  5556. '@sda(SYMBOL)'
  5557. Relative distance of SYMBOL from the base of the Small Data
  5558. Pointer.
  5559. 
  5560. File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent
  5561. 9.3.5 ARC Pre-defined Symbols
  5562. -----------------------------
  5563. The following assembler symbols will prove useful when developing
  5564. position-independent code. These symbols are available only with the
  5565. ARC 700 and above processors.
  5566. '__GLOBAL_OFFSET_TABLE__'
  5567. Symbol referring to the base of the Global Offset Table.
  5568. '__DYNAMIC__'
  5569. An alias for the Global Offset Table 'Base__GLOBAL_OFFSET_TABLE__'.
  5570. It can be used only with '@gotpc' modifiers.
  5571. 
  5572. File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent
  5573. 9.3.6 Opcodes
  5574. -------------
  5575. For information on the ARC instruction set, see 'ARC Programmers
  5576. Reference Manual', available where you download the processor IP
  5577. library.
  5578. 
  5579. File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies
  5580. 9.4 ARM Dependent Features
  5581. ==========================
  5582. * Menu:
  5583. * ARM Options:: Options
  5584. * ARM Syntax:: Syntax
  5585. * ARM Floating Point:: Floating Point
  5586. * ARM Directives:: ARM Machine Directives
  5587. * ARM Opcodes:: Opcodes
  5588. * ARM Mapping Symbols:: Mapping Symbols
  5589. * ARM Unwinding Tutorial:: Unwinding
  5590. 
  5591. File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent
  5592. 9.4.1 Options
  5593. -------------
  5594. '-mcpu=PROCESSOR[+EXTENSION...]'
  5595. This option specifies the target processor. The assembler will
  5596. issue an error message if an attempt is made to assemble an
  5597. instruction which will not execute on the target processor. The
  5598. following processor names are recognized: 'arm1', 'arm2', 'arm250',
  5599. 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7',
  5600. 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700',
  5601. 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t',
  5602. 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi',
  5603. 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1',
  5604. 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920',
  5605. 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526
  5606. processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e',
  5607. 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0',
  5608. 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi',
  5609. 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e',
  5610. 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te'
  5611. (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor),
  5612. 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE
  5613. processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s',
  5614. 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore',
  5615. 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9',
  5616. 'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35',
  5617. 'cortex-a53', 'cortex-a57', 'cortex-a72', 'cortex-a73',
  5618. 'cortex-r4', 'cortex-r4f', 'cortex-r5', 'cortex-r7', 'cortex-r8',
  5619. 'cortex-m33', 'cortex-m23', 'cortex-m7', 'cortex-m4', 'cortex-m3',
  5620. 'cortex-m1', 'cortex-m0', 'cortex-m0plus', 'exynos-m1',
  5621. 'marvell-pj4', 'marvell-whitney', 'falkor', 'qdf24xx', 'xgene1',
  5622. 'xgene2', 'ep9312' (ARM920 with Cirrus Maverick coprocessor),
  5623. 'i80200' (Intel XScale processor) 'iwmmxt' (Intel(r) XScale
  5624. processor with Wireless MMX(tm) technology coprocessor) and
  5625. 'xscale'. The special name 'all' may be used to allow the
  5626. assembler to accept instructions valid for any ARM processor.
  5627. In addition to the basic instruction set, the assembler can be told
  5628. to accept various extension mnemonics that extend the processor
  5629. using the co-processor instruction space. For example,
  5630. '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'.
  5631. Multiple extensions may be specified, separated by a '+'. The
  5632. extensions should be specified in ascending alphabetical order.
  5633. Some extensions may be restricted to particular architectures; this
  5634. is documented in the list of extensions below.
  5635. Extension mnemonics may also be removed from those the assembler
  5636. accepts. This is done be prepending 'no' to the option that adds
  5637. the extension. Extensions that are removed should be listed after
  5638. all extensions which have been added, again in ascending
  5639. alphabetical order. For example, '-mcpu=ep9312+nomaverick' is
  5640. equivalent to specifying '-mcpu=arm920'.
  5641. The following extensions are currently supported: 'crc' 'crypto'
  5642. (Cryptography Extensions for v8-A architecture, implies 'fp+simd'),
  5643. 'dotprod' (Dot Product Extensions for v8.2-A architecture, implies
  5644. 'fp+simd'), 'fp' (Floating Point Extensions for v8-A architecture),
  5645. 'idiv' (Integer Divide Extensions for v7-A and v7-R architectures),
  5646. 'iwmmxt', 'iwmmxt2', 'xscale', 'maverick', 'mp' (Multiprocessing
  5647. Extensions for v7-A and v7-R architectures), 'os' (Operating System
  5648. for v6M architecture), 'sec' (Security Extensions for v6K and v7-A
  5649. architectures), 'simd' (Advanced SIMD Extensions for v8-A
  5650. architecture, implies 'fp'), 'virt' (Virtualization Extensions for
  5651. v7-A architecture, implies 'idiv'), 'pan' (Priviliged Access Never
  5652. Extensions for v8-A architecture), 'ras' (Reliability, Availability
  5653. and Serviceability extensions for v8-A architecture), 'rdma'
  5654. (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
  5655. 'simd') and 'xscale'.
  5656. '-march=ARCHITECTURE[+EXTENSION...]'
  5657. This option specifies the target architecture. The assembler will
  5658. issue an error message if an attempt is made to assemble an
  5659. instruction which will not execute on the target architecture. The
  5660. following architecture names are recognized: 'armv1', 'armv2',
  5661. 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm',
  5662. 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te',
  5663. 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz',
  5664. 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r',
  5665. 'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a',
  5666. 'armv8.3-a', 'iwmmxt' 'iwmmxt2' and 'xscale'. If both '-mcpu' and
  5667. '-march' are specified, the assembler will use the setting for
  5668. '-mcpu'.
  5669. The architecture option can be extended with the same instruction
  5670. set extension options as the '-mcpu' option.
  5671. '-mfpu=FLOATING-POINT-FORMAT'
  5672. This option specifies the floating point format to assemble for.
  5673. The assembler will issue an error message if an attempt is made to
  5674. assemble an instruction which will not execute on the target
  5675. floating point unit. The following format options are recognized:
  5676. 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11',
  5677. 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0',
  5678. 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16',
  5679. 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16',
  5680. 'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t',
  5681. 'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv4',
  5682. 'neon-fp-armv8', 'crypto-neon-fp-armv8', 'neon-fp-armv8.1' and
  5683. 'crypto-neon-fp-armv8.1'.
  5684. In addition to determining which instructions are assembled, this
  5685. option also affects the way in which the '.double' assembler
  5686. directive behaves when assembling little-endian code.
  5687. The default is dependent on the processor selected. For
  5688. Architecture 5 or later, the default is to assembler for VFP
  5689. instructions; for earlier architectures the default is to assemble
  5690. for FPA instructions.
  5691. '-mthumb'
  5692. This option specifies that the assembler should start assembling
  5693. Thumb instructions; that is, it should behave as though the file
  5694. starts with a '.code 16' directive.
  5695. '-mthumb-interwork'
  5696. This option specifies that the output generated by the assembler
  5697. should be marked as supporting interworking.
  5698. '-mimplicit-it=never'
  5699. '-mimplicit-it=always'
  5700. '-mimplicit-it=arm'
  5701. '-mimplicit-it=thumb'
  5702. The '-mimplicit-it' option controls the behavior of the assembler
  5703. when conditional instructions are not enclosed in IT blocks. There
  5704. are four possible behaviors. If 'never' is specified, such
  5705. constructs cause a warning in ARM code and an error in Thumb-2
  5706. code. If 'always' is specified, such constructs are accepted in
  5707. both ARM and Thumb-2 code, where the IT instruction is added
  5708. implicitly. If 'arm' is specified, such constructs are accepted in
  5709. ARM code and cause an error in Thumb-2 code. If 'thumb' is
  5710. specified, such constructs cause a warning in ARM code and are
  5711. accepted in Thumb-2 code. If you omit this option, the behavior is
  5712. equivalent to '-mimplicit-it=arm'.
  5713. '-mapcs-26'
  5714. '-mapcs-32'
  5715. These options specify that the output generated by the assembler
  5716. should be marked as supporting the indicated version of the Arm
  5717. Procedure. Calling Standard.
  5718. '-matpcs'
  5719. This option specifies that the output generated by the assembler
  5720. should be marked as supporting the Arm/Thumb Procedure Calling
  5721. Standard. If enabled this option will cause the assembler to
  5722. create an empty debugging section in the object file called
  5723. .arm.atpcs. Debuggers can use this to determine the ABI being used
  5724. by.
  5725. '-mapcs-float'
  5726. This indicates the floating point variant of the APCS should be
  5727. used. In this variant floating point arguments are passed in FP
  5728. registers rather than integer registers.
  5729. '-mapcs-reentrant'
  5730. This indicates that the reentrant variant of the APCS should be
  5731. used. This variant supports position independent code.
  5732. '-mfloat-abi=ABI'
  5733. This option specifies that the output generated by the assembler
  5734. should be marked as using specified floating point ABI. The
  5735. following values are recognized: 'soft', 'softfp' and 'hard'.
  5736. '-meabi=VER'
  5737. This option specifies which EABI version the produced object files
  5738. should conform to. The following values are recognized: 'gnu', '4'
  5739. and '5'.
  5740. '-EB'
  5741. This option specifies that the output generated by the assembler
  5742. should be marked as being encoded for a big-endian processor.
  5743. Note: If a program is being built for a system with big-endian data
  5744. and little-endian instructions then it should be assembled with the
  5745. '-EB' option, (all of it, code and data) and then linked with the
  5746. '--be8' option. This will reverse the endianness of the
  5747. instructions back to little-endian, but leave the data as
  5748. big-endian.
  5749. '-EL'
  5750. This option specifies that the output generated by the assembler
  5751. should be marked as being encoded for a little-endian processor.
  5752. '-k'
  5753. This option specifies that the output of the assembler should be
  5754. marked as position-independent code (PIC).
  5755. '--fix-v4bx'
  5756. Allow 'BX' instructions in ARMv4 code. This is intended for use
  5757. with the linker option of the same name.
  5758. '-mwarn-deprecated'
  5759. '-mno-warn-deprecated'
  5760. Enable or disable warnings about using deprecated options or
  5761. features. The default is to warn.
  5762. '-mccs'
  5763. Turns on CodeComposer Studio assembly syntax compatibility mode.
  5764. '-mwarn-syms'
  5765. '-mno-warn-syms'
  5766. Enable or disable warnings about symbols that match the names of
  5767. ARM instructions. The default is to warn.
  5768. 
  5769. File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent
  5770. 9.4.2 Syntax
  5771. ------------
  5772. * Menu:
  5773. * ARM-Instruction-Set:: Instruction Set
  5774. * ARM-Chars:: Special Characters
  5775. * ARM-Regs:: Register Names
  5776. * ARM-Relocations:: Relocations
  5777. * ARM-Neon-Alignment:: NEON Alignment Specifiers
  5778. 
  5779. File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax
  5780. 9.4.2.1 Instruction Set Syntax
  5781. ..............................
  5782. Two slightly different syntaxes are support for ARM and THUMB
  5783. instructions. The default, 'divided', uses the old style where ARM and
  5784. THUMB instructions had their own, separate syntaxes. The new, 'unified'
  5785. syntax, which can be selected via the '.syntax' directive, and has the
  5786. following main features:
  5787. * Immediate operands do not require a '#' prefix.
  5788. * The 'IT' instruction may appear, and if it does it is validated
  5789. against subsequent conditional affixes. In ARM mode it does not
  5790. generate machine code, in THUMB mode it does.
  5791. * For ARM instructions the conditional affixes always appear at the
  5792. end of the instruction. For THUMB instructions conditional affixes
  5793. can be used, but only inside the scope of an 'IT' instruction.
  5794. * All of the instructions new to the V6T2 architecture (and later)
  5795. are available. (Only a few such instructions can be written in the
  5796. 'divided' syntax).
  5797. * The '.N' and '.W' suffixes are recognized and honored.
  5798. * All instructions set the flags if and only if they have an 's'
  5799. affix.
  5800. 
  5801. File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax
  5802. 9.4.2.2 Special Characters
  5803. ..........................
  5804. The presence of a '@' anywhere on a line indicates the start of a
  5805. comment that extends to the end of that line.
  5806. If a '#' appears as the first character of a line then the whole line
  5807. is treated as a comment, but in this case the line could also be a
  5808. logical line number directive (*note Comments::) or a preprocessor
  5809. control command (*note Preprocessing::).
  5810. The ';' character can be used instead of a newline to separate
  5811. statements.
  5812. Either '#' or '$' can be used to indicate immediate operands.
  5813. *TODO* Explain about /data modifier on symbols.
  5814. 
  5815. File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax
  5816. 9.4.2.3 Register Names
  5817. ......................
  5818. *TODO* Explain about ARM register naming, and the predefined names.
  5819. 
  5820. File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax
  5821. 9.4.2.4 ARM relocation generation
  5822. .................................
  5823. Specific data relocations can be generated by putting the relocation
  5824. name in parentheses after the symbol name. For example:
  5825. .word foo(TARGET1)
  5826. This will generate an 'R_ARM_TARGET1' relocation against the symbol
  5827. FOO. The following relocations are supported: 'GOT', 'GOTOFF',
  5828. 'TARGET1', 'TARGET2', 'SBREL', 'TLSGD', 'TLSLDM', 'TLSLDO', 'TLSDESC',
  5829. 'TLSCALL', 'GOTTPOFF', 'GOT_PREL' and 'TPOFF'.
  5830. For compatibility with older toolchains the assembler also accepts
  5831. '(PLT)' after branch targets. On legacy targets this will generate the
  5832. deprecated 'R_ARM_PLT32' relocation. On EABI targets it will encode
  5833. either the 'R_ARM_CALL' or 'R_ARM_JUMP24' relocation, as appropriate.
  5834. Relocations for 'MOVW' and 'MOVT' instructions can be generated by
  5835. prefixing the value with '#:lower16:' and '#:upper16' respectively. For
  5836. example to load the 32-bit address of foo into r0:
  5837. MOVW r0, #:lower16:foo
  5838. MOVT r0, #:upper16:foo
  5839. Relocations 'R_ARM_THM_ALU_ABS_G0_NC', 'R_ARM_THM_ALU_ABS_G1_NC',
  5840. 'R_ARM_THM_ALU_ABS_G2_NC' and 'R_ARM_THM_ALU_ABS_G3_NC' can be generated
  5841. by prefixing the value with '#:lower0_7:#', '#:lower8_15:#',
  5842. '#:upper0_7:#' and '#:upper8_15:#' respectively. For example to load
  5843. the 32-bit address of foo into r0:
  5844. MOVS r0, #:upper8_15:#foo
  5845. LSLS r0, r0, #8
  5846. ADDS r0, #:upper0_7:#foo
  5847. LSLS r0, r0, #8
  5848. ADDS r0, #:lower8_15:#foo
  5849. LSLS r0, r0, #8
  5850. ADDS r0, #:lower0_7:#foo
  5851. 
  5852. File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax
  5853. 9.4.2.5 NEON Alignment Specifiers
  5854. .................................
  5855. Some NEON load/store instructions allow an optional address alignment
  5856. qualifier. The ARM documentation specifies that this is indicated by '@
  5857. ALIGN'. However GAS already interprets the '@' character as a "line
  5858. comment" start, so ': ALIGN' is used instead. For example:
  5859. vld1.8 {q0}, [r0, :128]
  5860. 
  5861. File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent
  5862. 9.4.3 Floating Point
  5863. --------------------
  5864. The ARM family uses IEEE floating-point numbers.
  5865. 
  5866. File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent
  5867. 9.4.4 ARM Machine Directives
  5868. ----------------------------
  5869. '.2byte EXPRESSION [, EXPRESSION]*'
  5870. '.4byte EXPRESSION [, EXPRESSION]*'
  5871. '.8byte EXPRESSION [, EXPRESSION]*'
  5872. These directives write 2, 4 or 8 byte values to the output section.
  5873. '.align EXPRESSION [, EXPRESSION]'
  5874. This is the generic .ALIGN directive. For the ARM however if the
  5875. first argument is zero (ie no alignment is needed) the assembler
  5876. will behave as if the argument had been 2 (ie pad to the next four
  5877. byte boundary). This is for compatibility with ARM's own
  5878. assembler.
  5879. '.arch NAME'
  5880. Select the target architecture. Valid values for NAME are the same
  5881. as for the '-march' commandline option.
  5882. Specifying '.arch' clears any previously selected architecture
  5883. extensions.
  5884. '.arch_extension NAME'
  5885. Add or remove an architecture extension to the target architecture.
  5886. Valid values for NAME are the same as those accepted as
  5887. architectural extensions by the '-mcpu' commandline option.
  5888. '.arch_extension' may be used multiple times to add or remove
  5889. extensions incrementally to the architecture being compiled for.
  5890. '.arm'
  5891. This performs the same action as .CODE 32.
  5892. '.bss'
  5893. This directive switches to the '.bss' section.
  5894. '.cantunwind'
  5895. Prevents unwinding through the current function. No personality
  5896. routine or exception table data is required or permitted.
  5897. '.code [16|32]'
  5898. This directive selects the instruction set being generated. The
  5899. value 16 selects Thumb, with the value 32 selecting ARM.
  5900. '.cpu NAME'
  5901. Select the target processor. Valid values for NAME are the same as
  5902. for the '-mcpu' commandline option.
  5903. Specifying '.cpu' clears any previously selected architecture
  5904. extensions.
  5905. 'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]'
  5906. 'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]'
  5907. The 'dn' and 'qn' directives are used to create typed and/or
  5908. indexed register aliases for use in Advanced SIMD Extension (Neon)
  5909. instructions. The former should be used to create aliases of
  5910. double-precision registers, and the latter to create aliases of
  5911. quad-precision registers.
  5912. If these directives are used to create typed aliases, those aliases
  5913. can be used in Neon instructions instead of writing types after the
  5914. mnemonic or after each operand. For example:
  5915. x .dn d2.f32
  5916. y .dn d3.f32
  5917. z .dn d4.f32[1]
  5918. vmul x,y,z
  5919. This is equivalent to writing the following:
  5920. vmul.f32 d2,d3,d4[1]
  5921. Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'.
  5922. '.eabi_attribute TAG, VALUE'
  5923. Set the EABI object attribute TAG to VALUE.
  5924. The TAG is either an attribute number, or one of the following:
  5925. 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch',
  5926. 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use',
  5927. 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch',
  5928. 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 'Tag_ABI_PCS_RW_data',
  5929. 'Tag_ABI_PCS_RO_data', 'Tag_ABI_PCS_GOT_use',
  5930. 'Tag_ABI_PCS_wchar_t', 'Tag_ABI_FP_rounding',
  5931. 'Tag_ABI_FP_denormal', 'Tag_ABI_FP_exceptions',
  5932. 'Tag_ABI_FP_user_exceptions', 'Tag_ABI_FP_number_model',
  5933. 'Tag_ABI_align_needed', 'Tag_ABI_align_preserved',
  5934. 'Tag_ABI_enum_size', 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args',
  5935. 'Tag_ABI_WMMX_args', 'Tag_ABI_optimization_goals',
  5936. 'Tag_ABI_FP_optimization_goals', 'Tag_compatibility',
  5937. 'Tag_CPU_unaligned_access', 'Tag_FP_HP_extension',
  5938. 'Tag_ABI_FP_16bit_format', 'Tag_MPextension_use', 'Tag_DIV_use',
  5939. 'Tag_nodefaults', 'Tag_also_compatible_with', 'Tag_conformance',
  5940. 'Tag_T2EE_use', 'Tag_Virtualization_use'
  5941. The VALUE is either a 'number', '"string"', or 'number, "string"'
  5942. depending on the tag.
  5943. Note - the following legacy values are also accepted by TAG:
  5944. 'Tag_VFP_arch', 'Tag_ABI_align8_needed',
  5945. 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension',
  5946. '.even'
  5947. This directive aligns to an even-numbered address.
  5948. '.extend EXPRESSION [, EXPRESSION]*'
  5949. '.ldouble EXPRESSION [, EXPRESSION]*'
  5950. These directives write 12byte long double floating-point values to
  5951. the output section. These are not compatible with current ARM
  5952. processors or ABIs.
  5953. '.fnend'
  5954. Marks the end of a function with an unwind table entry. The unwind
  5955. index table entry is created when this directive is processed.
  5956. If no personality routine has been specified then standard
  5957. personality routine 0 or 1 will be used, depending on the number of
  5958. unwind opcodes required.
  5959. '.fnstart'
  5960. Marks the start of a function with an unwind table entry.
  5961. '.force_thumb'
  5962. This directive forces the selection of Thumb instructions, even if
  5963. the target processor does not support those instructions
  5964. '.fpu NAME'
  5965. Select the floating-point unit to assemble for. Valid values for
  5966. NAME are the same as for the '-mfpu' commandline option.
  5967. '.handlerdata'
  5968. Marks the end of the current function, and the start of the
  5969. exception table entry for that function. Anything between this
  5970. directive and the '.fnend' directive will be added to the exception
  5971. table entry.
  5972. Must be preceded by a '.personality' or '.personalityindex'
  5973. directive.
  5974. '.inst OPCODE [ , ... ]'
  5975. '.inst.n OPCODE [ , ... ]'
  5976. '.inst.w OPCODE [ , ... ]'
  5977. Generates the instruction corresponding to the numerical value
  5978. OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size
  5979. to be specified explicitly, overriding the normal encoding rules.
  5980. '.ldouble EXPRESSION [, EXPRESSION]*'
  5981. See '.extend'.
  5982. '.ltorg'
  5983. This directive causes the current contents of the literal pool to
  5984. be dumped into the current section (which is assumed to be the
  5985. .text section) at the current location (aligned to a word
  5986. boundary). 'GAS' maintains a separate literal pool for each
  5987. section and each sub-section. The '.ltorg' directive will only
  5988. affect the literal pool of the current section and sub-section. At
  5989. the end of assembly all remaining, un-empty literal pools will
  5990. automatically be dumped.
  5991. Note - older versions of 'GAS' would dump the current literal pool
  5992. any time a section change occurred. This is no longer done, since
  5993. it prevents accurate control of the placement of literal pools.
  5994. '.movsp REG [, #OFFSET]'
  5995. Tell the unwinder that REG contains an offset from the current
  5996. stack pointer. If OFFSET is not specified then it is assumed to be
  5997. zero.
  5998. '.object_arch NAME'
  5999. Override the architecture recorded in the EABI object attribute
  6000. section. Valid values for NAME are the same as for the '.arch'
  6001. directive. Typically this is useful when code uses runtime
  6002. detection of CPU features.
  6003. '.packed EXPRESSION [, EXPRESSION]*'
  6004. This directive writes 12-byte packed floating-point values to the
  6005. output section. These are not compatible with current ARM
  6006. processors or ABIs.
  6007. '.pad #COUNT'
  6008. Generate unwinder annotations for a stack adjustment of COUNT
  6009. bytes. A positive value indicates the function prologue allocated
  6010. stack space by decrementing the stack pointer.
  6011. '.personality NAME'
  6012. Sets the personality routine for the current function to NAME.
  6013. '.personalityindex INDEX'
  6014. Sets the personality routine for the current function to the EABI
  6015. standard routine number INDEX
  6016. '.pool'
  6017. This is a synonym for .ltorg.
  6018. 'NAME .req REGISTER NAME'
  6019. This creates an alias for REGISTER NAME called NAME. For example:
  6020. foo .req r0
  6021. '.save REGLIST'
  6022. Generate unwinder annotations to restore the registers in REGLIST.
  6023. The format of REGLIST is the same as the corresponding
  6024. store-multiple instruction.
  6025. _core registers_
  6026. .save {r4, r5, r6, lr}
  6027. stmfd sp!, {r4, r5, r6, lr}
  6028. _FPA registers_
  6029. .save f4, 2
  6030. sfmfd f4, 2, [sp]!
  6031. _VFP registers_
  6032. .save {d8, d9, d10}
  6033. fstmdx sp!, {d8, d9, d10}
  6034. _iWMMXt registers_
  6035. .save {wr10, wr11}
  6036. wstrd wr11, [sp, #-8]!
  6037. wstrd wr10, [sp, #-8]!
  6038. or
  6039. .save wr11
  6040. wstrd wr11, [sp, #-8]!
  6041. .save wr10
  6042. wstrd wr10, [sp, #-8]!
  6043. '.setfp FPREG, SPREG [, #OFFSET]'
  6044. Make all unwinder annotations relative to a frame pointer. Without
  6045. this the unwinder will use offsets from the stack pointer.
  6046. The syntax of this directive is the same as the 'add' or 'mov'
  6047. instruction used to set the frame pointer. SPREG must be either
  6048. 'sp' or mentioned in a previous '.movsp' directive.
  6049. .movsp ip
  6050. mov ip, sp
  6051. ...
  6052. .setfp fp, ip, #4
  6053. add fp, ip, #4
  6054. '.secrel32 EXPRESSION [, EXPRESSION]*'
  6055. This directive emits relocations that evaluate to the
  6056. section-relative offset of each expression's symbol. This
  6057. directive is only supported for PE targets.
  6058. '.syntax [unified | divided]'
  6059. This directive sets the Instruction Set Syntax as described in the
  6060. *note ARM-Instruction-Set:: section.
  6061. '.thumb'
  6062. This performs the same action as .CODE 16.
  6063. '.thumb_func'
  6064. This directive specifies that the following symbol is the name of a
  6065. Thumb encoded function. This information is necessary in order to
  6066. allow the assembler and linker to generate correct code for
  6067. interworking between Arm and Thumb instructions and should be used
  6068. even if interworking is not going to be performed. The presence of
  6069. this directive also implies '.thumb'
  6070. This directive is not neccessary when generating EABI objects. On
  6071. these targets the encoding is implicit when generating Thumb code.
  6072. '.thumb_set'
  6073. This performs the equivalent of a '.set' directive in that it
  6074. creates a symbol which is an alias for another symbol (possibly not
  6075. yet defined). This directive also has the added property in that
  6076. it marks the aliased symbol as being a thumb function entry point,
  6077. in the same way that the '.thumb_func' directive does.
  6078. '.tlsdescseq TLS-VARIABLE'
  6079. This directive is used to annotate parts of an inlined TLS
  6080. descriptor trampoline. Normally the trampoline is provided by the
  6081. linker, and this directive is not needed.
  6082. '.unreq ALIAS-NAME'
  6083. This undefines a register alias which was previously defined using
  6084. the 'req', 'dn' or 'qn' directives. For example:
  6085. foo .req r0
  6086. .unreq foo
  6087. An error occurs if the name is undefined. Note - this pseudo op
  6088. can be used to delete builtin in register name aliases (eg 'r0').
  6089. This should only be done if it is really necessary.
  6090. '.unwind_raw OFFSET, BYTE1, ...'
  6091. Insert one of more arbitary unwind opcode bytes, which are known to
  6092. adjust the stack pointer by OFFSET bytes.
  6093. For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save
  6094. {r0}'
  6095. '.vsave VFP-REGLIST'
  6096. Generate unwinder annotations to restore the VFP registers in
  6097. VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to
  6098. be restored using VLDM. The format of VFP-REGLIST is the same as
  6099. the corresponding store-multiple instruction.
  6100. _VFP registers_
  6101. .vsave {d8, d9, d10}
  6102. fstmdd sp!, {d8, d9, d10}
  6103. _VFPv3 registers_
  6104. .vsave {d15, d16, d17}
  6105. vstm sp!, {d15, d16, d17}
  6106. Since FLDMX and FSTMX are now deprecated, this directive should be
  6107. used in favour of '.save' for saving VFP registers for ARMv6 and
  6108. above.
  6109. 
  6110. File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent
  6111. 9.4.5 Opcodes
  6112. -------------
  6113. 'as' implements all the standard ARM opcodes. It also implements
  6114. several pseudo opcodes, including several synthetic load instructions.
  6115. 'NOP'
  6116. nop
  6117. This pseudo op will always evaluate to a legal ARM instruction that
  6118. does nothing. Currently it will evaluate to MOV r0, r0.
  6119. 'LDR'
  6120. ldr <register> , = <expression>
  6121. If expression evaluates to a numeric constant then a MOV or MVN
  6122. instruction will be used in place of the LDR instruction, if the
  6123. constant can be generated by either of these instructions.
  6124. Otherwise the constant will be placed into the nearest literal pool
  6125. (if it not already there) and a PC relative LDR instruction will be
  6126. generated.
  6127. 'ADR'
  6128. adr <register> <label>
  6129. This instruction will load the address of LABEL into the indicated
  6130. register. The instruction will evaluate to a PC relative ADD or
  6131. SUB instruction depending upon where the label is located. If the
  6132. label is out of range, or if it is not defined in the same file
  6133. (and section) as the ADR instruction, then an error will be
  6134. generated. This instruction will not make use of the literal pool.
  6135. 'ADRL'
  6136. adrl <register> <label>
  6137. This instruction will load the address of LABEL into the indicated
  6138. register. The instruction will evaluate to one or two PC relative
  6139. ADD or SUB instructions depending upon where the label is located.
  6140. If a second instruction is not needed a NOP instruction will be
  6141. generated in its place, so that this instruction is always 8 bytes
  6142. long.
  6143. If the label is out of range, or if it is not defined in the same
  6144. file (and section) as the ADRL instruction, then an error will be
  6145. generated. This instruction will not make use of the literal pool.
  6146. For information on the ARM or Thumb instruction sets, see 'ARM
  6147. Software Development Toolkit Reference Manual', Advanced RISC Machines
  6148. Ltd.
  6149. 
  6150. File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent
  6151. 9.4.6 Mapping Symbols
  6152. ---------------------
  6153. The ARM ELF specification requires that special symbols be inserted into
  6154. object files to mark certain features:
  6155. '$a'
  6156. At the start of a region of code containing ARM instructions.
  6157. '$t'
  6158. At the start of a region of code containing THUMB instructions.
  6159. '$d'
  6160. At the start of a region of data.
  6161. The assembler will automatically insert these symbols for you - there
  6162. is no need to code them yourself. Support for tagging symbols ($b, $f,
  6163. $p and $m) which is also mentioned in the current ARM ELF specification
  6164. is not implemented. This is because they have been dropped from the new
  6165. EABI and so tools cannot rely upon their presence.
  6166. 
  6167. File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent
  6168. 9.4.7 Unwinding
  6169. ---------------
  6170. The ABI for the ARM Architecture specifies a standard format for
  6171. exception unwind information. This information is used when an
  6172. exception is thrown to determine where control should be transferred.
  6173. In particular, the unwind information is used to determine which
  6174. function called the function that threw the exception, and which
  6175. function called that one, and so forth. This information is also used
  6176. to restore the values of callee-saved registers in the function catching
  6177. the exception.
  6178. If you are writing functions in assembly code, and those functions
  6179. call other functions that throw exceptions, you must use assembly pseudo
  6180. ops to ensure that appropriate exception unwind information is
  6181. generated. Otherwise, if one of the functions called by your assembly
  6182. code throws an exception, the run-time library will be unable to unwind
  6183. the stack through your assembly code and your program will not behave
  6184. correctly.
  6185. To illustrate the use of these pseudo ops, we will examine the code
  6186. that G++ generates for the following C++ input:
  6187. void callee (int *);
  6188. int
  6189. caller ()
  6190. {
  6191. int i;
  6192. callee (&i);
  6193. return i;
  6194. }
  6195. This example does not show how to throw or catch an exception from
  6196. assembly code. That is a much more complex operation and should always
  6197. be done in a high-level language, such as C++, that directly supports
  6198. exceptions.
  6199. The code generated by one particular version of G++ when compiling
  6200. the example above is:
  6201. _Z6callerv:
  6202. .fnstart
  6203. .LFB2:
  6204. @ Function supports interworking.
  6205. @ args = 0, pretend = 0, frame = 8
  6206. @ frame_needed = 1, uses_anonymous_args = 0
  6207. stmfd sp!, {fp, lr}
  6208. .save {fp, lr}
  6209. .LCFI0:
  6210. .setfp fp, sp, #4
  6211. add fp, sp, #4
  6212. .LCFI1:
  6213. .pad #8
  6214. sub sp, sp, #8
  6215. .LCFI2:
  6216. sub r3, fp, #8
  6217. mov r0, r3
  6218. bl _Z6calleePi
  6219. ldr r3, [fp, #-8]
  6220. mov r0, r3
  6221. sub sp, fp, #4
  6222. ldmfd sp!, {fp, lr}
  6223. bx lr
  6224. .LFE2:
  6225. .fnend
  6226. Of course, the sequence of instructions varies based on the options
  6227. you pass to GCC and on the version of GCC in use. The exact
  6228. instructions are not important since we are focusing on the pseudo ops
  6229. that are used to generate unwind information.
  6230. An important assumption made by the unwinder is that the stack frame
  6231. does not change during the body of the function. In particular, since
  6232. we assume that the assembly code does not itself throw an exception, the
  6233. only point where an exception can be thrown is from a call, such as the
  6234. 'bl' instruction above. At each call site, the same saved registers
  6235. (including 'lr', which indicates the return address) must be located in
  6236. the same locations relative to the frame pointer.
  6237. The '.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op
  6238. appears immediately before the first instruction of the function while
  6239. the '.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears
  6240. immediately after the last instruction of the function. These pseudo
  6241. ops specify the range of the function.
  6242. Only the order of the other pseudos ops (e.g., '.setfp' or '.pad')
  6243. matters; their exact locations are irrelevant. In the example above,
  6244. the compiler emits the pseudo ops with particular instructions. That
  6245. makes it easier to understand the code, but it is not required for
  6246. correctness. It would work just as well to emit all of the pseudo ops
  6247. other than '.fnend' in the same order, but immediately after '.fnstart'.
  6248. The '.save' (*note .save pseudo op: arm_save.) pseudo op indicates
  6249. registers that have been saved to the stack so that they can be restored
  6250. before the function returns. The argument to the '.save' pseudo op is a
  6251. list of registers to save. If a register is "callee-saved" (as
  6252. specified by the ABI) and is modified by the function you are writing,
  6253. then your code must save the value before it is modified and restore the
  6254. original value before the function returns. If an exception is thrown,
  6255. the run-time library restores the values of these registers from their
  6256. locations on the stack before returning control to the exception
  6257. handler. (Of course, if an exception is not thrown, the function that
  6258. contains the '.save' pseudo op restores these registers in the function
  6259. epilogue, as is done with the 'ldmfd' instruction above.)
  6260. You do not have to save callee-saved registers at the very beginning
  6261. of the function and you do not need to use the '.save' pseudo op
  6262. immediately following the point at which the registers are saved.
  6263. However, if you modify a callee-saved register, you must save it on the
  6264. stack before modifying it and before calling any functions which might
  6265. throw an exception. And, you must use the '.save' pseudo op to indicate
  6266. that you have done so.
  6267. The '.pad' (*note .pad: arm_pad.) pseudo op indicates a modification
  6268. of the stack pointer that does not save any registers. The argument is
  6269. the number of bytes (in decimal) that are subtracted from the stack
  6270. pointer. (On ARM CPUs, the stack grows downwards, so subtracting from
  6271. the stack pointer increases the size of the stack.)
  6272. The '.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op indicates
  6273. the register that contains the frame pointer. The first argument is the
  6274. register that is set, which is typically 'fp'. The second argument
  6275. indicates the register from which the frame pointer takes its value.
  6276. The third argument, if present, is the value (in decimal) added to the
  6277. register specified by the second argument to compute the value of the
  6278. frame pointer. You should not modify the frame pointer in the body of
  6279. the function.
  6280. If you do not use a frame pointer, then you should not use the
  6281. '.setfp' pseudo op. If you do not use a frame pointer, then you should
  6282. avoid modifying the stack pointer outside of the function prologue.
  6283. Otherwise, the run-time library will be unable to find saved registers
  6284. when it is unwinding the stack.
  6285. The pseudo ops described above are sufficient for writing assembly
  6286. code that calls functions which may throw exceptions. If you need to
  6287. know more about the object-file format used to represent unwind
  6288. information, you may consult the 'Exception Handling ABI for the ARM
  6289. Architecture' available from <http://infocenter.arm.com>.
  6290. 
  6291. File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies
  6292. 9.5 AVR Dependent Features
  6293. ==========================
  6294. * Menu:
  6295. * AVR Options:: Options
  6296. * AVR Syntax:: Syntax
  6297. * AVR Opcodes:: Opcodes
  6298. 
  6299. File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent
  6300. 9.5.1 Options
  6301. -------------
  6302. '-mmcu=MCU'
  6303. Specify ATMEL AVR instruction set or MCU type.
  6304. Instruction set avr1 is for the minimal AVR core, not supported by
  6305. the C compiler, only for assembler programs (MCU types: at90s1200,
  6306. attiny11, attiny12, attiny15, attiny28).
  6307. Instruction set avr2 (default) is for the classic AVR core with up
  6308. to 8K program memory space (MCU types: at90s2313, at90s2323,
  6309. at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433,
  6310. at90s4434, at90s8515, at90c8534, at90s8535).
  6311. Instruction set avr25 is for the classic AVR core with up to 8K
  6312. program memory space plus the MOVW instruction (MCU types:
  6313. attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a,
  6314. attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25,
  6315. attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a,
  6316. attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88,
  6317. attiny828, at86rf401, ata6289, ata5272).
  6318. Instruction set avr3 is for the classic AVR core with up to 128K
  6319. program memory space (MCU types: at43usb355, at76c711).
  6320. Instruction set avr31 is for the classic AVR core with exactly 128K
  6321. program memory space (MCU types: atmega103, at43usb320).
  6322. Instruction set avr35 is for classic AVR core plus MOVW, CALL, and
  6323. JMP instructions (MCU types: attiny167, attiny1634, at90usb82,
  6324. at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505).
  6325. Instruction set avr4 is for the enhanced AVR core with up to 8K
  6326. program memory space (MCU types: atmega48, atmega48a, atmega48pa,
  6327. atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p,
  6328. atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2,
  6329. at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286).
  6330. Instruction set avr5 is for the enhanced AVR core with up to 128K
  6331. program memory space (MCU types: at90pwm161, atmega16, atmega16a,
  6332. atmega161, atmega162, atmega163, atmega164a, atmega164p,
  6333. atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa,
  6334. atmega168, atmega168a, atmega168p, atmega168pa, atmega169,
  6335. atmega169a, atmega169p, atmega169pa, atmega32, atmega323,
  6336. atmega324a, atmega324p, atmega324pa, atmega325, atmega325a,
  6337. atmega32, atmega32a, atmega323, atmega324a, atmega324p,
  6338. atmega324pa, atmega325, atmega325a, atmega325p, atmega325p,
  6339. atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa,
  6340. atmega328, atmega328p, atmega329, atmega329a, atmega329p,
  6341. atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406,
  6342. atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640,
  6343. atmega644, atmega644a, atmega644p, atmega644pa, atmega645,
  6344. atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p,
  6345. atmega649, atmega649a, atmega649p, atmega6490, atmega6490a,
  6346. atmega6490p, atmega16hva, atmega16hva2, atmega16hvb,
  6347. atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve,
  6348. at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316,
  6349. atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1,
  6350. atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k,
  6351. at90scr100, ata5790, ata5795).
  6352. Instruction set avr51 is for the enhanced AVR core with exactly
  6353. 128K program memory space (MCU types: atmega128, atmega128a,
  6354. atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1,
  6355. atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
  6356. at90usb1287, m3000).
  6357. Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
  6358. (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
  6359. Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K
  6360. program memory space and less than 64K data space (MCU types:
  6361. atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1,
  6362. atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5,
  6363. atxmega8e5, atxmega32e5, atxmega32x1).
  6364. Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K
  6365. program memory space and greater than 64K data space (MCU types:
  6366. none).
  6367. Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K
  6368. program memory space and less than 64K data space (MCU types:
  6369. atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3,
  6370. atxmega64c3, atxmega64d3, atxmega64d4).
  6371. Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K
  6372. program memory space and greater than 64K data space (MCU types:
  6373. atxmega64a1, atxmega64a1u).
  6374. Instruction set avrxmega6 is for the XMEGA AVR core with larger
  6375. than 64K program memory space and less than 64K data space (MCU
  6376. types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3,
  6377. atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1,
  6378. atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3,
  6379. atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3,
  6380. atxmega256d3, atxmega384c3, atxmega256d3).
  6381. Instruction set avrxmega7 is for the XMEGA AVR core with larger
  6382. than 64K program memory space and greater than 64K data space (MCU
  6383. types: atxmega128a1, atxmega128a1u, atxmega128a4u).
  6384. Instruction set avrtiny is for the ATtiny4/5/9/10/20/40
  6385. microcontrollers.
  6386. '-mall-opcodes'
  6387. Accept all AVR opcodes, even if not supported by '-mmcu'.
  6388. '-mno-skip-bug'
  6389. This option disable warnings for skipping two-word instructions.
  6390. '-mno-wrap'
  6391. This option reject 'rjmp/rcall' instructions with 8K wrap-around.
  6392. '-mrmw'
  6393. Accept Read-Modify-Write ('XCH,LAC,LAS,LAT') instructions.
  6394. '-mlink-relax'
  6395. Enable support for link-time relaxation. This is now on by default
  6396. and this flag no longer has any effect.
  6397. '-mno-link-relax'
  6398. Disable support for link-time relaxation. The assembler will
  6399. resolve relocations when it can, and may be able to better compress
  6400. some debug information.
  6401. 
  6402. File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent
  6403. 9.5.2 Syntax
  6404. ------------
  6405. * Menu:
  6406. * AVR-Chars:: Special Characters
  6407. * AVR-Regs:: Register Names
  6408. * AVR-Modifiers:: Relocatable Expression Modifiers
  6409. 
  6410. File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax
  6411. 9.5.2.1 Special Characters
  6412. ..........................
  6413. The presence of a ';' anywhere on a line indicates the start of a
  6414. comment that extends to the end of that line.
  6415. If a '#' appears as the first character of a line, the whole line is
  6416. treated as a comment, but in this case the line can also be a logical
  6417. line number directive (*note Comments::) or a preprocessor control
  6418. command (*note Preprocessing::).
  6419. The '$' character can be used instead of a newline to separate
  6420. statements.
  6421. 
  6422. File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax
  6423. 9.5.2.2 Register Names
  6424. ......................
  6425. The AVR has 32 x 8-bit general purpose working registers 'r0', 'r1', ...
  6426. 'r31'. Six of the 32 registers can be used as three 16-bit indirect
  6427. address register pointers for Data Space addressing. One of the these
  6428. address pointers can also be used as an address pointer for look up
  6429. tables in Flash program memory. These added function registers are the
  6430. 16-bit 'X', 'Y' and 'Z' - registers.
  6431. X = r26:r27
  6432. Y = r28:r29
  6433. Z = r30:r31
  6434. 
  6435. File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax
  6436. 9.5.2.3 Relocatable Expression Modifiers
  6437. ........................................
  6438. The assembler supports several modifiers when using relocatable
  6439. addresses in AVR instruction operands. The general syntax is the
  6440. following:
  6441. modifier(relocatable-expression)
  6442. 'lo8'
  6443. This modifier allows you to use bits 0 through 7 of an address
  6444. expression as 8 bit relocatable expression.
  6445. 'hi8'
  6446. This modifier allows you to use bits 7 through 15 of an address
  6447. expression as 8 bit relocatable expression. This is useful with,
  6448. for example, the AVR 'ldi' instruction and 'lo8' modifier.
  6449. For example
  6450. ldi r26, lo8(sym+10)
  6451. ldi r27, hi8(sym+10)
  6452. 'hh8'
  6453. This modifier allows you to use bits 16 through 23 of an address
  6454. expression as 8 bit relocatable expression. Also, can be useful
  6455. for loading 32 bit constants.
  6456. 'hlo8'
  6457. Synonym of 'hh8'.
  6458. 'hhi8'
  6459. This modifier allows you to use bits 24 through 31 of an expression
  6460. as 8 bit expression. This is useful with, for example, the AVR
  6461. 'ldi' instruction and 'lo8', 'hi8', 'hlo8', 'hhi8', modifier.
  6462. For example
  6463. ldi r26, lo8(285774925)
  6464. ldi r27, hi8(285774925)
  6465. ldi r28, hlo8(285774925)
  6466. ldi r29, hhi8(285774925)
  6467. ; r29,r28,r27,r26 = 285774925
  6468. 'pm_lo8'
  6469. This modifier allows you to use bits 0 through 7 of an address
  6470. expression as 8 bit relocatable expression. This modifier useful
  6471. for addressing data or code from Flash/Program memory. The using
  6472. of 'pm_lo8' similar to 'lo8'.
  6473. 'pm_hi8'
  6474. This modifier allows you to use bits 8 through 15 of an address
  6475. expression as 8 bit relocatable expression. This modifier useful
  6476. for addressing data or code from Flash/Program memory.
  6477. 'pm_hh8'
  6478. This modifier allows you to use bits 15 through 23 of an address
  6479. expression as 8 bit relocatable expression. This modifier useful
  6480. for addressing data or code from Flash/Program memory.
  6481. 
  6482. File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent
  6483. 9.5.3 Opcodes
  6484. -------------
  6485. For detailed information on the AVR machine instruction set, see
  6486. <www.atmel.com/products/AVR>.
  6487. 'as' implements all the standard AVR opcodes. The following table
  6488. summarizes the AVR opcodes, and their arguments.
  6489. Legend:
  6490. r any register
  6491. d 'ldi' register (r16-r31)
  6492. v 'movw' even register (r0, r2, ..., r28, r30)
  6493. a 'fmul' register (r16-r23)
  6494. w 'adiw' register (r24,r26,r28,r30)
  6495. e pointer registers (X,Y,Z)
  6496. b base pointer register and displacement ([YZ]+disp)
  6497. z Z pointer register (for [e]lpm Rd,Z[+])
  6498. M immediate value from 0 to 255
  6499. n immediate value from 0 to 255 ( n = ~M ). Relocation impossible
  6500. s immediate value from 0 to 7
  6501. P Port address value from 0 to 63. (in, out)
  6502. p Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
  6503. K immediate value from 0 to 63 (used in 'adiw', 'sbiw')
  6504. i immediate value
  6505. l signed pc relative offset from -64 to 63
  6506. L signed pc relative offset from -2048 to 2047
  6507. h absolute code address (call, jmp)
  6508. S immediate value from 0 to 7 (S = s << 4)
  6509. ? use this opcode entry if no parameters, else use next opcode entry
  6510. 1001010010001000 clc
  6511. 1001010011011000 clh
  6512. 1001010011111000 cli
  6513. 1001010010101000 cln
  6514. 1001010011001000 cls
  6515. 1001010011101000 clt
  6516. 1001010010111000 clv
  6517. 1001010010011000 clz
  6518. 1001010000001000 sec
  6519. 1001010001011000 seh
  6520. 1001010001111000 sei
  6521. 1001010000101000 sen
  6522. 1001010001001000 ses
  6523. 1001010001101000 set
  6524. 1001010000111000 sev
  6525. 1001010000011000 sez
  6526. 100101001SSS1000 bclr S
  6527. 100101000SSS1000 bset S
  6528. 1001010100001001 icall
  6529. 1001010000001001 ijmp
  6530. 1001010111001000 lpm ?
  6531. 1001000ddddd010+ lpm r,z
  6532. 1001010111011000 elpm ?
  6533. 1001000ddddd011+ elpm r,z
  6534. 0000000000000000 nop
  6535. 1001010100001000 ret
  6536. 1001010100011000 reti
  6537. 1001010110001000 sleep
  6538. 1001010110011000 break
  6539. 1001010110101000 wdr
  6540. 1001010111101000 spm
  6541. 000111rdddddrrrr adc r,r
  6542. 000011rdddddrrrr add r,r
  6543. 001000rdddddrrrr and r,r
  6544. 000101rdddddrrrr cp r,r
  6545. 000001rdddddrrrr cpc r,r
  6546. 000100rdddddrrrr cpse r,r
  6547. 001001rdddddrrrr eor r,r
  6548. 001011rdddddrrrr mov r,r
  6549. 100111rdddddrrrr mul r,r
  6550. 001010rdddddrrrr or r,r
  6551. 000010rdddddrrrr sbc r,r
  6552. 000110rdddddrrrr sub r,r
  6553. 001001rdddddrrrr clr r
  6554. 000011rdddddrrrr lsl r
  6555. 000111rdddddrrrr rol r
  6556. 001000rdddddrrrr tst r
  6557. 0111KKKKddddKKKK andi d,M
  6558. 0111KKKKddddKKKK cbr d,n
  6559. 1110KKKKddddKKKK ldi d,M
  6560. 11101111dddd1111 ser d
  6561. 0110KKKKddddKKKK ori d,M
  6562. 0110KKKKddddKKKK sbr d,M
  6563. 0011KKKKddddKKKK cpi d,M
  6564. 0100KKKKddddKKKK sbci d,M
  6565. 0101KKKKddddKKKK subi d,M
  6566. 1111110rrrrr0sss sbrc r,s
  6567. 1111111rrrrr0sss sbrs r,s
  6568. 1111100ddddd0sss bld r,s
  6569. 1111101ddddd0sss bst r,s
  6570. 10110PPdddddPPPP in r,P
  6571. 10111PPrrrrrPPPP out P,r
  6572. 10010110KKddKKKK adiw w,K
  6573. 10010111KKddKKKK sbiw w,K
  6574. 10011000pppppsss cbi p,s
  6575. 10011010pppppsss sbi p,s
  6576. 10011001pppppsss sbic p,s
  6577. 10011011pppppsss sbis p,s
  6578. 111101lllllll000 brcc l
  6579. 111100lllllll000 brcs l
  6580. 111100lllllll001 breq l
  6581. 111101lllllll100 brge l
  6582. 111101lllllll101 brhc l
  6583. 111100lllllll101 brhs l
  6584. 111101lllllll111 brid l
  6585. 111100lllllll111 brie l
  6586. 111100lllllll000 brlo l
  6587. 111100lllllll100 brlt l
  6588. 111100lllllll010 brmi l
  6589. 111101lllllll001 brne l
  6590. 111101lllllll010 brpl l
  6591. 111101lllllll000 brsh l
  6592. 111101lllllll110 brtc l
  6593. 111100lllllll110 brts l
  6594. 111101lllllll011 brvc l
  6595. 111100lllllll011 brvs l
  6596. 111101lllllllsss brbc s,l
  6597. 111100lllllllsss brbs s,l
  6598. 1101LLLLLLLLLLLL rcall L
  6599. 1100LLLLLLLLLLLL rjmp L
  6600. 1001010hhhhh111h call h
  6601. 1001010hhhhh110h jmp h
  6602. 1001010rrrrr0101 asr r
  6603. 1001010rrrrr0000 com r
  6604. 1001010rrrrr1010 dec r
  6605. 1001010rrrrr0011 inc r
  6606. 1001010rrrrr0110 lsr r
  6607. 1001010rrrrr0001 neg r
  6608. 1001000rrrrr1111 pop r
  6609. 1001001rrrrr1111 push r
  6610. 1001010rrrrr0111 ror r
  6611. 1001010rrrrr0010 swap r
  6612. 00000001ddddrrrr movw v,v
  6613. 00000010ddddrrrr muls d,d
  6614. 000000110ddd0rrr mulsu a,a
  6615. 000000110ddd1rrr fmul a,a
  6616. 000000111ddd0rrr fmuls a,a
  6617. 000000111ddd1rrr fmulsu a,a
  6618. 1001001ddddd0000 sts i,r
  6619. 1001000ddddd0000 lds r,i
  6620. 10o0oo0dddddbooo ldd r,b
  6621. 100!000dddddee-+ ld r,e
  6622. 10o0oo1rrrrrbooo std b,r
  6623. 100!001rrrrree-+ st e,r
  6624. 1001010100011001 eicall
  6625. 1001010000011001 eijmp
  6626. 
  6627. File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies
  6628. 9.6 Blackfin Dependent Features
  6629. ===============================
  6630. * Menu:
  6631. * Blackfin Options:: Blackfin Options
  6632. * Blackfin Syntax:: Blackfin Syntax
  6633. * Blackfin Directives:: Blackfin Directives
  6634. 
  6635. File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent
  6636. 9.6.1 Options
  6637. -------------
  6638. '-mcpu=PROCESSOR[-SIREVISION]'
  6639. This option specifies the target processor. The optional
  6640. SIREVISION is not used in assembler. It's here such that GCC can
  6641. easily pass down its '-mcpu=' option. The assembler will issue an
  6642. error message if an attempt is made to assemble an instruction
  6643. which will not execute on the target processor. The following
  6644. processor names are recognized: 'bf504', 'bf506', 'bf512', 'bf514',
  6645. 'bf516', 'bf518', 'bf522', 'bf523', 'bf524', 'bf525', 'bf526',
  6646. 'bf527', 'bf531', 'bf532', 'bf533', 'bf534', 'bf535' (not
  6647. implemented yet), 'bf536', 'bf537', 'bf538', 'bf539', 'bf542',
  6648. 'bf542m', 'bf544', 'bf544m', 'bf547', 'bf547m', 'bf548', 'bf548m',
  6649. 'bf549', 'bf549m', 'bf561', and 'bf592'.
  6650. '-mfdpic'
  6651. Assemble for the FDPIC ABI.
  6652. '-mno-fdpic'
  6653. '-mnopic'
  6654. Disable -mfdpic.
  6655. 
  6656. File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent
  6657. 9.6.2 Syntax
  6658. ------------
  6659. 'Special Characters'
  6660. Assembler input is free format and may appear anywhere on the line.
  6661. One instruction may extend across multiple lines or more than one
  6662. instruction may appear on the same line. White space (space, tab,
  6663. comments or newline) may appear anywhere between tokens. A token
  6664. must not have embedded spaces. Tokens include numbers, register
  6665. names, keywords, user identifiers, and also some multicharacter
  6666. special symbols like "+=", "/*" or "||".
  6667. Comments are introduced by the '#' character and extend to the end
  6668. of the current line. If the '#' appears as the first character of
  6669. a line, the whole line is treated as a comment, but in this case
  6670. the line can also be a logical line number directive (*note
  6671. Comments::) or a preprocessor control command (*note
  6672. Preprocessing::).
  6673. 'Instruction Delimiting'
  6674. A semicolon must terminate every instruction. Sometimes a complete
  6675. instruction will consist of more than one operation. There are two
  6676. cases where this occurs. The first is when two general operations
  6677. are combined. Normally a comma separates the different parts, as
  6678. in
  6679. a0= r3.h * r2.l, a1 = r3.l * r2.h ;
  6680. The second case occurs when a general instruction is combined with
  6681. one or two memory references for joint issue. The latter portions
  6682. are set off by a "||" token.
  6683. a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
  6684. Multiple instructions can occur on the same line. Each must be
  6685. terminated by a semicolon character.
  6686. 'Register Names'
  6687. The assembler treats register names and instruction keywords in a
  6688. case insensitive manner. User identifiers are case sensitive.
  6689. Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
  6690. assembler.
  6691. Register names are reserved and may not be used as program
  6692. identifiers.
  6693. Some operations (such as "Move Register") require a register pair.
  6694. Register pairs are always data registers and are denoted using a
  6695. colon, eg., R3:2. The larger number must be written firsts. Note
  6696. that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
  6697. R3:2, and R1:0.
  6698. Some instructions (such as -SP (Push Multiple)) require a group of
  6699. adjacent registers. Adjacent registers are denoted in the syntax
  6700. by the range enclosed in parentheses and separated by a colon, eg.,
  6701. (R7:3). Again, the larger number appears first.
  6702. Portions of a particular register may be individually specified.
  6703. This is written with a dot (".") following the register name and
  6704. then a letter denoting the desired portion. For 32-bit registers,
  6705. ".H" denotes the most significant ("High") portion. ".L" denotes
  6706. the least-significant portion. The subdivisions of the 40-bit
  6707. registers are described later.
  6708. 'Accumulators'
  6709. The set of 40-bit registers A1 and A0 that normally contain data
  6710. that is being manipulated. Each accumulator can be accessed in
  6711. four ways.
  6712. 'one 40-bit register'
  6713. The register will be referred to as A1 or A0.
  6714. 'one 32-bit register'
  6715. The registers are designated as A1.W or A0.W.
  6716. 'two 16-bit registers'
  6717. The registers are designated as A1.H, A1.L, A0.H or A0.L.
  6718. 'one 8-bit register'
  6719. The registers are designated as A1.X or A0.X for the bits that
  6720. extend beyond bit 31.
  6721. 'Data Registers'
  6722. The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
  6723. that normally contain data for manipulation. These are abbreviated
  6724. as D-register or Dreg. Data registers can be accessed as 32-bit
  6725. registers or as two independent 16-bit registers. The least
  6726. significant 16 bits of each register is called the "low" half and
  6727. is designated with ".L" following the register name. The most
  6728. significant 16 bits are called the "high" half and is designated
  6729. with ".H" following the name.
  6730. R7.L, r2.h, r4.L, R0.H
  6731. 'Pointer Registers'
  6732. The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
  6733. that normally contain byte addresses of data structures. These are
  6734. abbreviated as P-register or Preg.
  6735. p2, p5, fp, sp
  6736. 'Stack Pointer SP'
  6737. The stack pointer contains the 32-bit address of the last occupied
  6738. byte location in the stack. The stack grows by decrementing the
  6739. stack pointer.
  6740. 'Frame Pointer FP'
  6741. The frame pointer contains the 32-bit address of the previous frame
  6742. pointer in the stack. It is located at the top of a frame.
  6743. 'Loop Top'
  6744. LT0 and LT1. These registers contain the 32-bit address of the top
  6745. of a zero overhead loop.
  6746. 'Loop Count'
  6747. LC0 and LC1. These registers contain the 32-bit counter of the
  6748. zero overhead loop executions.
  6749. 'Loop Bottom'
  6750. LB0 and LB1. These registers contain the 32-bit address of the
  6751. bottom of a zero overhead loop.
  6752. 'Index Registers'
  6753. The set of 32-bit registers (I0, I1, I2, I3) that normally contain
  6754. byte addresses of data structures. Abbreviated I-register or Ireg.
  6755. 'Modify Registers'
  6756. The set of 32-bit registers (M0, M1, M2, M3) that normally contain
  6757. offset values that are added and subtracted to one of the index
  6758. registers. Abbreviated as Mreg.
  6759. 'Length Registers'
  6760. The set of 32-bit registers (L0, L1, L2, L3) that normally contain
  6761. the length in bytes of the circular buffer. Abbreviated as Lreg.
  6762. Clear the Lreg to disable circular addressing for the corresponding
  6763. Ireg.
  6764. 'Base Registers'
  6765. The set of 32-bit registers (B0, B1, B2, B3) that normally contain
  6766. the base address in bytes of the circular buffer. Abbreviated as
  6767. Breg.
  6768. 'Floating Point'
  6769. The Blackfin family has no hardware floating point but the .float
  6770. directive generates ieee floating point numbers for use with
  6771. software floating point libraries.
  6772. 'Blackfin Opcodes'
  6773. For detailed information on the Blackfin machine instruction set,
  6774. see the Blackfin(r) Processor Instruction Set Reference.
  6775. 
  6776. File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent
  6777. 9.6.3 Directives
  6778. ----------------
  6779. The following directives are provided for compatibility with the VDSP
  6780. assembler.
  6781. '.byte2'
  6782. Initializes a two byte data object.
  6783. This maps to the '.short' directive.
  6784. '.byte4'
  6785. Initializes a four byte data object.
  6786. This maps to the '.int' directive.
  6787. '.db'
  6788. Initializes a single byte data object.
  6789. This directive is a synonym for '.byte'.
  6790. '.dw'
  6791. Initializes a two byte data object.
  6792. This directive is a synonym for '.byte2'.
  6793. '.dd'
  6794. Initializes a four byte data object.
  6795. This directive is a synonym for '.byte4'.
  6796. '.var'
  6797. Define and initialize a 32 bit data object.
  6798. 
  6799. File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies
  6800. 9.7 CR16 Dependent Features
  6801. ===========================
  6802. * Menu:
  6803. * CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
  6804. * CR16 Syntax:: Syntax for the CR16
  6805. 
  6806. File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent
  6807. 9.7.1 CR16 Operand Qualifiers
  6808. -----------------------------
  6809. The National Semiconductor CR16 target of 'as' has a few machine
  6810. dependent operand qualifiers.
  6811. Operand expression type qualifier is an optional field in the
  6812. instruction operand, to determines the type of the expression field of
  6813. an operand. The '@' is required. CR16 architecture uses one of the
  6814. following expression qualifiers:
  6815. 's'
  6816. - 'Specifies expression operand type as small'
  6817. 'm'
  6818. - 'Specifies expression operand type as medium'
  6819. 'l'
  6820. - 'Specifies expression operand type as large'
  6821. 'c'
  6822. - 'Specifies the CR16 Assembler generates a relocation entry for
  6823. the operand, where pc has implied bit, the expression is adjusted
  6824. accordingly. The linker uses the relocation entry to update the
  6825. operand address at link time.'
  6826. 'got/GOT'
  6827. - 'Specifies the CR16 Assembler generates a relocation entry for
  6828. the operand, offset from Global Offset Table. The linker uses this
  6829. relocation entry to update the operand address at link time'
  6830. 'cgot/cGOT'
  6831. - 'Specifies the CompactRISC Assembler generates a relocation entry
  6832. for the operand, where pc has implied bit, the expression is
  6833. adjusted accordingly. The linker uses the relocation entry to
  6834. update the operand address at link time.'
  6835. CR16 target operand qualifiers and its size (in bits):
  6836. 'Immediate Operand: s'
  6837. 4 bits.
  6838. 'Immediate Operand: m'
  6839. 16 bits, for movb and movw instructions.
  6840. 'Immediate Operand: m'
  6841. 20 bits, movd instructions.
  6842. 'Immediate Operand: l'
  6843. 32 bits.
  6844. 'Absolute Operand: s'
  6845. Illegal specifier for this operand.
  6846. 'Absolute Operand: m'
  6847. 20 bits, movd instructions.
  6848. 'Displacement Operand: s'
  6849. 8 bits.
  6850. 'Displacement Operand: m'
  6851. 16 bits.
  6852. 'Displacement Operand: l'
  6853. 24 bits.
  6854. For example:
  6855. 1 movw $_myfun@c,r1
  6856. This loads the address of _myfun, shifted right by 1, into r1.
  6857. 2 movd $_myfun@c,(r2,r1)
  6858. This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
  6859. 3 _myfun_ptr:
  6860. .long _myfun@c
  6861. loadd _myfun_ptr, (r1,r0)
  6862. jal (r1,r0)
  6863. This .long directive, the address of _myfunc, shifted right by 1 at link time.
  6864. 4 loadd _data1@GOT(r12), (r1,r0)
  6865. This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
  6866. 5 loadd _myfunc@cGOT(r12), (r1,r0)
  6867. This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
  6868. 
  6869. File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent
  6870. 9.7.2 CR16 Syntax
  6871. -----------------
  6872. * Menu:
  6873. * CR16-Chars:: Special Characters
  6874. 
  6875. File: as.info, Node: CR16-Chars, Up: CR16 Syntax
  6876. 9.7.2.1 Special Characters
  6877. ..........................
  6878. The presence of a '#' on a line indicates the start of a comment that
  6879. extends to the end of the current line. If the '#' appears as the first
  6880. character of a line, the whole line is treated as a comment, but in this
  6881. case the line can also be a logical line number directive (*note
  6882. Comments::) or a preprocessor control command (*note Preprocessing::).
  6883. The ';' character can be used to separate statements on the same
  6884. line.
  6885. 
  6886. File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies
  6887. 9.8 CRIS Dependent Features
  6888. ===========================
  6889. * Menu:
  6890. * CRIS-Opts:: Command-line Options
  6891. * CRIS-Expand:: Instruction expansion
  6892. * CRIS-Symbols:: Symbols
  6893. * CRIS-Syntax:: Syntax
  6894. 
  6895. File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent
  6896. 9.8.1 Command-line Options
  6897. --------------------------
  6898. The CRIS version of 'as' has these machine-dependent command-line
  6899. options.
  6900. The format of the generated object files can be either ELF or a.out,
  6901. specified by the command-line options '--emulation=crisaout' and
  6902. '--emulation=criself'. The default is ELF (criself), unless 'as' has
  6903. been configured specifically for a.out by using the configuration name
  6904. 'cris-axis-aout'.
  6905. There are two different link-incompatible ELF object file variants
  6906. for CRIS, for use in environments where symbols are expected to be
  6907. prefixed by a leading '_' character and for environments without such a
  6908. symbol prefix. The variant used for GNU/Linux port has no symbol
  6909. prefix. Which variant to produce is specified by either of the options
  6910. '--underscore' and '--no-underscore'. The default is '--underscore'.
  6911. Since symbols in CRIS a.out objects are expected to have a '_' prefix,
  6912. specifying '--no-underscore' when generating a.out objects is an error.
  6913. Besides the object format difference, the effect of this option is to
  6914. parse register names differently (*note crisnous::). The
  6915. '--no-underscore' option makes a '$' register prefix mandatory.
  6916. The option '--pic' must be passed to 'as' in order to recognize the
  6917. symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
  6918. crispic::). This will also affect expansion of instructions. The
  6919. expansion with '--pic' will use PC-relative rather than (slightly
  6920. faster) absolute addresses in those expansions. This option is only
  6921. valid when generating ELF format object files.
  6922. The option '--march=ARCHITECTURE' specifies the recognized
  6923. instruction set and recognized register names. It also controls the
  6924. architecture type of the object file. Valid values for ARCHITECTURE
  6925. are:
  6926. 'v0_v10'
  6927. All instructions and register names for any architecture variant in
  6928. the set v0...v10 are recognized. This is the default if the target
  6929. is configured as cris-*.
  6930. 'v10'
  6931. Only instructions and register names for CRIS v10 (as found in
  6932. ETRAX 100 LX) are recognized. This is the default if the target is
  6933. configured as crisv10-*.
  6934. 'v32'
  6935. Only instructions and register names for CRIS v32 (code name
  6936. Guinness) are recognized. This is the default if the target is
  6937. configured as crisv32-*. This value implies '--no-mul-bug-abort'.
  6938. (A subsequent '--mul-bug-abort' will turn it back on.)
  6939. 'common_v10_v32'
  6940. Only instructions with register names and addressing modes with
  6941. opcodes common to the v10 and v32 are recognized.
  6942. When '-N' is specified, 'as' will emit a warning when a 16-bit branch
  6943. instruction is expanded into a 32-bit multiple-instruction construct
  6944. (*note CRIS-Expand::).
  6945. Some versions of the CRIS v10, for example in the Etrax 100 LX,
  6946. contain a bug that causes destabilizing memory accesses when a multiply
  6947. instruction is executed with certain values in the first operand just
  6948. before a cache-miss. When the '--mul-bug-abort' command line option is
  6949. active (the default value), 'as' will refuse to assemble a file
  6950. containing a multiply instruction at a dangerous offset, one that could
  6951. be the last on a cache-line, or is in a section with insufficient
  6952. alignment. This placement checking does not catch any case where the
  6953. multiply instruction is dangerously placed because it is located in a
  6954. delay-slot. The '--mul-bug-abort' command line option turns off the
  6955. checking.
  6956. 
  6957. File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent
  6958. 9.8.2 Instruction expansion
  6959. ---------------------------
  6960. 'as' will silently choose an instruction that fits the operand size for
  6961. '[register+constant]' operands. For example, the offset '127' in
  6962. 'move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
  6963. Similarly, 'move.d [r2+32767],r1' will generate an instruction using a
  6964. 16-bit offset. For symbolic expressions and constants that do not fit
  6965. in 16 bits including the sign bit, a 32-bit offset is generated.
  6966. For branches, 'as' will expand from a 16-bit branch instruction into
  6967. a sequence of instructions that can reach a full 32-bit address. Since
  6968. this does not correspond to a single instruction, such expansions can
  6969. optionally be warned about. *Note CRIS-Opts::.
  6970. If the operand is found to fit the range, a 'lapc' mnemonic will
  6971. translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit
  6972. 'lapc' instruction.
  6973. Similarly, the 'addo' mnemonic will translate to the shortest fitting
  6974. instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand
  6975. that is a constant known at assembly time.
  6976. 
  6977. File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent
  6978. 9.8.3 Symbols
  6979. -------------
  6980. Some symbols are defined by the assembler. They're intended to be used
  6981. in conditional assembly, for example:
  6982. .if ..asm.arch.cris.v32
  6983. CODE FOR CRIS V32
  6984. .elseif ..asm.arch.cris.common_v10_v32
  6985. CODE COMMON TO CRIS V32 AND CRIS V10
  6986. .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
  6987. CODE FOR V10
  6988. .else
  6989. .error "Code needs to be added here."
  6990. .endif
  6991. These symbols are defined in the assembler, reflecting command-line
  6992. options, either when specified or the default. They are always defined,
  6993. to 0 or 1.
  6994. '..asm.arch.cris.any_v0_v10'
  6995. This symbol is non-zero when '--march=v0_v10' is specified or the
  6996. default.
  6997. '..asm.arch.cris.common_v10_v32'
  6998. Set according to the option '--march=common_v10_v32'.
  6999. '..asm.arch.cris.v10'
  7000. Reflects the option '--march=v10'.
  7001. '..asm.arch.cris.v32'
  7002. Corresponds to '--march=v10'.
  7003. Speaking of symbols, when a symbol is used in code, it can have a
  7004. suffix modifying its value for use in position-independent code. *Note
  7005. CRIS-Pic::.
  7006. 
  7007. File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent
  7008. 9.8.4 Syntax
  7009. ------------
  7010. There are different aspects of the CRIS assembly syntax.
  7011. * Menu:
  7012. * CRIS-Chars:: Special Characters
  7013. * CRIS-Pic:: Position-Independent Code Symbols
  7014. * CRIS-Regs:: Register Names
  7015. * CRIS-Pseudos:: Assembler Directives
  7016. 
  7017. File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax
  7018. 9.8.4.1 Special Characters
  7019. ..........................
  7020. The character '#' is a line comment character. It starts a comment if
  7021. and only if it is placed at the beginning of a line.
  7022. A ';' character starts a comment anywhere on the line, causing all
  7023. characters up to the end of the line to be ignored.
  7024. A '@' character is handled as a line separator equivalent to a
  7025. logical new-line character (except in a comment), so separate
  7026. instructions can be specified on a single line.
  7027. 
  7028. File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax
  7029. 9.8.4.2 Symbols in position-independent code
  7030. ............................................
  7031. When generating position-independent code (SVR4 PIC) for use in
  7032. cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
  7033. suffixes are used to specify what kind of run-time symbol lookup will be
  7034. used, expressed in the object as different _relocation types_. Usually,
  7035. all absolute symbol values must be located in a table, the _global
  7036. offset table_, leaving the code position-independent; independent of
  7037. values of global symbols and independent of the address of the code.
  7038. The suffix modifies the value of the symbol, into for example an index
  7039. into the global offset table where the real symbol value is entered, or
  7040. a PC-relative value, or a value relative to the start of the global
  7041. offset table. All symbol suffixes start with the character ':' (omitted
  7042. in the list below). Every symbol use in code or a read-only section
  7043. must therefore have a PIC suffix to enable a useful shared library to be
  7044. created. Usually, these constructs must not be used with an additive
  7045. constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is
  7046. allowed. This restriction is checked at link-time, not at
  7047. assembly-time.
  7048. 'GOT'
  7049. Attaching this suffix to a symbol in an instruction causes the
  7050. symbol to be entered into the global offset table. The value is a
  7051. 32-bit index for that symbol into the global offset table. The
  7052. name of the corresponding relocation is 'R_CRIS_32_GOT'. Example:
  7053. 'move.d [$r0+extsym:GOT],$r9'
  7054. 'GOT16'
  7055. Same as for 'GOT', but the value is a 16-bit index into the global
  7056. offset table. The corresponding relocation is 'R_CRIS_16_GOT'.
  7057. Example: 'move.d [$r0+asymbol:GOT16],$r10'
  7058. 'PLT'
  7059. This suffix is used for function symbols. It causes a _procedure
  7060. linkage table_, an array of code stubs, to be created at the time
  7061. the shared object is created or linked against, together with a
  7062. global offset table entry. The value is a pc-relative offset to
  7063. the corresponding stub code in the procedure linkage table. This
  7064. arrangement causes the run-time symbol resolver to be called to
  7065. look up and set the value of the symbol the first time the function
  7066. is called (at latest; depending environment variables). It is only
  7067. safe to leave the symbol unresolved this way if all references are
  7068. function calls. The name of the relocation is
  7069. 'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc'
  7070. 'PLTG'
  7071. Like PLT, but the value is relative to the beginning of the global
  7072. offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example:
  7073. 'move.d fnname:PLTG,$r3'
  7074. 'GOTPLT'
  7075. Similar to 'PLT', but the value of the symbol is a 32-bit index
  7076. into the global offset table. This is somewhat of a mix between
  7077. the effect of the 'GOT' and the 'PLT' suffix; the difference to
  7078. 'GOT' is that there will be a procedure linkage table entry
  7079. created, and that the symbol is assumed to be a function entry and
  7080. will be resolved by the run-time resolver as with 'PLT'. The
  7081. relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr
  7082. [$r0+fnname:GOTPLT]'
  7083. 'GOTPLT16'
  7084. A variant of 'GOTPLT' giving a 16-bit value. Its relocation name
  7085. is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]'
  7086. 'GOTOFF'
  7087. This suffix must only be attached to a local symbol, but may be
  7088. used in an expression adding an offset. The value is the address
  7089. of the symbol relative to the start of the global offset table.
  7090. The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d
  7091. [$r0+localsym:GOTOFF],r3'
  7092. 
  7093. File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax
  7094. 9.8.4.3 Register names
  7095. ......................
  7096. A '$' character may always prefix a general or special register name in
  7097. an instruction operand but is mandatory when the option
  7098. '--no-underscore' is specified or when the '.syntax register_prefix'
  7099. directive is in effect (*note crisnous::). Register names are
  7100. case-insensitive.
  7101. 
  7102. File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax
  7103. 9.8.4.4 Assembler Directives
  7104. ............................
  7105. There are a few CRIS-specific pseudo-directives in addition to the
  7106. generic ones. *Note Pseudo Ops::. Constants emitted by
  7107. pseudo-directives are in little-endian order for CRIS. There is no
  7108. support for floating-point-specific directives for CRIS.
  7109. '.dword EXPRESSIONS'
  7110. The '.dword' directive is a synonym for '.int', expecting zero or
  7111. more EXPRESSIONS, separated by commas. For each expression, a
  7112. 32-bit little-endian constant is emitted.
  7113. '.syntax ARGUMENT'
  7114. The '.syntax' directive takes as ARGUMENT one of the following
  7115. case-sensitive choices.
  7116. 'no_register_prefix'
  7117. The '.syntax no_register_prefix' directive makes a '$'
  7118. character prefix on all registers optional. It overrides a
  7119. previous setting, including the corresponding effect of the
  7120. option '--no-underscore'. If this directive is used when
  7121. ordinary symbols do not have a '_' character prefix, care must
  7122. be taken to avoid ambiguities whether an operand is a register
  7123. or a symbol; using symbols with names the same as general or
  7124. special registers then invoke undefined behavior.
  7125. 'register_prefix'
  7126. This directive makes a '$' character prefix on all registers
  7127. mandatory. It overrides a previous setting, including the
  7128. corresponding effect of the option '--underscore'.
  7129. 'leading_underscore'
  7130. This is an assertion directive, emitting an error if the
  7131. '--no-underscore' option is in effect.
  7132. 'no_leading_underscore'
  7133. This is the opposite of the '.syntax leading_underscore'
  7134. directive and emits an error if the option '--underscore' is
  7135. in effect.
  7136. '.arch ARGUMENT'
  7137. This is an assertion directive, giving an error if the specified
  7138. ARGUMENT is not the same as the specified or default value for the
  7139. '--march=ARCHITECTURE' option (*note march-option::).
  7140. 
  7141. File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies
  7142. 9.9 D10V Dependent Features
  7143. ===========================
  7144. * Menu:
  7145. * D10V-Opts:: D10V Options
  7146. * D10V-Syntax:: Syntax
  7147. * D10V-Float:: Floating Point
  7148. * D10V-Opcodes:: Opcodes
  7149. 
  7150. File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent
  7151. 9.9.1 D10V Options
  7152. ------------------
  7153. The Mitsubishi D10V version of 'as' has a few machine dependent options.
  7154. '-O'
  7155. The D10V can often execute two sub-instructions in parallel. When
  7156. this option is used, 'as' will attempt to optimize its output by
  7157. detecting when instructions can be executed in parallel.
  7158. '--nowarnswap'
  7159. To optimize execution performance, 'as' will sometimes swap the
  7160. order of instructions. Normally this generates a warning. When
  7161. this option is used, no warning will be generated when instructions
  7162. are swapped.
  7163. '--gstabs-packing'
  7164. '--no-gstabs-packing'
  7165. 'as' packs adjacent short instructions into a single packed
  7166. instruction. '--no-gstabs-packing' turns instruction packing off
  7167. if '--gstabs' is specified as well; '--gstabs-packing' (the
  7168. default) turns instruction packing on even when '--gstabs' is
  7169. specified.
  7170. 
  7171. File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent
  7172. 9.9.2 Syntax
  7173. ------------
  7174. The D10V syntax is based on the syntax in Mitsubishi's D10V architecture
  7175. manual. The differences are detailed below.
  7176. * Menu:
  7177. * D10V-Size:: Size Modifiers
  7178. * D10V-Subs:: Sub-Instructions
  7179. * D10V-Chars:: Special Characters
  7180. * D10V-Regs:: Register Names
  7181. * D10V-Addressing:: Addressing Modes
  7182. * D10V-Word:: @WORD Modifier
  7183. 
  7184. File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax
  7185. 9.9.2.1 Size Modifiers
  7186. ......................
  7187. The D10V version of 'as' uses the instruction names in the D10V
  7188. Architecture Manual. However, the names in the manual are sometimes
  7189. ambiguous. There are instruction names that can assemble to a short or
  7190. long form opcode. How does the assembler pick the correct form? 'as'
  7191. will always pick the smallest form if it can. When dealing with a
  7192. symbol that is not defined yet when a line is being assembled, it will
  7193. always use the long form. If you need to force the assembler to use
  7194. either the short or long form of the instruction, you can append either
  7195. '.s' (short) or '.l' (long) to it. For example, if you are writing an
  7196. assembly program and you want to do a branch to a symbol that is defined
  7197. later in your program, you can write 'bra.s foo'. Objdump and GDB will
  7198. always append '.s' or '.l' to instructions which have both short and
  7199. long forms.
  7200. 
  7201. File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax
  7202. 9.9.2.2 Sub-Instructions
  7203. ........................
  7204. The D10V assembler takes as input a series of instructions, either
  7205. one-per-line, or in the special two-per-line format described in the
  7206. next section. Some of these instructions will be short-form or
  7207. sub-instructions. These sub-instructions can be packed into a single
  7208. instruction. The assembler will do this automatically. It will also
  7209. detect when it should not pack instructions. For example, when a label
  7210. is defined, the next instruction will never be packaged with the
  7211. previous one. Whenever a branch and link instruction is called, it will
  7212. not be packaged with the next instruction so the return address will be
  7213. valid. Nops are automatically inserted when necessary.
  7214. If you do not want the assembler automatically making these
  7215. decisions, you can control the packaging and execution type (parallel or
  7216. sequential) with the special execution symbols described in the next
  7217. section.
  7218. 
  7219. File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax
  7220. 9.9.2.3 Special Characters
  7221. ..........................
  7222. A semicolon (';') can be used anywhere on a line to start a comment that
  7223. extends to the end of the line.
  7224. If a '#' appears as the first character of a line, the whole line is
  7225. treated as a comment, but in this case the line could also be a logical
  7226. line number directive (*note Comments::) or a preprocessor control
  7227. command (*note Preprocessing::).
  7228. Sub-instructions may be executed in order, in reverse-order, or in
  7229. parallel. Instructions listed in the standard one-per-line format will
  7230. be executed sequentially. To specify the executing order, use the
  7231. following symbols:
  7232. '->'
  7233. Sequential with instruction on the left first.
  7234. '<-'
  7235. Sequential with instruction on the right first.
  7236. '||'
  7237. Parallel
  7238. The D10V syntax allows either one instruction per line, one
  7239. instruction per line with the execution symbol, or two instructions per
  7240. line. For example
  7241. 'abs a1 -> abs r0'
  7242. Execute these sequentially. The instruction on the right is in the
  7243. right container and is executed second.
  7244. 'abs r0 <- abs a1'
  7245. Execute these reverse-sequentially. The instruction on the right
  7246. is in the right container, and is executed first.
  7247. 'ld2w r2,@r8+ || mac a0,r0,r7'
  7248. Execute these in parallel.
  7249. 'ld2w r2,@r8+ ||'
  7250. 'mac a0,r0,r7'
  7251. Two-line format. Execute these in parallel.
  7252. 'ld2w r2,@r8+'
  7253. 'mac a0,r0,r7'
  7254. Two-line format. Execute these sequentially. Assembler will put
  7255. them in the proper containers.
  7256. 'ld2w r2,@r8+ ->'
  7257. 'mac a0,r0,r7'
  7258. Two-line format. Execute these sequentially. Same as above but
  7259. second instruction will always go into right container.
  7260. Since '$' has no special meaning, you may use it in symbol names.
  7261. 
  7262. File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax
  7263. 9.9.2.4 Register Names
  7264. ......................
  7265. You can use the predefined symbols 'r0' through 'r15' to refer to the
  7266. D10V registers. You can also use 'sp' as an alias for 'r15'. The
  7267. accumulators are 'a0' and 'a1'. There are special register-pair names
  7268. that may optionally be used in opcodes that require even-numbered
  7269. registers. Register names are not case sensitive.
  7270. Register Pairs
  7271. 'r0-r1'
  7272. 'r2-r3'
  7273. 'r4-r5'
  7274. 'r6-r7'
  7275. 'r8-r9'
  7276. 'r10-r11'
  7277. 'r12-r13'
  7278. 'r14-r15'
  7279. The D10V also has predefined symbols for these control registers and
  7280. status bits:
  7281. 'psw'
  7282. Processor Status Word
  7283. 'bpsw'
  7284. Backup Processor Status Word
  7285. 'pc'
  7286. Program Counter
  7287. 'bpc'
  7288. Backup Program Counter
  7289. 'rpt_c'
  7290. Repeat Count
  7291. 'rpt_s'
  7292. Repeat Start address
  7293. 'rpt_e'
  7294. Repeat End address
  7295. 'mod_s'
  7296. Modulo Start address
  7297. 'mod_e'
  7298. Modulo End address
  7299. 'iba'
  7300. Instruction Break Address
  7301. 'f0'
  7302. Flag 0
  7303. 'f1'
  7304. Flag 1
  7305. 'c'
  7306. Carry flag
  7307. 
  7308. File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax
  7309. 9.9.2.5 Addressing Modes
  7310. ........................
  7311. 'as' understands the following addressing modes for the D10V. 'RN' in
  7312. the following refers to any of the numbered registers, but _not_ the
  7313. control registers.
  7314. 'RN'
  7315. Register direct
  7316. '@RN'
  7317. Register indirect
  7318. '@RN+'
  7319. Register indirect with post-increment
  7320. '@RN-'
  7321. Register indirect with post-decrement
  7322. '@-SP'
  7323. Register indirect with pre-decrement
  7324. '@(DISP, RN)'
  7325. Register indirect with displacement
  7326. 'ADDR'
  7327. PC relative address (for branch or rep).
  7328. '#IMM'
  7329. Immediate data (the '#' is optional and ignored)
  7330. 
  7331. File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax
  7332. 9.9.2.6 @WORD Modifier
  7333. ......................
  7334. Any symbol followed by '@word' will be replaced by the symbol's value
  7335. shifted right by 2. This is used in situations such as loading a
  7336. register with the address of a function (or any other code fragment).
  7337. For example, if you want to load a register with the location of the
  7338. function 'main' then jump to that function, you could do it as follows:
  7339. ldi r2, main@word
  7340. jmp r2
  7341. 
  7342. File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent
  7343. 9.9.3 Floating Point
  7344. --------------------
  7345. The D10V has no hardware floating point, but the '.float' and '.double'
  7346. directives generates IEEE floating-point numbers for compatibility with
  7347. other development tools.
  7348. 
  7349. File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent
  7350. 9.9.4 Opcodes
  7351. -------------
  7352. For detailed information on the D10V machine instruction set, see 'D10V
  7353. Architecture: A VLIW Microprocessor for Multimedia Applications'
  7354. (Mitsubishi Electric Corp.). 'as' implements all the standard D10V
  7355. opcodes. The only changes are those described in the section on size
  7356. modifiers
  7357. 
  7358. File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies
  7359. 9.10 D30V Dependent Features
  7360. ============================
  7361. * Menu:
  7362. * D30V-Opts:: D30V Options
  7363. * D30V-Syntax:: Syntax
  7364. * D30V-Float:: Floating Point
  7365. * D30V-Opcodes:: Opcodes
  7366. 
  7367. File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent
  7368. 9.10.1 D30V Options
  7369. -------------------
  7370. The Mitsubishi D30V version of 'as' has a few machine dependent options.
  7371. '-O'
  7372. The D30V can often execute two sub-instructions in parallel. When
  7373. this option is used, 'as' will attempt to optimize its output by
  7374. detecting when instructions can be executed in parallel.
  7375. '-n'
  7376. When this option is used, 'as' will issue a warning every time it
  7377. adds a nop instruction.
  7378. '-N'
  7379. When this option is used, 'as' will issue a warning if it needs to
  7380. insert a nop after a 32-bit multiply before a load or 16-bit
  7381. multiply instruction.
  7382. 
  7383. File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent
  7384. 9.10.2 Syntax
  7385. -------------
  7386. The D30V syntax is based on the syntax in Mitsubishi's D30V architecture
  7387. manual. The differences are detailed below.
  7388. * Menu:
  7389. * D30V-Size:: Size Modifiers
  7390. * D30V-Subs:: Sub-Instructions
  7391. * D30V-Chars:: Special Characters
  7392. * D30V-Guarded:: Guarded Execution
  7393. * D30V-Regs:: Register Names
  7394. * D30V-Addressing:: Addressing Modes
  7395. 
  7396. File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax
  7397. 9.10.2.1 Size Modifiers
  7398. .......................
  7399. The D30V version of 'as' uses the instruction names in the D30V
  7400. Architecture Manual. However, the names in the manual are sometimes
  7401. ambiguous. There are instruction names that can assemble to a short or
  7402. long form opcode. How does the assembler pick the correct form? 'as'
  7403. will always pick the smallest form if it can. When dealing with a
  7404. symbol that is not defined yet when a line is being assembled, it will
  7405. always use the long form. If you need to force the assembler to use
  7406. either the short or long form of the instruction, you can append either
  7407. '.s' (short) or '.l' (long) to it. For example, if you are writing an
  7408. assembly program and you want to do a branch to a symbol that is defined
  7409. later in your program, you can write 'bra.s foo'. Objdump and GDB will
  7410. always append '.s' or '.l' to instructions which have both short and
  7411. long forms.
  7412. 
  7413. File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax
  7414. 9.10.2.2 Sub-Instructions
  7415. .........................
  7416. The D30V assembler takes as input a series of instructions, either
  7417. one-per-line, or in the special two-per-line format described in the
  7418. next section. Some of these instructions will be short-form or
  7419. sub-instructions. These sub-instructions can be packed into a single
  7420. instruction. The assembler will do this automatically. It will also
  7421. detect when it should not pack instructions. For example, when a label
  7422. is defined, the next instruction will never be packaged with the
  7423. previous one. Whenever a branch and link instruction is called, it will
  7424. not be packaged with the next instruction so the return address will be
  7425. valid. Nops are automatically inserted when necessary.
  7426. If you do not want the assembler automatically making these
  7427. decisions, you can control the packaging and execution type (parallel or
  7428. sequential) with the special execution symbols described in the next
  7429. section.
  7430. 
  7431. File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax
  7432. 9.10.2.3 Special Characters
  7433. ...........................
  7434. A semicolon (';') can be used anywhere on a line to start a comment that
  7435. extends to the end of the line.
  7436. If a '#' appears as the first character of a line, the whole line is
  7437. treated as a comment, but in this case the line could also be a logical
  7438. line number directive (*note Comments::) or a preprocessor control
  7439. command (*note Preprocessing::).
  7440. Sub-instructions may be executed in order, in reverse-order, or in
  7441. parallel. Instructions listed in the standard one-per-line format will
  7442. be executed sequentially unless you use the '-O' option.
  7443. To specify the executing order, use the following symbols:
  7444. '->'
  7445. Sequential with instruction on the left first.
  7446. '<-'
  7447. Sequential with instruction on the right first.
  7448. '||'
  7449. Parallel
  7450. The D30V syntax allows either one instruction per line, one
  7451. instruction per line with the execution symbol, or two instructions per
  7452. line. For example
  7453. 'abs r2,r3 -> abs r4,r5'
  7454. Execute these sequentially. The instruction on the right is in the
  7455. right container and is executed second.
  7456. 'abs r2,r3 <- abs r4,r5'
  7457. Execute these reverse-sequentially. The instruction on the right
  7458. is in the right container, and is executed first.
  7459. 'abs r2,r3 || abs r4,r5'
  7460. Execute these in parallel.
  7461. 'ldw r2,@(r3,r4) ||'
  7462. 'mulx r6,r8,r9'
  7463. Two-line format. Execute these in parallel.
  7464. 'mulx a0,r8,r9'
  7465. 'stw r2,@(r3,r4)'
  7466. Two-line format. Execute these sequentially unless '-O' option is
  7467. used. If the '-O' option is used, the assembler will determine if
  7468. the instructions could be done in parallel (the above two
  7469. instructions can be done in parallel), and if so, emit them as
  7470. parallel instructions. The assembler will put them in the proper
  7471. containers. In the above example, the assembler will put the 'stw'
  7472. instruction in left container and the 'mulx' instruction in the
  7473. right container.
  7474. 'stw r2,@(r3,r4) ->'
  7475. 'mulx a0,r8,r9'
  7476. Two-line format. Execute the 'stw' instruction followed by the
  7477. 'mulx' instruction sequentially. The first instruction goes in the
  7478. left container and the second instruction goes into right
  7479. container. The assembler will give an error if the machine
  7480. ordering constraints are violated.
  7481. 'stw r2,@(r3,r4) <-'
  7482. 'mulx a0,r8,r9'
  7483. Same as previous example, except that the 'mulx' instruction is
  7484. executed before the 'stw' instruction.
  7485. Since '$' has no special meaning, you may use it in symbol names.
  7486. 
  7487. File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax
  7488. 9.10.2.4 Guarded Execution
  7489. ..........................
  7490. 'as' supports the full range of guarded execution directives for each
  7491. instruction. Just append the directive after the instruction proper.
  7492. The directives are:
  7493. '/tx'
  7494. Execute the instruction if flag f0 is true.
  7495. '/fx'
  7496. Execute the instruction if flag f0 is false.
  7497. '/xt'
  7498. Execute the instruction if flag f1 is true.
  7499. '/xf'
  7500. Execute the instruction if flag f1 is false.
  7501. '/tt'
  7502. Execute the instruction if both flags f0 and f1 are true.
  7503. '/tf'
  7504. Execute the instruction if flag f0 is true and flag f1 is false.
  7505. 
  7506. File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax
  7507. 9.10.2.5 Register Names
  7508. .......................
  7509. You can use the predefined symbols 'r0' through 'r63' to refer to the
  7510. D30V registers. You can also use 'sp' as an alias for 'r63' and 'link'
  7511. as an alias for 'r62'. The accumulators are 'a0' and 'a1'.
  7512. The D30V also has predefined symbols for these control registers and
  7513. status bits:
  7514. 'psw'
  7515. Processor Status Word
  7516. 'bpsw'
  7517. Backup Processor Status Word
  7518. 'pc'
  7519. Program Counter
  7520. 'bpc'
  7521. Backup Program Counter
  7522. 'rpt_c'
  7523. Repeat Count
  7524. 'rpt_s'
  7525. Repeat Start address
  7526. 'rpt_e'
  7527. Repeat End address
  7528. 'mod_s'
  7529. Modulo Start address
  7530. 'mod_e'
  7531. Modulo End address
  7532. 'iba'
  7533. Instruction Break Address
  7534. 'f0'
  7535. Flag 0
  7536. 'f1'
  7537. Flag 1
  7538. 'f2'
  7539. Flag 2
  7540. 'f3'
  7541. Flag 3
  7542. 'f4'
  7543. Flag 4
  7544. 'f5'
  7545. Flag 5
  7546. 'f6'
  7547. Flag 6
  7548. 'f7'
  7549. Flag 7
  7550. 's'
  7551. Same as flag 4 (saturation flag)
  7552. 'v'
  7553. Same as flag 5 (overflow flag)
  7554. 'va'
  7555. Same as flag 6 (sticky overflow flag)
  7556. 'c'
  7557. Same as flag 7 (carry/borrow flag)
  7558. 'b'
  7559. Same as flag 7 (carry/borrow flag)
  7560. 
  7561. File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax
  7562. 9.10.2.6 Addressing Modes
  7563. .........................
  7564. 'as' understands the following addressing modes for the D30V. 'RN' in
  7565. the following refers to any of the numbered registers, but _not_ the
  7566. control registers.
  7567. 'RN'
  7568. Register direct
  7569. '@RN'
  7570. Register indirect
  7571. '@RN+'
  7572. Register indirect with post-increment
  7573. '@RN-'
  7574. Register indirect with post-decrement
  7575. '@-SP'
  7576. Register indirect with pre-decrement
  7577. '@(DISP, RN)'
  7578. Register indirect with displacement
  7579. 'ADDR'
  7580. PC relative address (for branch or rep).
  7581. '#IMM'
  7582. Immediate data (the '#' is optional and ignored)
  7583. 
  7584. File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent
  7585. 9.10.3 Floating Point
  7586. ---------------------
  7587. The D30V has no hardware floating point, but the '.float' and '.double'
  7588. directives generates IEEE floating-point numbers for compatibility with
  7589. other development tools.
  7590. 
  7591. File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent
  7592. 9.10.4 Opcodes
  7593. --------------
  7594. For detailed information on the D30V machine instruction set, see 'D30V
  7595. Architecture: A VLIW Microprocessor for Multimedia Applications'
  7596. (Mitsubishi Electric Corp.). 'as' implements all the standard D30V
  7597. opcodes. The only changes are those described in the section on size
  7598. modifiers
  7599. 
  7600. File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies
  7601. 9.11 Epiphany Dependent Features
  7602. ================================
  7603. * Menu:
  7604. * Epiphany Options:: Options
  7605. * Epiphany Syntax:: Epiphany Syntax
  7606. 
  7607. File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent
  7608. 9.11.1 Options
  7609. --------------
  7610. 'as' has two additional command-line options for the Epiphany
  7611. architecture.
  7612. '-mepiphany'
  7613. Specifies that the both 32 and 16 bit instructions are allowed.
  7614. This is the default behavior.
  7615. '-mepiphany16'
  7616. Restricts the permitted instructions to just the 16 bit set.
  7617. 
  7618. File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent
  7619. 9.11.2 Epiphany Syntax
  7620. ----------------------
  7621. * Menu:
  7622. * Epiphany-Chars:: Special Characters
  7623. 
  7624. File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax
  7625. 9.11.2.1 Special Characters
  7626. ...........................
  7627. The presence of a ';' on a line indicates the start of a comment that
  7628. extends to the end of the current line.
  7629. If a '#' appears as the first character of a line then the whole line
  7630. is treated as a comment, but in this case the line could also be a
  7631. logical line number directive (*note Comments::) or a preprocessor
  7632. control command (*note Preprocessing::).
  7633. The '`' character can be used to separate statements on the same
  7634. line.
  7635. 
  7636. File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies
  7637. 9.12 H8/300 Dependent Features
  7638. ==============================
  7639. * Menu:
  7640. * H8/300 Options:: Options
  7641. * H8/300 Syntax:: Syntax
  7642. * H8/300 Floating Point:: Floating Point
  7643. * H8/300 Directives:: H8/300 Machine Directives
  7644. * H8/300 Opcodes:: Opcodes
  7645. 
  7646. File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent
  7647. 9.12.1 Options
  7648. --------------
  7649. The Renesas H8/300 version of 'as' has one machine-dependent option:
  7650. '-h-tick-hex'
  7651. Support H'00 style hex constants in addition to 0x00 style.
  7652. '-mach=NAME'
  7653. Sets the H8300 machine variant. The following machine names are
  7654. recognised: 'h8300h', 'h8300hn', 'h8300s', 'h8300sn', 'h8300sx' and
  7655. 'h8300sxn'.
  7656. 
  7657. File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent
  7658. 9.12.2 Syntax
  7659. -------------
  7660. * Menu:
  7661. * H8/300-Chars:: Special Characters
  7662. * H8/300-Regs:: Register Names
  7663. * H8/300-Addressing:: Addressing Modes
  7664. 
  7665. File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax
  7666. 9.12.2.1 Special Characters
  7667. ...........................
  7668. ';' is the line comment character.
  7669. '$' can be used instead of a newline to separate statements.
  7670. Therefore _you may not use '$' in symbol names_ on the H8/300.
  7671. 
  7672. File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax
  7673. 9.12.2.2 Register Names
  7674. .......................
  7675. You can use predefined symbols of the form 'rNh' and 'rNl' to refer to
  7676. the H8/300 registers as sixteen 8-bit general-purpose registers. N is a
  7677. digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid
  7678. register names.
  7679. You can also use the eight predefined symbols 'rN' to refer to the
  7680. H8/300 registers as 16-bit registers (you must use this form for
  7681. addressing).
  7682. On the H8/300H, you can also use the eight predefined symbols 'erN'
  7683. ('er0' ... 'er7') to refer to the 32-bit general purpose registers.
  7684. The two control registers are called 'pc' (program counter; a 16-bit
  7685. register, except on the H8/300H where it is 24 bits) and 'ccr'
  7686. (condition code register; an 8-bit register). 'r7' is used as the stack
  7687. pointer, and can also be called 'sp'.
  7688. 
  7689. File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax
  7690. 9.12.2.3 Addressing Modes
  7691. .........................
  7692. as understands the following addressing modes for the H8/300:
  7693. 'rN'
  7694. Register direct
  7695. '@rN'
  7696. Register indirect
  7697. '@(D, rN)'
  7698. '@(D:16, rN)'
  7699. '@(D:24, rN)'
  7700. Register indirect: 16-bit or 24-bit displacement D from register N.
  7701. (24-bit displacements are only meaningful on the H8/300H.)
  7702. '@rN+'
  7703. Register indirect with post-increment
  7704. '@-rN'
  7705. Register indirect with pre-decrement
  7706. '@AA'
  7707. '@AA:8'
  7708. '@AA:16'
  7709. '@AA:24'
  7710. Absolute address 'aa'. (The address size ':24' only makes sense on
  7711. the H8/300H.)
  7712. '#XX'
  7713. '#XX:8'
  7714. '#XX:16'
  7715. '#XX:32'
  7716. Immediate data XX. You may specify the ':8', ':16', or ':32' for
  7717. clarity, if you wish; but 'as' neither requires this nor uses
  7718. it--the data size required is taken from context.
  7719. '@@AA'
  7720. '@@AA:8'
  7721. Memory indirect. You may specify the ':8' for clarity, if you
  7722. wish; but 'as' neither requires this nor uses it.
  7723. 
  7724. File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent
  7725. 9.12.3 Floating Point
  7726. ---------------------
  7727. The H8/300 family has no hardware floating point, but the '.float'
  7728. directive generates IEEE floating-point numbers for compatibility with
  7729. other development tools.
  7730. 
  7731. File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent
  7732. 9.12.4 H8/300 Machine Directives
  7733. --------------------------------
  7734. 'as' has the following machine-dependent directives for the H8/300:
  7735. '.h8300h'
  7736. Recognize and emit additional instructions for the H8/300H variant,
  7737. and also make '.int' emit 32-bit numbers rather than the usual
  7738. (16-bit) for the H8/300 family.
  7739. '.h8300s'
  7740. Recognize and emit additional instructions for the H8S variant, and
  7741. also make '.int' emit 32-bit numbers rather than the usual (16-bit)
  7742. for the H8/300 family.
  7743. '.h8300hn'
  7744. Recognize and emit additional instructions for the H8/300H variant
  7745. in normal mode, and also make '.int' emit 32-bit numbers rather
  7746. than the usual (16-bit) for the H8/300 family.
  7747. '.h8300sn'
  7748. Recognize and emit additional instructions for the H8S variant in
  7749. normal mode, and also make '.int' emit 32-bit numbers rather than
  7750. the usual (16-bit) for the H8/300 family.
  7751. On the H8/300 family (including the H8/300H) '.word' directives
  7752. generate 16-bit numbers.
  7753. 
  7754. File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent
  7755. 9.12.5 Opcodes
  7756. --------------
  7757. For detailed information on the H8/300 machine instruction set, see
  7758. 'H8/300 Series Programming Manual'. For information specific to the
  7759. H8/300H, see 'H8/300H Series Programming Manual' (Renesas).
  7760. 'as' implements all the standard H8/300 opcodes. No additional
  7761. pseudo-instructions are needed on this family.
  7762. The following table summarizes the H8/300 opcodes, and their
  7763. arguments. Entries marked '*' are opcodes used only on the H8/300H.
  7764. Legend:
  7765. Rs source register
  7766. Rd destination register
  7767. abs absolute address
  7768. imm immediate data
  7769. disp:N N-bit displacement from a register
  7770. pcrel:N N-bit displacement relative to program counter
  7771. add.b #imm,rd * andc #imm,ccr
  7772. add.b rs,rd band #imm,rd
  7773. add.w rs,rd band #imm,@rd
  7774. * add.w #imm,rd band #imm,@abs:8
  7775. * add.l rs,rd bra pcrel:8
  7776. * add.l #imm,rd * bra pcrel:16
  7777. adds #imm,rd bt pcrel:8
  7778. addx #imm,rd * bt pcrel:16
  7779. addx rs,rd brn pcrel:8
  7780. and.b #imm,rd * brn pcrel:16
  7781. and.b rs,rd bf pcrel:8
  7782. * and.w rs,rd * bf pcrel:16
  7783. * and.w #imm,rd bhi pcrel:8
  7784. * and.l #imm,rd * bhi pcrel:16
  7785. * and.l rs,rd bls pcrel:8
  7786. * bls pcrel:16 bld #imm,rd
  7787. bcc pcrel:8 bld #imm,@rd
  7788. * bcc pcrel:16 bld #imm,@abs:8
  7789. bhs pcrel:8 bnot #imm,rd
  7790. * bhs pcrel:16 bnot #imm,@rd
  7791. bcs pcrel:8 bnot #imm,@abs:8
  7792. * bcs pcrel:16 bnot rs,rd
  7793. blo pcrel:8 bnot rs,@rd
  7794. * blo pcrel:16 bnot rs,@abs:8
  7795. bne pcrel:8 bor #imm,rd
  7796. * bne pcrel:16 bor #imm,@rd
  7797. beq pcrel:8 bor #imm,@abs:8
  7798. * beq pcrel:16 bset #imm,rd
  7799. bvc pcrel:8 bset #imm,@rd
  7800. * bvc pcrel:16 bset #imm,@abs:8
  7801. bvs pcrel:8 bset rs,rd
  7802. * bvs pcrel:16 bset rs,@rd
  7803. bpl pcrel:8 bset rs,@abs:8
  7804. * bpl pcrel:16 bsr pcrel:8
  7805. bmi pcrel:8 bsr pcrel:16
  7806. * bmi pcrel:16 bst #imm,rd
  7807. bge pcrel:8 bst #imm,@rd
  7808. * bge pcrel:16 bst #imm,@abs:8
  7809. blt pcrel:8 btst #imm,rd
  7810. * blt pcrel:16 btst #imm,@rd
  7811. bgt pcrel:8 btst #imm,@abs:8
  7812. * bgt pcrel:16 btst rs,rd
  7813. ble pcrel:8 btst rs,@rd
  7814. * ble pcrel:16 btst rs,@abs:8
  7815. bclr #imm,rd bxor #imm,rd
  7816. bclr #imm,@rd bxor #imm,@rd
  7817. bclr #imm,@abs:8 bxor #imm,@abs:8
  7818. bclr rs,rd cmp.b #imm,rd
  7819. bclr rs,@rd cmp.b rs,rd
  7820. bclr rs,@abs:8 cmp.w rs,rd
  7821. biand #imm,rd cmp.w rs,rd
  7822. biand #imm,@rd * cmp.w #imm,rd
  7823. biand #imm,@abs:8 * cmp.l #imm,rd
  7824. bild #imm,rd * cmp.l rs,rd
  7825. bild #imm,@rd daa rs
  7826. bild #imm,@abs:8 das rs
  7827. bior #imm,rd dec.b rs
  7828. bior #imm,@rd * dec.w #imm,rd
  7829. bior #imm,@abs:8 * dec.l #imm,rd
  7830. bist #imm,rd divxu.b rs,rd
  7831. bist #imm,@rd * divxu.w rs,rd
  7832. bist #imm,@abs:8 * divxs.b rs,rd
  7833. bixor #imm,rd * divxs.w rs,rd
  7834. bixor #imm,@rd eepmov
  7835. bixor #imm,@abs:8 * eepmovw
  7836. * exts.w rd mov.w rs,@abs:16
  7837. * exts.l rd * mov.l #imm,rd
  7838. * extu.w rd * mov.l rs,rd
  7839. * extu.l rd * mov.l @rs,rd
  7840. inc rs * mov.l @(disp:16,rs),rd
  7841. * inc.w #imm,rd * mov.l @(disp:24,rs),rd
  7842. * inc.l #imm,rd * mov.l @rs+,rd
  7843. jmp @rs * mov.l @abs:16,rd
  7844. jmp abs * mov.l @abs:24,rd
  7845. jmp @@abs:8 * mov.l rs,@rd
  7846. jsr @rs * mov.l rs,@(disp:16,rd)
  7847. jsr abs * mov.l rs,@(disp:24,rd)
  7848. jsr @@abs:8 * mov.l rs,@-rd
  7849. ldc #imm,ccr * mov.l rs,@abs:16
  7850. ldc rs,ccr * mov.l rs,@abs:24
  7851. * ldc @abs:16,ccr movfpe @abs:16,rd
  7852. * ldc @abs:24,ccr movtpe rs,@abs:16
  7853. * ldc @(disp:16,rs),ccr mulxu.b rs,rd
  7854. * ldc @(disp:24,rs),ccr * mulxu.w rs,rd
  7855. * ldc @rs+,ccr * mulxs.b rs,rd
  7856. * ldc @rs,ccr * mulxs.w rs,rd
  7857. * mov.b @(disp:24,rs),rd neg.b rs
  7858. * mov.b rs,@(disp:24,rd) * neg.w rs
  7859. mov.b @abs:16,rd * neg.l rs
  7860. mov.b rs,rd nop
  7861. mov.b @abs:8,rd not.b rs
  7862. mov.b rs,@abs:8 * not.w rs
  7863. mov.b rs,rd * not.l rs
  7864. mov.b #imm,rd or.b #imm,rd
  7865. mov.b @rs,rd or.b rs,rd
  7866. mov.b @(disp:16,rs),rd * or.w #imm,rd
  7867. mov.b @rs+,rd * or.w rs,rd
  7868. mov.b @abs:8,rd * or.l #imm,rd
  7869. mov.b rs,@rd * or.l rs,rd
  7870. mov.b rs,@(disp:16,rd) orc #imm,ccr
  7871. mov.b rs,@-rd pop.w rs
  7872. mov.b rs,@abs:8 * pop.l rs
  7873. mov.w rs,@rd push.w rs
  7874. * mov.w @(disp:24,rs),rd * push.l rs
  7875. * mov.w rs,@(disp:24,rd) rotl.b rs
  7876. * mov.w @abs:24,rd * rotl.w rs
  7877. * mov.w rs,@abs:24 * rotl.l rs
  7878. mov.w rs,rd rotr.b rs
  7879. mov.w #imm,rd * rotr.w rs
  7880. mov.w @rs,rd * rotr.l rs
  7881. mov.w @(disp:16,rs),rd rotxl.b rs
  7882. mov.w @rs+,rd * rotxl.w rs
  7883. mov.w @abs:16,rd * rotxl.l rs
  7884. mov.w rs,@(disp:16,rd) rotxr.b rs
  7885. mov.w rs,@-rd * rotxr.w rs
  7886. * rotxr.l rs * stc ccr,@(disp:24,rd)
  7887. bpt * stc ccr,@-rd
  7888. rte * stc ccr,@abs:16
  7889. rts * stc ccr,@abs:24
  7890. shal.b rs sub.b rs,rd
  7891. * shal.w rs sub.w rs,rd
  7892. * shal.l rs * sub.w #imm,rd
  7893. shar.b rs * sub.l rs,rd
  7894. * shar.w rs * sub.l #imm,rd
  7895. * shar.l rs subs #imm,rd
  7896. shll.b rs subx #imm,rd
  7897. * shll.w rs subx rs,rd
  7898. * shll.l rs * trapa #imm
  7899. shlr.b rs xor #imm,rd
  7900. * shlr.w rs xor rs,rd
  7901. * shlr.l rs * xor.w #imm,rd
  7902. sleep * xor.w rs,rd
  7903. stc ccr,rd * xor.l #imm,rd
  7904. * stc ccr,@rs * xor.l rs,rd
  7905. * stc ccr,@(disp:16,rd) xorc #imm,ccr
  7906. Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined
  7907. with variants using the suffixes '.b', '.w', and '.l' to specify the
  7908. size of a memory operand. 'as' supports these suffixes, but does not
  7909. require them; since one of the operands is always a register, 'as' can
  7910. deduce the correct size.
  7911. For example, since 'r0' refers to a 16-bit register,
  7912. mov r0,@foo
  7913. is equivalent to
  7914. mov.w r0,@foo
  7915. If you use the size suffixes, 'as' issues a warning when the suffix
  7916. and the register size do not match.
  7917. 
  7918. File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies
  7919. 9.13 HPPA Dependent Features
  7920. ============================
  7921. * Menu:
  7922. * HPPA Notes:: Notes
  7923. * HPPA Options:: Options
  7924. * HPPA Syntax:: Syntax
  7925. * HPPA Floating Point:: Floating Point
  7926. * HPPA Directives:: HPPA Machine Directives
  7927. * HPPA Opcodes:: Opcodes
  7928. 
  7929. File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent
  7930. 9.13.1 Notes
  7931. ------------
  7932. As a back end for GNU CC 'as' has been throughly tested and should work
  7933. extremely well. We have tested it only minimally on hand written
  7934. assembly code and no one has tested it much on the assembly output from
  7935. the HP compilers.
  7936. The format of the debugging sections has changed since the original
  7937. 'as' port (version 1.3X) was released; therefore, you must rebuild all
  7938. HPPA objects and libraries with the new assembler so that you can debug
  7939. the final executable.
  7940. The HPPA 'as' port generates a small subset of the relocations
  7941. available in the SOM and ELF object file formats. Additional relocation
  7942. support will be added as it becomes necessary.
  7943. 
  7944. File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent
  7945. 9.13.2 Options
  7946. --------------
  7947. 'as' has no machine-dependent command-line options for the HPPA.
  7948. 
  7949. File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
  7950. 9.13.3 Syntax
  7951. -------------
  7952. The assembler syntax closely follows the HPPA instruction set reference
  7953. manual; assembler directives and general syntax closely follow the HPPA
  7954. assembly language reference manual, with a few noteworthy differences.
  7955. First, a colon may immediately follow a label definition. This is
  7956. simply for compatibility with how most assembly language programmers
  7957. write code.
  7958. Some obscure expression parsing problems may affect hand written code
  7959. which uses the 'spop' instructions, or code which makes significant use
  7960. of the '!' line separator.
  7961. 'as' is much less forgiving about missing arguments and other similar
  7962. oversights than the HP assembler. 'as' notifies you of missing
  7963. arguments as syntax errors; this is regarded as a feature, not a bug.
  7964. Finally, 'as' allows you to use an external symbol without explicitly
  7965. importing the symbol. _Warning:_ in the future this will be an error
  7966. for HPPA targets.
  7967. Special characters for HPPA targets include:
  7968. ';' is the line comment character.
  7969. '!' can be used instead of a newline to separate statements.
  7970. Since '$' has no special meaning, you may use it in symbol names.
  7971. 
  7972. File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
  7973. 9.13.4 Floating Point
  7974. ---------------------
  7975. The HPPA family uses IEEE floating-point numbers.
  7976. 
  7977. File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
  7978. 9.13.5 HPPA Assembler Directives
  7979. --------------------------------
  7980. 'as' for the HPPA supports many additional directives for compatibility
  7981. with the native assembler. This section describes them only briefly.
  7982. For detailed information on HPPA-specific assembler directives, see
  7983. 'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
  7984. 'as' does _not_ support the following assembler directives described
  7985. in the HP manual:
  7986. .endm .liston
  7987. .enter .locct
  7988. .leave .macro
  7989. .listoff
  7990. Beyond those implemented for compatibility, 'as' supports one
  7991. additional assembler directive for the HPPA: '.param'. It conveys
  7992. register argument locations for static functions. Its syntax closely
  7993. follows the '.export' directive.
  7994. These are the additional directives in 'as' for the HPPA:
  7995. '.block N'
  7996. '.blockz N'
  7997. Reserve N bytes of storage, and initialize them to zero.
  7998. '.call'
  7999. Mark the beginning of a procedure call. Only the special case with
  8000. _no arguments_ is allowed.
  8001. '.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]'
  8002. Specify a number of parameters and flags that define the
  8003. environment for a procedure.
  8004. PARAM may be any of 'frame' (frame size), 'entry_gr' (end of
  8005. general register range), 'entry_fr' (end of float register range),
  8006. 'entry_sr' (end of space register range).
  8007. The values for FLAG are 'calls' or 'caller' (proc has subroutines),
  8008. 'no_calls' (proc does not call subroutines), 'save_rp' (preserve
  8009. return pointer), 'save_sp' (proc preserves stack pointer),
  8010. 'no_unwind' (do not unwind this proc), 'hpux_int' (proc is
  8011. interrupt routine).
  8012. '.code'
  8013. Assemble into the standard section called '$TEXT$', subsection
  8014. '$CODE$'.
  8015. '.copyright "STRING"'
  8016. In the SOM object format, insert STRING into the object code,
  8017. marked as a copyright string.
  8018. '.copyright "STRING"'
  8019. In the ELF object format, insert STRING into the object code,
  8020. marked as a version string.
  8021. '.enter'
  8022. Not yet supported; the assembler rejects programs containing this
  8023. directive.
  8024. '.entry'
  8025. Mark the beginning of a procedure.
  8026. '.exit'
  8027. Mark the end of a procedure.
  8028. '.export NAME [ ,TYP ] [ ,PARAM=R ]'
  8029. Make a procedure NAME available to callers. TYP, if present, must
  8030. be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry',
  8031. 'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'.
  8032. PARAM, if present, provides either relocation information for the
  8033. procedure arguments and result, or a privilege level. PARAM may be
  8034. 'argwN' (where N ranges from '0' to '3', and indicates one of four
  8035. one-word arguments); 'rtnval' (the procedure's result); or
  8036. 'priv_lev' (privilege level). For arguments or the result, R
  8037. specifies how to relocate, and must be one of 'no' (not
  8038. relocatable), 'gr' (argument is in general register), 'fr' (in
  8039. floating point register), or 'fu' (upper half of float register).
  8040. For 'priv_lev', R is an integer.
  8041. '.half N'
  8042. Define a two-byte integer constant N; synonym for the portable 'as'
  8043. directive '.short'.
  8044. '.import NAME [ ,TYP ]'
  8045. Converse of '.export'; make a procedure available to call. The
  8046. arguments use the same conventions as the first two arguments for
  8047. '.export'.
  8048. '.label NAME'
  8049. Define NAME as a label for the current assembly location.
  8050. '.leave'
  8051. Not yet supported; the assembler rejects programs containing this
  8052. directive.
  8053. '.origin LC'
  8054. Advance location counter to LC. Synonym for the 'as' portable
  8055. directive '.org'.
  8056. '.param NAME [ ,TYP ] [ ,PARAM=R ]'
  8057. Similar to '.export', but used for static procedures.
  8058. '.proc'
  8059. Use preceding the first statement of a procedure.
  8060. '.procend'
  8061. Use following the last statement of a procedure.
  8062. 'LABEL .reg EXPR'
  8063. Synonym for '.equ'; define LABEL with the absolute expression EXPR
  8064. as its value.
  8065. '.space SECNAME [ ,PARAMS ]'
  8066. Switch to section SECNAME, creating a new section by that name if
  8067. necessary. You may only use PARAMS when creating a new section,
  8068. not when switching to an existing one. SECNAME may identify a
  8069. section by number rather than by name.
  8070. If specified, the list PARAMS declares attributes of the section,
  8071. identified by keywords. The keywords recognized are 'spnum=EXP'
  8072. (identify this section by the number EXP, an absolute expression),
  8073. 'sort=EXP' (order sections according to this sort key when linking;
  8074. EXP is an absolute expression), 'unloadable' (section contains no
  8075. loadable data), 'notdefined' (this section defined elsewhere), and
  8076. 'private' (data in this section not available to other programs).
  8077. '.spnum SECNAM'
  8078. Allocate four bytes of storage, and initialize them with the
  8079. section number of the section named SECNAM. (You can define the
  8080. section number with the HPPA '.space' directive.)
  8081. '.string "STR"'
  8082. Copy the characters in the string STR to the object file. *Note
  8083. Strings: Strings, for information on escape sequences you can use
  8084. in 'as' strings.
  8085. _Warning!_ The HPPA version of '.string' differs from the usual
  8086. 'as' definition: it does _not_ write a zero byte after copying STR.
  8087. '.stringz "STR"'
  8088. Like '.string', but appends a zero byte after copying STR to object
  8089. file.
  8090. '.subspa NAME [ ,PARAMS ]'
  8091. '.nsubspa NAME [ ,PARAMS ]'
  8092. Similar to '.space', but selects a subsection NAME within the
  8093. current section. You may only specify PARAMS when you create a
  8094. subsection (in the first instance of '.subspa' for this NAME).
  8095. If specified, the list PARAMS declares attributes of the
  8096. subsection, identified by keywords. The keywords recognized are
  8097. 'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR'
  8098. (alignment for beginning of this subsection; a power of two),
  8099. 'access=EXPR' (value for "access rights" field), 'sort=EXPR'
  8100. (sorting order for this subspace in link), 'code_only' (subsection
  8101. contains only code), 'unloadable' (subsection cannot be loaded into
  8102. memory), 'comdat' (subsection is comdat), 'common' (subsection is
  8103. common block), 'dup_comm' (subsection may have duplicate names), or
  8104. 'zero' (subsection is all zeros, do not write in object file).
  8105. '.nsubspa' always creates a new subspace with the given name, even
  8106. if one with the same name already exists.
  8107. 'comdat', 'common' and 'dup_comm' can be used to implement various
  8108. flavors of one-only support when using the SOM linker. The SOM
  8109. linker only supports specific combinations of these flags. The
  8110. details are not documented. A brief description is provided here.
  8111. 'comdat' provides a form of linkonce support. It is useful for
  8112. both code and data subspaces. A 'comdat' subspace has a key symbol
  8113. marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first
  8114. subspace for any given key is selected. The key symbol becomes
  8115. universal in shared links. This is similar to the behavior of
  8116. 'secondary_def' symbols.
  8117. 'common' provides Fortran named common support. It is only useful
  8118. for data subspaces. Symbols with the flag 'is_common' retain this
  8119. flag in shared links. Referencing a 'is_common' symbol in a shared
  8120. library from outside the library doesn't work. Thus, 'is_common'
  8121. symbols must be output whenever they are needed.
  8122. 'common' and 'dup_comm' together provide Cobol common support. The
  8123. subspaces in this case must all be the same length. Otherwise,
  8124. this support is similar to the Fortran common support.
  8125. 'dup_comm' by itself provides a type of one-only support for code.
  8126. Only the first 'dup_comm' subspace is selected. There is a rather
  8127. complex algorithm to compare subspaces. Code symbols marked with
  8128. the 'dup_common' flag are hidden. This support was intended for
  8129. "C++ duplicate inlines".
  8130. A simplified technique is used to mark the flags of symbols based
  8131. on the flags of their subspace. A symbol with the scope
  8132. SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
  8133. the corresponding settings of 'comdat', 'common' and 'dup_comm'
  8134. from the subspace, respectively. This avoids having to introduce
  8135. additional directives to mark these symbols. The HP assembler sets
  8136. 'is_common' from 'common'. However, it doesn't set the
  8137. 'dup_common' from 'dup_comm'. It doesn't have 'comdat' support.
  8138. '.version "STR"'
  8139. Write STR as version identifier in object code.
  8140. 
  8141. File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
  8142. 9.13.6 Opcodes
  8143. --------------
  8144. For detailed information on the HPPA machine instruction set, see
  8145. 'PA-RISC Architecture and Instruction Set Reference Manual' (HP
  8146. 09740-90039).
  8147. 
  8148. File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
  8149. 9.14 ESA/390 Dependent Features
  8150. ===============================
  8151. * Menu:
  8152. * ESA/390 Notes:: Notes
  8153. * ESA/390 Options:: Options
  8154. * ESA/390 Syntax:: Syntax
  8155. * ESA/390 Floating Point:: Floating Point
  8156. * ESA/390 Directives:: ESA/390 Machine Directives
  8157. * ESA/390 Opcodes:: Opcodes
  8158. 
  8159. File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
  8160. 9.14.1 Notes
  8161. ------------
  8162. The ESA/390 'as' port is currently intended to be a back-end for the GNU
  8163. CC compiler. It is not HLASM compatible, although it does support a
  8164. subset of some of the HLASM directives. The only supported binary file
  8165. format is ELF; none of the usual MVS/VM/OE/USS object file formats, such
  8166. as ESD or XSD, are supported.
  8167. When used with the GNU CC compiler, the ESA/390 'as' will produce
  8168. correct, fully relocated, functional binaries, and has been used to
  8169. compile and execute large projects. However, many aspects should still
  8170. be considered experimental; these include shared library support,
  8171. dynamically loadable objects, and any relocation other than the 31-bit
  8172. relocation.
  8173. 
  8174. File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
  8175. 9.14.2 Options
  8176. --------------
  8177. 'as' has no machine-dependent command-line options for the ESA/390.
  8178. 
  8179. File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
  8180. 9.14.3 Syntax
  8181. -------------
  8182. The opcode/operand syntax follows the ESA/390 Principles of Operation
  8183. manual; assembler directives and general syntax are loosely based on the
  8184. prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
  8185. are _not_ supported for the most part, with the exception of those
  8186. described herein.
  8187. A leading dot in front of directives is optional, and the case of
  8188. directives is ignored; thus for example, .using and USING have the same
  8189. effect.
  8190. A colon may immediately follow a label definition. This is simply
  8191. for compatibility with how most assembly language programmers write
  8192. code.
  8193. '#' is the line comment character.
  8194. ';' can be used instead of a newline to separate statements.
  8195. Since '$' has no special meaning, you may use it in symbol names.
  8196. Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
  8197. fp6. By using thesse symbolic names, 'as' can detect simple syntax
  8198. errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
  8199. r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
  8200. for r3 and rpgt or r.pgt for r4.
  8201. '*' is the current location counter. Unlike '.' it is always
  8202. relative to the last USING directive. Note that this means that
  8203. expressions cannot use multiplication, as any occurrence of '*' will be
  8204. interpreted as a location counter.
  8205. All labels are relative to the last USING. Thus, branches to a label
  8206. always imply the use of base+displacement.
  8207. Many of the usual forms of address constants / address literals are
  8208. supported. Thus,
  8209. .using *,r3
  8210. L r15,=A(some_routine)
  8211. LM r6,r7,=V(some_longlong_extern)
  8212. A r1,=F'12'
  8213. AH r0,=H'42'
  8214. ME r6,=E'3.1416'
  8215. MD r6,=D'3.14159265358979'
  8216. O r6,=XL4'cacad0d0'
  8217. .ltorg
  8218. should all behave as expected: that is, an entry in the literal pool
  8219. will be created (or reused if it already exists), and the instruction
  8220. operands will be the displacement into the literal pool using the
  8221. current base register (as last declared with the '.using' directive).
  8222. 
  8223. File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
  8224. 9.14.4 Floating Point
  8225. ---------------------
  8226. The assembler generates only IEEE floating-point numbers. The older
  8227. floating point formats are not supported.
  8228. 
  8229. File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
  8230. 9.14.5 ESA/390 Assembler Directives
  8231. -----------------------------------
  8232. 'as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
  8233. directives that are documented in the main part of this documentation.
  8234. Several additional directives are supported in order to implement the
  8235. ESA/390 addressing model. The most important of these are '.using' and
  8236. '.ltorg'
  8237. These are the additional directives in 'as' for the ESA/390:
  8238. '.dc'
  8239. A small subset of the usual DC directive is supported.
  8240. '.drop REGNO'
  8241. Stop using REGNO as the base register. The REGNO must have been
  8242. previously declared with a '.using' directive in the same section
  8243. as the current section.
  8244. '.ebcdic STRING'
  8245. Emit the EBCDIC equivalent of the indicated string. The emitted
  8246. string will be null terminated. Note that the directives '.string'
  8247. etc. emit ascii strings by default.
  8248. 'EQU'
  8249. The standard HLASM-style EQU directive is not supported; however,
  8250. the standard 'as' directive .equ can be used to the same effect.
  8251. '.ltorg'
  8252. Dump the literal pool accumulated so far; begin a new literal pool.
  8253. The literal pool will be written in the current section; in order
  8254. to generate correct assembly, a '.using' must have been previously
  8255. specified in the same section.
  8256. '.using EXPR,REGNO'
  8257. Use REGNO as the base register for all subsequent RX, RS, and SS
  8258. form instructions. The EXPR will be evaluated to obtain the base
  8259. address; usually, EXPR will merely be '*'.
  8260. This assembler allows two '.using' directives to be simultaneously
  8261. outstanding, one in the '.text' section, and one in another section
  8262. (typically, the '.data' section). This feature allows dynamically
  8263. loaded objects to be implemented in a relatively straightforward
  8264. way. A '.using' directive must always be specified in the '.text'
  8265. section; this will specify the base register that will be used for
  8266. branches in the '.text' section. A second '.using' may be
  8267. specified in another section; this will specify the base register
  8268. that is used for non-label address literals. When a second
  8269. '.using' is specified, then the subsequent '.ltorg' must be put in
  8270. the same section; otherwise an error will result.
  8271. Thus, for example, the following code uses 'r3' to address branch
  8272. targets and 'r4' to address the literal pool, which has been
  8273. written to the '.data' section. The is, the constants
  8274. '=A(some_routine)', '=H'42'' and '=E'3.1416'' will all appear in
  8275. the '.data' section.
  8276. .data
  8277. .using LITPOOL,r4
  8278. .text
  8279. BASR r3,0
  8280. .using *,r3
  8281. B START
  8282. .long LITPOOL
  8283. START:
  8284. L r4,4(,r3)
  8285. L r15,=A(some_routine)
  8286. LTR r15,r15
  8287. BNE LABEL
  8288. AH r0,=H'42'
  8289. LABEL:
  8290. ME r6,=E'3.1416'
  8291. .data
  8292. LITPOOL:
  8293. .ltorg
  8294. Note that this dual-'.using' directive semantics extends and is not
  8295. compatible with HLASM semantics. Note that this assembler
  8296. directive does not support the full range of HLASM semantics.
  8297. 
  8298. File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
  8299. 9.14.6 Opcodes
  8300. --------------
  8301. For detailed information on the ESA/390 machine instruction set, see
  8302. 'ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
  8303. 
  8304. File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
  8305. 9.15 80386 Dependent Features
  8306. =============================
  8307. The i386 version 'as' supports both the original Intel 386 architecture
  8308. in both 16 and 32-bit mode as well as AMD x86-64 architecture extending
  8309. the Intel architecture to 64-bits.
  8310. * Menu:
  8311. * i386-Options:: Options
  8312. * i386-Directives:: X86 specific directives
  8313. * i386-Syntax:: Syntactical considerations
  8314. * i386-Mnemonics:: Instruction Naming
  8315. * i386-Regs:: Register Naming
  8316. * i386-Prefixes:: Instruction Prefixes
  8317. * i386-Memory:: Memory References
  8318. * i386-Jumps:: Handling of Jump Instructions
  8319. * i386-Float:: Floating Point
  8320. * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
  8321. * i386-LWP:: AMD's Lightweight Profiling Instructions
  8322. * i386-BMI:: Bit Manipulation Instruction
  8323. * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
  8324. * i386-16bit:: Writing 16-bit Code
  8325. * i386-Arch:: Specifying an x86 CPU architecture
  8326. * i386-Bugs:: AT&T Syntax bugs
  8327. * i386-Notes:: Notes
  8328. 
  8329. File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent
  8330. 9.15.1 Options
  8331. --------------
  8332. The i386 version of 'as' has a few machine dependent options:
  8333. '--32 | --x32 | --64'
  8334. Select the word size, either 32 bits or 64 bits. '--32' implies
  8335. Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64
  8336. architecture with 32-bit or 64-bit word-size respectively.
  8337. These options are only available with the ELF object file format,
  8338. and require that the necessary BFD support has been included (on a
  8339. 32-bit platform you have to add -enable-64-bit-bfd to configure
  8340. enable 64-bit usage and use x86-64 as target platform).
  8341. '-n'
  8342. By default, x86 GAS replaces multiple nop instructions used for
  8343. alignment within code sections with multi-byte nop instructions
  8344. such as leal 0(%esi,1),%esi. This switch disables the
  8345. optimization.
  8346. '--divide'
  8347. On SVR4-derived platforms, the character '/' is treated as a
  8348. comment character, which means that it cannot be used in
  8349. expressions. The '--divide' option turns '/' into a normal
  8350. character. This does not disable '/' at the beginning of a line
  8351. starting a comment, or affect using '#' for starting a comment.
  8352. '-march=CPU[+EXTENSION...]'
  8353. This option specifies the target processor. The assembler will
  8354. issue an error message if an attempt is made to assemble an
  8355. instruction which will not execute on the target processor. The
  8356. following processor names are recognized: 'i8086', 'i186', 'i286',
  8357. 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro',
  8358. 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona',
  8359. 'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2',
  8360. 'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2',
  8361. 'bdver3', 'bdver4', 'znver1', 'btver1', 'btver2', 'generic32' and
  8362. 'generic64'.
  8363. In addition to the basic instruction set, the assembler can be told
  8364. to accept various extension mnemonics. For example,
  8365. '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
  8366. following extensions are currently supported: '8087', '287', '387',
  8367. '687', 'no87', 'no287', 'no387', 'no687', 'mmx', 'nommx', 'sse',
  8368. 'sse2', 'sse3', 'ssse3', 'sse4.1', 'sse4.2', 'sse4', 'nosse',
  8369. 'nosse2', 'nosse3', 'nossse3', 'nosse4.1', 'nosse4.2', 'nosse4',
  8370. 'avx', 'avx2', 'noavx', 'noavx2', 'adx', 'rdseed', 'prfchw',
  8371. 'smap', 'mpx', 'sha', 'rdpid', 'ptwrite', 'prefetchwt1',
  8372. 'clflushopt', 'se1', 'clwb', 'avx512f', 'avx512cd', 'avx512er',
  8373. 'avx512pf', 'avx512vl', 'avx512bw', 'avx512dq', 'avx512ifma',
  8374. 'avx512vbmi', 'avx512_4fmaps', 'avx512_4vnniw', 'avx512_vpopcntdq',
  8375. 'noavx512f', 'noavx512cd', 'noavx512er', 'noavx512pf',
  8376. 'noavx512vl', 'noavx512bw', 'noavx512dq', 'noavx512ifma',
  8377. 'noavx512vbmi', 'noavx512_4fmaps', 'noavx512_4vnniw',
  8378. 'noavx512_vpopcntdq', 'vmx', 'vmfunc', 'smx', 'xsave', 'xsaveopt',
  8379. 'xsavec', 'xsaves', 'aes', 'pclmul', 'fsgsbase', 'rdrnd', 'f16c',
  8380. 'bmi2', 'fma', 'movbe', 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid',
  8381. 'clflush', 'mwaitx', 'clzero', 'lwp', 'fma4', 'xop', 'cx16',
  8382. 'syscall', 'rdtscp', '3dnow', '3dnowa', 'sse4a', 'sse5', 'svme',
  8383. 'abm' and 'padlock'. Note that rather than extending a basic
  8384. instruction set, the extension mnemonics starting with 'no' revoke
  8385. the respective functionality.
  8386. When the '.arch' directive is used with '-march', the '.arch'
  8387. directive will take precedent.
  8388. '-mtune=CPU'
  8389. This option specifies a processor to optimize for. When used in
  8390. conjunction with the '-march' option, only instructions of the
  8391. processor specified by the '-march' option will be generated.
  8392. Valid CPU values are identical to the processor list of
  8393. '-march=CPU'.
  8394. '-msse2avx'
  8395. This option specifies that the assembler should encode SSE
  8396. instructions with VEX prefix.
  8397. '-msse-check=NONE'
  8398. '-msse-check=WARNING'
  8399. '-msse-check=ERROR'
  8400. These options control if the assembler should check SSE
  8401. instructions. '-msse-check=NONE' will make the assembler not to
  8402. check SSE instructions, which is the default.
  8403. '-msse-check=WARNING' will make the assembler issue a warning for
  8404. any SSE instruction. '-msse-check=ERROR' will make the assembler
  8405. issue an error for any SSE instruction.
  8406. '-mavxscalar=128'
  8407. '-mavxscalar=256'
  8408. These options control how the assembler should encode scalar AVX
  8409. instructions. '-mavxscalar=128' will encode scalar AVX
  8410. instructions with 128bit vector length, which is the default.
  8411. '-mavxscalar=256' will encode scalar AVX instructions with 256bit
  8412. vector length.
  8413. '-mevexlig=128'
  8414. '-mevexlig=256'
  8415. '-mevexlig=512'
  8416. These options control how the assembler should encode
  8417. length-ignored (LIG) EVEX instructions. '-mevexlig=128' will
  8418. encode LIG EVEX instructions with 128bit vector length, which is
  8419. the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG
  8420. EVEX instructions with 256bit and 512bit vector length,
  8421. respectively.
  8422. '-mevexwig=0'
  8423. '-mevexwig=1'
  8424. These options control how the assembler should encode w-ignored
  8425. (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX
  8426. instructions with evex.w = 0, which is the default. '-mevexwig=1'
  8427. will encode WIG EVEX instructions with evex.w = 1.
  8428. '-mmnemonic=ATT'
  8429. '-mmnemonic=INTEL'
  8430. This option specifies instruction mnemonic for matching
  8431. instructions. The '.att_mnemonic' and '.intel_mnemonic' directives
  8432. will take precedent.
  8433. '-msyntax=ATT'
  8434. '-msyntax=INTEL'
  8435. This option specifies instruction syntax when processing
  8436. instructions. The '.att_syntax' and '.intel_syntax' directives
  8437. will take precedent.
  8438. '-mnaked-reg'
  8439. This opetion specifies that registers don't require a '%' prefix.
  8440. The '.att_syntax' and '.intel_syntax' directives will take
  8441. precedent.
  8442. '-madd-bnd-prefix'
  8443. This option forces the assembler to add BND prefix to all branches,
  8444. even if such prefix was not explicitly specified in the source
  8445. code.
  8446. '-mno-shared'
  8447. On ELF target, the assembler normally optimizes out non-PLT
  8448. relocations against defined non-weak global branch targets with
  8449. default visibility. The '-mshared' option tells the assembler to
  8450. generate code which may go into a shared library where all non-weak
  8451. global branch targets with default visibility can be preempted.
  8452. The resulting code is slightly bigger. This option only affects
  8453. the handling of branch instructions.
  8454. '-mbig-obj'
  8455. On x86-64 PE/COFF target this option forces the use of big object
  8456. file format, which allows more than 32768 sections.
  8457. '-momit-lock-prefix=NO'
  8458. '-momit-lock-prefix=YES'
  8459. These options control how the assembler should encode lock prefix.
  8460. This option is intended as a workaround for processors, that fail
  8461. on lock prefix. This option can only be safely used with
  8462. single-core, single-thread computers '-momit-lock-prefix=YES' will
  8463. omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock
  8464. prefix as usual, which is the default.
  8465. '-mfence-as-lock-add=NO'
  8466. '-mfence-as-lock-add=YES'
  8467. These options control how the assembler should encode lfence,
  8468. mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence,
  8469. mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and
  8470. 'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO'
  8471. will encode lfence, mfence and sfence as usual, which is the
  8472. default.
  8473. '-mrelax-relocations=NO'
  8474. '-mrelax-relocations=YES'
  8475. These options control whether the assembler should generate relax
  8476. relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
  8477. and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
  8478. '-mrelax-relocations=YES' will generate relax relocations.
  8479. '-mrelax-relocations=NO' will not generate relax relocations. The
  8480. default can be controlled by a configure option
  8481. '--enable-x86-relax-relocations'.
  8482. '-mevexrcig=RNE'
  8483. '-mevexrcig=RD'
  8484. '-mevexrcig=RU'
  8485. '-mevexrcig=RZ'
  8486. These options control how the assembler should encode SAE-only EVEX
  8487. instructions. '-mevexrcig=RNE' will encode RC bits of EVEX
  8488. instruction with 00, which is the default. '-mevexrcig=RD',
  8489. '-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX
  8490. instructions with 01, 10 and 11 RC bits, respectively.
  8491. '-mamd64'
  8492. '-mintel64'
  8493. This option specifies that the assembler should accept only AMD64
  8494. or Intel64 ISA in 64-bit mode. The default is to accept both.
  8495. 
  8496. File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent
  8497. 9.15.2 x86 specific Directives
  8498. ------------------------------
  8499. '.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
  8500. Reserve LENGTH (an absolute expression) bytes for a local common
  8501. denoted by SYMBOL. The section and value of SYMBOL are those of
  8502. the new local common. The addresses are allocated in the bss
  8503. section, so that at run-time the bytes start off zeroed. Since
  8504. SYMBOL is not declared global, it is normally not visible to 'ld'.
  8505. The optional third parameter, ALIGNMENT, specifies the desired
  8506. alignment of the symbol in the bss section.
  8507. This directive is only available for COFF based x86 targets.
  8508. 
  8509. File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent
  8510. 9.15.3 i386 Syntactical Considerations
  8511. --------------------------------------
  8512. * Menu:
  8513. * i386-Variations:: AT&T Syntax versus Intel Syntax
  8514. * i386-Chars:: Special Characters
  8515. 
  8516. File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax
  8517. 9.15.3.1 AT&T Syntax versus Intel Syntax
  8518. ........................................
  8519. 'as' now supports assembly using Intel assembler syntax.
  8520. '.intel_syntax' selects Intel mode, and '.att_syntax' switches back to
  8521. the usual AT&T mode for compatibility with the output of 'gcc'. Either
  8522. of these directives may have an optional argument, 'prefix', or
  8523. 'noprefix' specifying whether registers require a '%' prefix. AT&T
  8524. System V/386 assembler syntax is quite different from Intel syntax. We
  8525. mention these differences because almost all 80386 documents use Intel
  8526. syntax. Notable differences between the two syntaxes are:
  8527. * AT&T immediate operands are preceded by '$'; Intel immediate
  8528. operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T
  8529. register operands are preceded by '%'; Intel register operands are
  8530. undelimited. AT&T absolute (as opposed to PC relative) jump/call
  8531. operands are prefixed by '*'; they are undelimited in Intel syntax.
  8532. * AT&T and Intel syntax use the opposite order for source and
  8533. destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The
  8534. 'source, dest' convention is maintained for compatibility with
  8535. previous Unix assemblers. Note that 'bound', 'invlpga', and
  8536. instructions with 2 immediate operands, such as the 'enter'
  8537. instruction, do _not_ have reversed order. *note i386-Bugs::.
  8538. * In AT&T syntax the size of memory operands is determined from the
  8539. last character of the instruction mnemonic. Mnemonic suffixes of
  8540. 'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long
  8541. (32-bit) and quadruple word (64-bit) memory references. Intel
  8542. syntax accomplishes this by prefixing memory operands (_not_ the
  8543. instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr' and
  8544. 'qword ptr'. Thus, Intel 'mov al, byte ptr FOO' is 'movb FOO, %al'
  8545. in AT&T syntax.
  8546. In 64-bit code, 'movabs' can be used to encode the 'mov'
  8547. instruction with the 64-bit displacement or immediate operand.
  8548. * Immediate form long jumps and calls are 'lcall/ljmp $SECTION,
  8549. $OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far
  8550. SECTION:OFFSET'. Also, the far return instruction is 'lret
  8551. $STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far
  8552. STACK-ADJUST'.
  8553. * The AT&T assembler does not provide support for multiple section
  8554. programs. Unix style systems expect all programs to be single
  8555. sections.
  8556. 
  8557. File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax
  8558. 9.15.3.2 Special Characters
  8559. ...........................
  8560. The presence of a '#' appearing anywhere on a line indicates the start
  8561. of a comment that extends to the end of that line.
  8562. If a '#' appears as the first character of a line then the whole line
  8563. is treated as a comment, but in this case the line can also be a logical
  8564. line number directive (*note Comments::) or a preprocessor control
  8565. command (*note Preprocessing::).
  8566. If the '--divide' command line option has not been specified then the
  8567. '/' character appearing anywhere on a line also introduces a line
  8568. comment.
  8569. The ';' character can be used to separate statements on the same
  8570. line.
  8571. 
  8572. File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
  8573. 9.15.4 i386-Mnemonics
  8574. ---------------------
  8575. 9.15.4.1 Instruction Naming
  8576. ...........................
  8577. Instruction mnemonics are suffixed with one character modifiers which
  8578. specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify
  8579. byte, word, long and quadruple word operands. If no suffix is specified
  8580. by an instruction then 'as' tries to fill in the missing suffix based on
  8581. the destination register operand (the last one by convention). Thus,
  8582. 'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is
  8583. equivalent to 'movw $1, bx'. Note that this is incompatible with the
  8584. AT&T Unix assembler which assumes that a missing mnemonic suffix implies
  8585. long operand size. (This incompatibility does not affect compiler
  8586. output since compilers always explicitly specify the mnemonic suffix.)
  8587. Almost all instructions have the same names in AT&T and Intel format.
  8588. There are a few exceptions. The sign extend and zero extend
  8589. instructions need two sizes to specify them. They need a size to
  8590. sign/zero extend _from_ and a size to zero extend _to_. This is
  8591. accomplished by using two instruction mnemonic suffixes in AT&T syntax.
  8592. Base names for sign extend and zero extend are 'movs...' and 'movz...'
  8593. in AT&T syntax ('movsx' and 'movzx' in Intel syntax). The instruction
  8594. mnemonic suffixes are tacked on to this base name, the _from_ suffix
  8595. before the _to_ suffix. Thus, 'movsbl %al, %edx' is AT&T syntax for
  8596. "move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are
  8597. 'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to
  8598. long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple
  8599. word), and 'lq' (from long to quadruple word).
  8600. Different encoding options can be specified via optional mnemonic
  8601. suffix. '.s' suffix swaps 2 register operands in encoding when moving
  8602. from one register to another. '.d8' or '.d32' suffix prefers 8bit or
  8603. 32bit displacement in encoding.
  8604. The Intel-syntax conversion instructions
  8605. * 'cbw' -- sign-extend byte in '%al' to word in '%ax',
  8606. * 'cwde' -- sign-extend word in '%ax' to long in '%eax',
  8607. * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax',
  8608. * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax',
  8609. * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64
  8610. only),
  8611. * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax'
  8612. (x86-64 only),
  8613. are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T
  8614. naming. 'as' accepts either naming for these instructions.
  8615. Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but
  8616. are 'call far' and 'jump far' in Intel convention.
  8617. 9.15.4.2 AT&T Mnemonic versus Intel Mnemonic
  8618. ............................................
  8619. 'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects
  8620. Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to
  8621. the usual AT&T mnemonic with AT&T syntax for compatibility with the
  8622. output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp',
  8623. 'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are
  8624. implemented in AT&T System V/386 assembler with different mnemonics from
  8625. those in Intel IA32 specification. 'gcc' generates those instructions
  8626. with AT&T mnemonic.
  8627. 
  8628. File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
  8629. 9.15.5 Register Naming
  8630. ----------------------
  8631. Register operands are always prefixed with '%'. The 80386 registers
  8632. consist of
  8633. * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx',
  8634. '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the
  8635. stack pointer).
  8636. * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di',
  8637. '%si', '%bp', and '%sp'.
  8638. * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl',
  8639. '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax',
  8640. '%bx', '%cx', and '%dx')
  8641. * the 6 section registers '%cs' (code section), '%ds' (data section),
  8642. '%ss' (stack section), '%es', '%fs', and '%gs'.
  8643. * the 5 processor control registers '%cr0', '%cr2', '%cr3', '%cr4',
  8644. and '%cr8'.
  8645. * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and
  8646. '%db7'.
  8647. * the 2 test registers '%tr6' and '%tr7'.
  8648. * the 8 floating point register stack '%st' or equivalently '%st(0)',
  8649. '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and
  8650. '%st(7)'. These registers are overloaded by 8 MMX registers
  8651. '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'.
  8652. * the 8 128-bit SSE registers registers '%xmm0', '%xmm1', '%xmm2',
  8653. '%xmm3', '%xmm4', '%xmm5', '%xmm6' and '%xmm7'.
  8654. The AMD x86-64 architecture extends the register set by:
  8655. * enhancing the 8 32-bit registers to 64-bit: '%rax' (the
  8656. accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the
  8657. frame pointer), '%rsp' (the stack pointer)
  8658. * the 8 extended registers '%r8'-'%r15'.
  8659. * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'.
  8660. * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'.
  8661. * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'.
  8662. * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'.
  8663. * the 8 debug registers: '%db8'-'%db15'.
  8664. * the 8 128-bit SSE registers: '%xmm8'-'%xmm15'.
  8665. With the AVX extensions more registers were made available:
  8666. * the 16 256-bit SSE '%ymm0'-'%ymm15' (only the first 8 available in
  8667. 32-bit mode). The bottom 128 bits are overlaid with the
  8668. 'xmm0'-'xmm15' registers.
  8669. The AVX2 extensions made in 64-bit mode more registers available:
  8670. * the 16 128-bit registers '%xmm16'-'%xmm31' and the 16 256-bit
  8671. registers '%ymm16'-'%ymm31'.
  8672. The AVX512 extensions added the following registers:
  8673. * the 32 512-bit registers '%zmm0'-'%zmm31' (only the first 8
  8674. available in 32-bit mode). The bottom 128 bits are overlaid with
  8675. the '%xmm0'-'%xmm31' registers and the first 256 bits are overlaid
  8676. with the '%ymm0'-'%ymm31' registers.
  8677. * the 8 mask registers '%k0'-'%k7'.
  8678. 
  8679. File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
  8680. 9.15.6 Instruction Prefixes
  8681. ---------------------------
  8682. Instruction prefixes are used to modify the following instruction. They
  8683. are used to repeat string instructions, to provide section overrides, to
  8684. perform bus lock operations, and to change operand and address sizes.
  8685. (Most instructions that normally operate on 32-bit operands will use
  8686. 16-bit operands if the instruction has an "operand size" prefix.)
  8687. Instruction prefixes are best written on the same line as the
  8688. instruction they act upon. For example, the 'scas' (scan string)
  8689. instruction is repeated with:
  8690. repne scas %es:(%edi),%al
  8691. You may also place prefixes on the lines immediately preceding the
  8692. instruction, but this circumvents checks that 'as' does with prefixes,
  8693. and will not work with all prefixes.
  8694. Here is a list of instruction prefixes:
  8695. * Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'.
  8696. These are automatically added by specifying using the
  8697. SECTION:MEMORY-OPERAND form for memory references.
  8698. * Operand/Address size prefixes 'data16' and 'addr16' change 32-bit
  8699. operands/addresses into 16-bit operands/addresses, while 'data32'
  8700. and 'addr32' change 16-bit ones (in a '.code16' section) into
  8701. 32-bit operands/addresses. These prefixes _must_ appear on the
  8702. same line of code as the instruction they modify. For example, in
  8703. a 16-bit '.code16' section, you might write:
  8704. addr32 jmpl *(%ebx)
  8705. * The bus lock prefix 'lock' inhibits interrupts during execution of
  8706. the instruction it precedes. (This is only valid with certain
  8707. instructions; see a 80386 manual for details).
  8708. * The wait for coprocessor prefix 'wait' waits for the coprocessor to
  8709. complete the current instruction. This should never be needed for
  8710. the 80386/80387 combination.
  8711. * The 'rep', 'repe', and 'repne' prefixes are added to string
  8712. instructions to make them repeat '%ecx' times ('%cx' times if the
  8713. current address size is 16-bits).
  8714. * The 'rex' family of prefixes is used by x86-64 to encode extensions
  8715. to i386 instruction set. The 'rex' prefix has four bits -- an
  8716. operand size overwrite ('64') used to change operand size from
  8717. 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
  8718. register set.
  8719. You may write the 'rex' prefixes directly. The 'rex64xyz'
  8720. instruction emits 'rex' prefix with all the bits set. By omitting
  8721. the '64', 'x', 'y' or 'z' you may write other prefixes as well.
  8722. Normally, there is no need to write the prefixes explicitly, since
  8723. gas will automatically generate them based on the instruction
  8724. operands.
  8725. 
  8726. File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
  8727. 9.15.7 Memory References
  8728. ------------------------
  8729. An Intel syntax indirect memory reference of the form
  8730. SECTION:[BASE + INDEX*SCALE + DISP]
  8731. is translated into the AT&T syntax
  8732. SECTION:DISP(BASE, INDEX, SCALE)
  8733. where BASE and INDEX are the optional 32-bit base and index registers,
  8734. DISP is the optional displacement, and SCALE, taking the values 1, 2, 4,
  8735. and 8, multiplies INDEX to calculate the address of the operand. If no
  8736. SCALE is specified, SCALE is taken to be 1. SECTION specifies the
  8737. optional section register for the memory operand, and may override the
  8738. default section register (see a 80386 manual for section register
  8739. defaults). Note that section overrides in AT&T syntax _must_ be
  8740. preceded by a '%'. If you specify a section override which coincides
  8741. with the default section register, 'as' does _not_ output any section
  8742. register override prefixes to assemble the given instruction. Thus,
  8743. section overrides can be specified to emphasize which section register
  8744. is used for a given memory operand.
  8745. Here are some examples of Intel and AT&T style memory references:
  8746. AT&T: '-4(%ebp)', Intel: '[ebp - 4]'
  8747. BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default
  8748. section is used ('%ss' for addressing with '%ebp' as the base
  8749. register). INDEX, SCALE are both missing.
  8750. AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]'
  8751. INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other
  8752. fields are missing. The section register here defaults to '%ds'.
  8753. AT&T: 'foo(,1)'; Intel '[foo]'
  8754. This uses the value pointed to by 'foo' as a memory operand. Note
  8755. that BASE and INDEX are both missing, but there is only _one_ ','.
  8756. This is a syntactic exception.
  8757. AT&T: '%gs:foo'; Intel 'gs:foo'
  8758. This selects the contents of the variable 'foo' with section
  8759. register SECTION being '%gs'.
  8760. Absolute (as opposed to PC relative) call and jump operands must be
  8761. prefixed with '*'. If no '*' is specified, 'as' always chooses PC
  8762. relative addressing for jump/call labels.
  8763. Any instruction that has a memory operand, but no register operand,
  8764. _must_ specify its size (byte, word, long, or quadruple) with an
  8765. instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively).
  8766. The x86-64 architecture adds an RIP (instruction pointer relative)
  8767. addressing. This addressing mode is specified by using 'rip' as a base
  8768. register. Only constant offsets are valid. For example:
  8769. AT&T: '1234(%rip)', Intel: '[rip + 1234]'
  8770. Points to the address 1234 bytes past the end of the current
  8771. instruction.
  8772. AT&T: 'symbol(%rip)', Intel: '[rip + symbol]'
  8773. Points to the 'symbol' in RIP relative way, this is shorter than
  8774. the default absolute addressing.
  8775. Other addressing modes remain unchanged in x86-64 architecture,
  8776. except registers used are 64-bit instead of 32-bit.
  8777. 
  8778. File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
  8779. 9.15.8 Handling of Jump Instructions
  8780. ------------------------------------
  8781. Jump instructions are always optimized to use the smallest possible
  8782. displacements. This is accomplished by using byte (8-bit) displacement
  8783. jumps whenever the target is sufficiently close. If a byte displacement
  8784. is insufficient a long displacement is used. We do not support word
  8785. (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
  8786. instruction with the 'data16' instruction prefix), since the 80386
  8787. insists upon masking '%eip' to 16 bits after the word displacement is
  8788. added. (See also *note i386-Arch::)
  8789. Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and
  8790. 'loopne' instructions only come in byte displacements, so that if you
  8791. use these instructions ('gcc' does not use them) you may get an error
  8792. message (and incorrect code). The AT&T 80386 assembler tries to get
  8793. around this problem by expanding 'jcxz foo' to
  8794. jcxz cx_zero
  8795. jmp cx_nonzero
  8796. cx_zero: jmp foo
  8797. cx_nonzero:
  8798. 
  8799. File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
  8800. 9.15.9 Floating Point
  8801. ---------------------
  8802. All 80387 floating point types except packed BCD are supported. (BCD
  8803. support may be added without much difficulty). These data types are
  8804. 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
  8805. and extended (80-bit) precision floating point. Each supported type has
  8806. an instruction mnemonic suffix and a constructor associated with it.
  8807. Instruction mnemonic suffixes specify the operand's data type.
  8808. Constructors build these data types into memory.
  8809. * Floating point constructors are '.float' or '.single', '.double',
  8810. and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond
  8811. to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for
  8812. 80-bit (ten byte) real. The 80387 only supports this format via
  8813. the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store
  8814. 80-bit real and pop stack) instructions.
  8815. * Integer constructors are '.word', '.long' or '.int', and '.quad'
  8816. for the 16-, 32-, and 64-bit integer formats. The corresponding
  8817. instruction mnemonic suffixes are 's' (single), 'l' (long), and 'q'
  8818. (quad). As with the 80-bit real format, the 64-bit 'q' format is
  8819. only present in the 'fildq' (load quad integer to stack top) and
  8820. 'fistpq' (store quad integer and pop stack) instructions.
  8821. Register to register operations should not use instruction mnemonic
  8822. suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as
  8823. if you wrote 'fst %st, %st(1)', since all register to register
  8824. operations use 80-bit floating point operands. (Contrast this with
  8825. 'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating
  8826. point format, then stores the result in the 4 byte location 'mem')
  8827. 
  8828. File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent
  8829. 9.15.10 Intel's MMX and AMD's 3DNow! SIMD Operations
  8830. ----------------------------------------------------
  8831. 'as' supports Intel's MMX instruction set (SIMD instructions for integer
  8832. data), available on Intel's Pentium MMX processors and Pentium II
  8833. processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
  8834. probably others. It also supports AMD's 3DNow! instruction set (SIMD
  8835. instructions for 32-bit floating point data) available on AMD's K6-2
  8836. processor and possibly others in the future.
  8837. Currently, 'as' does not support Intel's floating point SIMD, Katmai
  8838. (KNI).
  8839. The eight 64-bit MMX operands, also used by 3DNow!, are called
  8840. '%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four
  8841. 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
  8842. floating point values. The MMX registers cannot be used at the same
  8843. time as the floating point stack.
  8844. See Intel and AMD documentation, keeping in mind that the operand
  8845. order in instructions is reversed from the Intel syntax.
  8846. 
  8847. File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent
  8848. 9.15.11 AMD's Lightweight Profiling Instructions
  8849. ------------------------------------------------
  8850. 'as' supports AMD's Lightweight Profiling (LWP) instruction set,
  8851. available on AMD's Family 15h (Orochi) processors.
  8852. LWP enables applications to collect and manage performance data, and
  8853. react to performance events. The collection of performance data
  8854. requires no context switches. LWP runs in the context of a thread and
  8855. so several counters can be used independently across multiple threads.
  8856. LWP can be used in both 64-bit and legacy 32-bit modes.
  8857. For detailed information on the LWP instruction set, see the 'AMD
  8858. Lightweight Profiling Specification' available at Lightweight Profiling
  8859. Specification (http://developer.amd.com/cpu/LWP).
  8860. 
  8861. File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent
  8862. 9.15.12 Bit Manipulation Instructions
  8863. -------------------------------------
  8864. 'as' supports the Bit Manipulation (BMI) instruction set.
  8865. BMI instructions provide several instructions implementing individual
  8866. bit manipulation operations such as isolation, masking, setting, or
  8867. resetting.
  8868. 
  8869. File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent
  8870. 9.15.13 AMD's Trailing Bit Manipulation Instructions
  8871. ----------------------------------------------------
  8872. 'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set,
  8873. available on AMD's BDVER2 processors (Trinity and Viperfish).
  8874. TBM instructions provide instructions implementing individual bit
  8875. manipulation operations such as isolating, masking, setting, resetting,
  8876. complementing, and operations on trailing zeros and ones.
  8877. 
  8878. File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent
  8879. 9.15.14 Writing 16-bit Code
  8880. ---------------------------
  8881. While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64
  8882. code depending on the default configuration, it also supports writing
  8883. code to run in real mode or in 16-bit protected mode code segments. To
  8884. do this, put a '.code16' or '.code16gcc' directive before the assembly
  8885. language instructions to be run in 16-bit mode. You can switch 'as' to
  8886. writing 32-bit code with the '.code32' directive or 64-bit code with the
  8887. '.code64' directive.
  8888. '.code16gcc' provides experimental support for generating 16-bit code
  8889. from gcc, and differs from '.code16' in that 'call', 'ret', 'enter',
  8890. 'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf'
  8891. instructions default to 32-bit size. This is so that the stack pointer
  8892. is manipulated in the same way over function calls, allowing access to
  8893. function parameters at the same stack offsets as in 32-bit mode.
  8894. '.code16gcc' also automatically adds address size prefixes where
  8895. necessary to use the 32-bit addressing modes that gcc generates.
  8896. The code which 'as' generates in 16-bit mode will not necessarily run
  8897. on a 16-bit pre-80386 processor. To write code that runs on such a
  8898. processor, you must refrain from using _any_ 32-bit constructs which
  8899. require 'as' to output address or operand size prefixes.
  8900. Note that writing 16-bit code instructions by explicitly specifying a
  8901. prefix or an instruction mnemonic suffix within a 32-bit code section
  8902. generates different machine instructions than those generated for a
  8903. 16-bit code segment. In a 32-bit code section, the following code
  8904. generates the machine opcode bytes '66 6a 04', which pushes the value
  8905. '4' onto the stack, decrementing '%esp' by 2.
  8906. pushw $4
  8907. The same code in a 16-bit code section would generate the machine
  8908. opcode bytes '6a 04' (i.e., without the operand size prefix), which is
  8909. correct since the processor default operand size is assumed to be 16
  8910. bits in a 16-bit code section.
  8911. 
  8912. File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent
  8913. 9.15.15 Specifying CPU Architecture
  8914. -----------------------------------
  8915. 'as' may be told to assemble for a particular CPU (sub-)architecture
  8916. with the '.arch CPU_TYPE' directive. This directive enables a warning
  8917. when gas detects an instruction that is not supported on the CPU
  8918. specified. The choices for CPU_TYPE are:
  8919. 'i8086' 'i186' 'i286' 'i386'
  8920. 'i486' 'i586' 'i686' 'pentium'
  8921. 'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4'
  8922. 'prescott' 'nocona' 'core' 'core2'
  8923. 'corei7' 'l1om' 'k1om'
  8924. 'iamcu'
  8925. 'k6' 'k6_2' 'athlon' 'k8'
  8926. 'amdfam10' 'bdver1' 'bdver2' 'bdver3'
  8927. 'bdver4' 'znver1' 'btver1' 'btver2'
  8928. 'generic32' 'generic64'
  8929. '.mmx' '.sse' '.sse2' '.sse3'
  8930. '.ssse3' '.sse4.1' '.sse4.2' '.sse4'
  8931. '.avx' '.vmx' '.smx' '.ept'
  8932. '.clflush' '.movbe' '.xsave' '.xsaveopt'
  8933. '.aes' '.pclmul' '.fma' '.fsgsbase'
  8934. '.rdrnd' '.f16c' '.avx2' '.bmi2'
  8935. '.lzcnt' '.invpcid' '.vmfunc' '.hle'
  8936. '.rtm' '.adx' '.rdseed' '.prfchw'
  8937. '.smap' '.mpx' '.sha' '.prefetchwt1'
  8938. '.clflushopt' '.xsavec' '.xsaves' '.se1'
  8939. '.avx512f' '.avx512cd' '.avx512er' '.avx512pf'
  8940. '.avx512vl' '.avx512bw' '.avx512dq' '.avx512ifma'
  8941. '.avx512vbmi' '.avx512_4fmaps''.avx512_4vnniw'
  8942. '.avx512_vpopcntdq''.clwb' '.rdpid' '.ptwrite'
  8943. '.3dnow' '.3dnowa' '.sse4a' '.sse5'
  8944. '.syscall' '.rdtscp' '.svme' '.abm'
  8945. '.lwp' '.fma4' '.xop' '.cx16'
  8946. '.padlock' '.clzero' '.mwaitx'
  8947. Apart from the warning, there are only two other effects on 'as'
  8948. operation; Firstly, if you specify a CPU other than 'i486', then shift
  8949. by one instructions such as 'sarl $1, %eax' will automatically use a two
  8950. byte opcode sequence. The larger three byte opcode sequence is used on
  8951. the 486 (and when no architecture is specified) because it executes
  8952. faster on the 486. Note that you can explicitly request the two byte
  8953. opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086',
  8954. 'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset
  8955. conditional jumps will be promoted when necessary to a two instruction
  8956. sequence consisting of a conditional jump of the opposite sense around
  8957. an unconditional jump to the target.
  8958. Following the CPU architecture (but not a sub-architecture, which are
  8959. those starting with a dot), you may specify 'jumps' or 'nojumps' to
  8960. control automatic promotion of conditional jumps. 'jumps' is the
  8961. default, and enables jump promotion; All external jumps will be of the
  8962. long variety, and file-local jumps will be promoted as necessary.
  8963. (*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte
  8964. offset jumps, and warns about file-local conditional jumps that 'as'
  8965. promotes. Unconditional jumps are treated as for 'jumps'.
  8966. For example
  8967. .arch i8086,nojumps
  8968. 
  8969. File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
  8970. 9.15.16 AT&T Syntax bugs
  8971. ------------------------
  8972. The UnixWare assembler, and probably other AT&T derived ix86 Unix
  8973. assemblers, generate floating point instructions with reversed source
  8974. and destination registers in certain cases. Unfortunately, gcc and
  8975. possibly many other programs use this reversed syntax, so we're stuck
  8976. with it.
  8977. For example
  8978. fsub %st,%st(3)
  8979. results in '%st(3)' being updated to '%st - %st(3)' rather than the
  8980. expected '%st(3) - %st'. This happens with all the non-commutative
  8981. arithmetic floating point operations with two register operands where
  8982. the source register is '%st' and the destination register is '%st(i)'.
  8983. 
  8984. File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
  8985. 9.15.17 Notes
  8986. -------------
  8987. There is some trickery concerning the 'mul' and 'imul' instructions that
  8988. deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies
  8989. (base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be
  8990. output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_
  8991. select the expanding multiply; the expanding multiply would clobber the
  8992. '%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx'
  8993. to get the 64-bit product in '%edx:%eax'.
  8994. We have added a two operand form of 'imul' when the first operand is
  8995. an immediate mode expression and the second operand is a register. This
  8996. is just a shorthand, so that, multiplying '%eax' by 69, for example, can
  8997. be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'.
  8998. 
  8999. File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
  9000. 9.16 Intel i860 Dependent Features
  9001. ==================================
  9002. * Menu:
  9003. * Notes-i860:: i860 Notes
  9004. * Options-i860:: i860 Command-line Options
  9005. * Directives-i860:: i860 Machine Directives
  9006. * Opcodes for i860:: i860 Opcodes
  9007. * Syntax of i860:: i860 Syntax
  9008. 
  9009. File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
  9010. 9.16.1 i860 Notes
  9011. -----------------
  9012. This is a fairly complete i860 assembler which is compatible with the
  9013. UNIX System V/860 Release 4 assembler. However, it does not currently
  9014. support SVR4 PIC (i.e., '@GOT, @GOTOFF, @PLT').
  9015. Like the SVR4/860 assembler, the output object format is ELF32.
  9016. Currently, this is the only supported object format. If there is
  9017. sufficient interest, other formats such as COFF may be implemented.
  9018. Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
  9019. being the default. One difference is that AT&T syntax requires the '%'
  9020. prefix on register names while Intel syntax does not. Another
  9021. difference is in the specification of relocatable expressions. The
  9022. Intel syntax is 'ha%expression' whereas the SVR4 syntax is
  9023. '[expression]@ha' (and similarly for the "l" and "h" selectors).
  9024. 
  9025. File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
  9026. 9.16.2 i860 Command-line Options
  9027. --------------------------------
  9028. 9.16.2.1 SVR4 compatibility options
  9029. ...................................
  9030. '-V'
  9031. Print assembler version.
  9032. '-Qy'
  9033. Ignored.
  9034. '-Qn'
  9035. Ignored.
  9036. 9.16.2.2 Other options
  9037. ......................
  9038. '-EL'
  9039. Select little endian output (this is the default).
  9040. '-EB'
  9041. Select big endian output. Note that the i860 always reads
  9042. instructions as little endian data, so this option only effects
  9043. data and not instructions.
  9044. '-mwarn-expand'
  9045. Emit a warning message if any pseudo-instruction expansions
  9046. occurred. For example, a 'or' instruction with an immediate larger
  9047. than 16-bits will be expanded into two instructions. This is a
  9048. very undesirable feature to rely on, so this flag can help detect
  9049. any code where it happens. One use of it, for instance, has been
  9050. to find and eliminate any place where 'gcc' may emit these
  9051. pseudo-instructions.
  9052. '-mxp'
  9053. Enable support for the i860XP instructions and control registers.
  9054. By default, this option is disabled so that only the base
  9055. instruction set (i.e., i860XR) is supported.
  9056. '-mintel-syntax'
  9057. The i860 assembler defaults to AT&T/SVR4 syntax. This option
  9058. enables the Intel syntax.
  9059. 
  9060. File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
  9061. 9.16.3 i860 Machine Directives
  9062. ------------------------------
  9063. '.dual'
  9064. Enter dual instruction mode. While this directive is supported,
  9065. the preferred way to use dual instruction mode is to explicitly
  9066. code the dual bit with the 'd.' prefix.
  9067. '.enddual'
  9068. Exit dual instruction mode. While this directive is supported, the
  9069. preferred way to use dual instruction mode is to explicitly code
  9070. the dual bit with the 'd.' prefix.
  9071. '.atmp'
  9072. Change the temporary register used when expanding pseudo
  9073. operations. The default register is 'r31'.
  9074. The '.dual', '.enddual', and '.atmp' directives are available only in
  9075. the Intel syntax mode.
  9076. Both syntaxes allow for the standard '.align' directive. However,
  9077. the Intel syntax additionally allows keywords for the alignment
  9078. parameter: "'.align type'", where 'type' is one of '.short', '.long',
  9079. '.quad', '.single', '.double' representing alignments of 2, 4, 16, 4,
  9080. and 8, respectively.
  9081. 
  9082. File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent
  9083. 9.16.4 i860 Opcodes
  9084. -------------------
  9085. All of the Intel i860XR and i860XP machine instructions are supported.
  9086. Please see either _i860 Microprocessor Programmer's Reference Manual_ or
  9087. _i860 Microprocessor Architecture_ for more information.
  9088. 9.16.4.1 Other instruction support (pseudo-instructions)
  9089. ........................................................
  9090. For compatibility with some other i860 assemblers, a number of
  9091. pseudo-instructions are supported. While these are supported, they are
  9092. a very undesirable feature that should be avoided - in particular, when
  9093. they result in an expansion to multiple actual i860 instructions. Below
  9094. are the pseudo-instructions that result in expansions.
  9095. * Load large immediate into general register:
  9096. The pseudo-instruction 'mov imm,%rn' (where the immediate does not
  9097. fit within a signed 16-bit field) will be expanded into:
  9098. orh large_imm@h,%r0,%rn
  9099. or large_imm@l,%rn,%rn
  9100. * Load/store with relocatable address expression:
  9101. For example, the pseudo-instruction 'ld.b addr_exp(%rx),%rn' will
  9102. be expanded into:
  9103. orh addr_exp@ha,%rx,%r31
  9104. ld.l addr_exp@l(%r31),%rn
  9105. The analogous expansions apply to 'ld.x, st.x, fld.x, pfld.x,
  9106. fst.x', and 'pst.x' as well.
  9107. * Signed large immediate with add/subtract:
  9108. If any of the arithmetic operations 'adds, addu, subs, subu' are
  9109. used with an immediate larger than 16-bits (signed), then they will
  9110. be expanded. For instance, the pseudo-instruction 'adds
  9111. large_imm,%rx,%rn' expands to:
  9112. orh large_imm@h,%r0,%r31
  9113. or large_imm@l,%r31,%r31
  9114. adds %r31,%rx,%rn
  9115. * Unsigned large immediate with logical operations:
  9116. Logical operations ('or, andnot, or, xor') also result in
  9117. expansions. The pseudo-instruction 'or large_imm,%rx,%rn' results
  9118. in:
  9119. orh large_imm@h,%rx,%r31
  9120. or large_imm@l,%r31,%rn
  9121. Similarly for the others, except for 'and' which expands to:
  9122. andnot (-1 - large_imm)@h,%rx,%r31
  9123. andnot (-1 - large_imm)@l,%r31,%rn
  9124. 
  9125. File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent
  9126. 9.16.5 i860 Syntax
  9127. ------------------
  9128. * Menu:
  9129. * i860-Chars:: Special Characters
  9130. 
  9131. File: as.info, Node: i860-Chars, Up: Syntax of i860
  9132. 9.16.5.1 Special Characters
  9133. ...........................
  9134. The presence of a '#' appearing anywhere on a line indicates the start
  9135. of a comment that extends to the end of that line.
  9136. If a '#' appears as the first character of a line then the whole line
  9137. is treated as a comment, but in this case the line can also be a logical
  9138. line number directive (*note Comments::) or a preprocessor control
  9139. command (*note Preprocessing::).
  9140. The ';' character can be used to separate statements on the same
  9141. line.
  9142. 
  9143. File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
  9144. 9.17 Intel 80960 Dependent Features
  9145. ===================================
  9146. * Menu:
  9147. * Options-i960:: i960 Command-line Options
  9148. * Floating Point-i960:: Floating Point
  9149. * Directives-i960:: i960 Machine Directives
  9150. * Opcodes for i960:: i960 Opcodes
  9151. * Syntax of i960:: i960 Syntax
  9152. 
  9153. File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
  9154. 9.17.1 i960 Command-line Options
  9155. --------------------------------
  9156. '-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
  9157. Select the 80960 architecture. Instructions or features not
  9158. supported by the selected architecture cause fatal errors.
  9159. '-ACA' is equivalent to '-ACA_A'; '-AKC' is equivalent to '-AMC'.
  9160. Synonyms are provided for compatibility with other tools.
  9161. If you do not specify any of these options, 'as' generates code for
  9162. any instruction or feature that is supported by _some_ version of
  9163. the 960 (even if this means mixing architectures!). In principle,
  9164. 'as' attempts to deduce the minimal sufficient processor type if
  9165. none is specified; depending on the object code format, the
  9166. processor type may be recorded in the object file. If it is
  9167. critical that the 'as' output match a specific architecture,
  9168. specify that architecture explicitly.
  9169. '-b'
  9170. Add code to collect information about conditional branches taken,
  9171. for later optimization using branch prediction bits. (The
  9172. conditional branch instructions have branch prediction bits in the
  9173. CA, CB, and CC architectures.) If BR represents a conditional
  9174. branch instruction, the following represents the code generated by
  9175. the assembler when '-b' is specified:
  9176. call INCREMENT ROUTINE
  9177. .word 0 # pre-counter
  9178. Label: BR
  9179. call INCREMENT ROUTINE
  9180. .word 0 # post-counter
  9181. The counter following a branch records the number of times that
  9182. branch was _not_ taken; the difference between the two counters is
  9183. the number of times the branch _was_ taken.
  9184. A table of every such 'Label' is also generated, so that the
  9185. external postprocessor 'gbr960' (supplied by Intel) can locate all
  9186. the counters. This table is always labeled '__BRANCH_TABLE__';
  9187. this is a local symbol to permit collecting statistics for many
  9188. separate object files. The table is word aligned, and begins with
  9189. a two-word header. The first word, initialized to 0, is used in
  9190. maintaining linked lists of branch tables. The second word is a
  9191. count of the number of entries in the table, which follow
  9192. immediately: each is a word, pointing to one of the labels
  9193. illustrated above.
  9194. +------------+------------+------------+ ... +------------+
  9195. | | | | | |
  9196. | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
  9197. | | | | | |
  9198. +------------+------------+------------+ ... +------------+
  9199. __BRANCH_TABLE__ layout
  9200. The first word of the header is used to locate multiple branch
  9201. tables, since each object file may contain one. Normally the links
  9202. are maintained with a call to an initialization routine, placed at
  9203. the beginning of each function in the file. The GNU C compiler
  9204. generates these calls automatically when you give it a '-b' option.
  9205. For further details, see the documentation of 'gbr960'.
  9206. '-no-relax'
  9207. Normally, Compare-and-Branch instructions with targets that require
  9208. displacements greater than 13 bits (or that have external targets)
  9209. are replaced with the corresponding compare (or 'chkbit') and
  9210. branch instructions. You can use the '-no-relax' option to specify
  9211. that 'as' should generate errors instead, if the target
  9212. displacement is larger than 13 bits.
  9213. This option does not affect the Compare-and-Jump instructions; the
  9214. code emitted for them is _always_ adjusted when necessary
  9215. (depending on displacement size), regardless of whether you use
  9216. '-no-relax'.
  9217. 
  9218. File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
  9219. 9.17.2 Floating Point
  9220. ---------------------
  9221. 'as' generates IEEE floating-point numbers for the directives '.float',
  9222. '.double', '.extended', and '.single'.
  9223. 
  9224. File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent
  9225. 9.17.3 i960 Machine Directives
  9226. ------------------------------
  9227. '.bss SYMBOL, LENGTH, ALIGN'
  9228. Reserve LENGTH bytes in the bss section for a local SYMBOL, aligned
  9229. to the power of two specified by ALIGN. LENGTH and ALIGN must be
  9230. positive absolute expressions. This directive differs from
  9231. '.lcomm' only in that it permits you to specify an alignment.
  9232. *Note '.lcomm': Lcomm.
  9233. '.extended FLONUMS'
  9234. '.extended' expects zero or more flonums, separated by commas; for
  9235. each flonum, '.extended' emits an IEEE extended-format (80-bit)
  9236. floating-point number.
  9237. '.leafproc CALL-LAB, BAL-LAB'
  9238. You can use the '.leafproc' directive in conjunction with the
  9239. optimized 'callj' instruction to enable faster calls of leaf
  9240. procedures. If a procedure is known to call no other procedures,
  9241. you may define an entry point that skips procedure prolog code (and
  9242. that does not depend on system-supplied saved context), and declare
  9243. it as the BAL-LAB using '.leafproc'. If the procedure also has an
  9244. entry point that goes through the normal prolog, you can specify
  9245. that entry point as CALL-LAB.
  9246. A '.leafproc' declaration is meant for use in conjunction with the
  9247. optimized call instruction 'callj'; the directive records the data
  9248. needed later to choose between converting the 'callj' into a 'bal'
  9249. or a 'call'.
  9250. CALL-LAB is optional; if only one argument is present, or if the
  9251. two arguments are identical, the single argument is assumed to be
  9252. the 'bal' entry point.
  9253. '.sysproc NAME, INDEX'
  9254. The '.sysproc' directive defines a name for a system procedure.
  9255. After you define it using '.sysproc', you can use NAME to refer to
  9256. the system procedure identified by INDEX when calling procedures
  9257. with the optimized call instruction 'callj'.
  9258. Both arguments are required; INDEX must be between 0 and 31
  9259. (inclusive).
  9260. 
  9261. File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent
  9262. 9.17.4 i960 Opcodes
  9263. -------------------
  9264. All Intel 960 machine instructions are supported; *note i960
  9265. Command-line Options: Options-i960. for a discussion of selecting the
  9266. instruction subset for a particular 960 architecture.
  9267. Some opcodes are processed beyond simply emitting a single
  9268. corresponding instruction: 'callj', and Compare-and-Branch or
  9269. Compare-and-Jump instructions with target displacements larger than 13
  9270. bits.
  9271. * Menu:
  9272. * callj-i960:: 'callj'
  9273. * Compare-and-branch-i960:: Compare-and-Branch
  9274. 
  9275. File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960
  9276. 9.17.4.1 'callj'
  9277. ................
  9278. You can write 'callj' to have the assembler or the linker determine the
  9279. most appropriate form of subroutine call: 'call', 'bal', or 'calls'. If
  9280. the assembly source contains enough information--a '.leafproc' or
  9281. '.sysproc' directive defining the operand--then 'as' translates the
  9282. 'callj'; if not, it simply emits the 'callj', leaving it for the linker
  9283. to resolve.
  9284. 
  9285. File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
  9286. 9.17.4.2 Compare-and-Branch
  9287. ...........................
  9288. The 960 architectures provide combined Compare-and-Branch instructions
  9289. that permit you to store the branch target in the lower 13 bits of the
  9290. instruction word itself. However, if you specify a branch target far
  9291. enough away that its address won't fit in 13 bits, the assembler can
  9292. either issue an error, or convert your Compare-and-Branch instruction
  9293. into separate instructions to do the compare and the branch.
  9294. Whether 'as' gives an error or expands the instruction depends on two
  9295. choices you can make: whether you use the '-no-relax' option, and
  9296. whether you use a "Compare and Branch" instruction or a "Compare and
  9297. Jump" instruction. The "Jump" instructions are _always_ expanded if
  9298. necessary; the "Branch" instructions are expanded when necessary
  9299. _unless_ you specify '-no-relax'--in which case 'as' gives an error
  9300. instead.
  9301. These are the Compare-and-Branch instructions, their "Jump" variants,
  9302. and the instruction pairs they may expand into:
  9303. Compare and
  9304. Branch Jump Expanded to
  9305. ------ ------ ------------
  9306. bbc chkbit; bno
  9307. bbs chkbit; bo
  9308. cmpibe cmpije cmpi; be
  9309. cmpibg cmpijg cmpi; bg
  9310. cmpibge cmpijge cmpi; bge
  9311. cmpibl cmpijl cmpi; bl
  9312. cmpible cmpijle cmpi; ble
  9313. cmpibno cmpijno cmpi; bno
  9314. cmpibne cmpijne cmpi; bne
  9315. cmpibo cmpijo cmpi; bo
  9316. cmpobe cmpoje cmpo; be
  9317. cmpobg cmpojg cmpo; bg
  9318. cmpobge cmpojge cmpo; bge
  9319. cmpobl cmpojl cmpo; bl
  9320. cmpoble cmpojle cmpo; ble
  9321. cmpobne cmpojne cmpo; bne
  9322. 
  9323. File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent
  9324. 9.17.5 Syntax for the i960
  9325. --------------------------
  9326. * Menu:
  9327. * i960-Chars:: Special Characters
  9328. 
  9329. File: as.info, Node: i960-Chars, Up: Syntax of i960
  9330. 9.17.5.1 Special Characters
  9331. ...........................
  9332. The presence of a '#' on a line indicates the start of a comment that
  9333. extends to the end of the current line.
  9334. If a '#' appears as the first character of a line, the whole line is
  9335. treated as a comment, but in this case the line can also be a logical
  9336. line number directive (*note Comments::) or a preprocessor control
  9337. command (*note Preprocessing::).
  9338. The ';' character can be used to separate statements on the same
  9339. line.
  9340. 
  9341. File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
  9342. 9.18 IA-64 Dependent Features
  9343. =============================
  9344. * Menu:
  9345. * IA-64 Options:: Options
  9346. * IA-64 Syntax:: Syntax
  9347. * IA-64 Opcodes:: Opcodes
  9348. 
  9349. File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent
  9350. 9.18.1 Options
  9351. --------------
  9352. '-mconstant-gp'
  9353. This option instructs the assembler to mark the resulting object
  9354. file as using the "constant GP" model. With this model, it is
  9355. assumed that the entire program uses a single global pointer (GP)
  9356. value. Note that this option does not in any fashion affect the
  9357. machine code emitted by the assembler. All it does is turn on the
  9358. EF_IA_64_CONS_GP flag in the ELF file header.
  9359. '-mauto-pic'
  9360. This option instructs the assembler to mark the resulting object
  9361. file as using the "constant GP without function descriptor" data
  9362. model. This model is like the "constant GP" model, except that it
  9363. additionally does away with function descriptors. What this means
  9364. is that the address of a function refers directly to the function's
  9365. code entry-point. Normally, such an address would refer to a
  9366. function descriptor, which contains both the code entry-point and
  9367. the GP-value needed by the function. Note that this option does
  9368. not in any fashion affect the machine code emitted by the
  9369. assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP
  9370. flag in the ELF file header.
  9371. '-milp32'
  9372. '-milp64'
  9373. '-mlp64'
  9374. '-mp64'
  9375. These options select the data model. The assembler defaults to
  9376. '-mlp64' (LP64 data model).
  9377. '-mle'
  9378. '-mbe'
  9379. These options select the byte order. The '-mle' option selects
  9380. little-endian byte order (default) and '-mbe' selects big-endian
  9381. byte order. Note that IA-64 machine code always uses little-endian
  9382. byte order.
  9383. '-mtune=itanium1'
  9384. '-mtune=itanium2'
  9385. Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
  9386. is ITANIUM2.
  9387. '-munwind-check=warning'
  9388. '-munwind-check=error'
  9389. These options control what the assembler will do when performing
  9390. consistency checks on unwind directives. '-munwind-check=warning'
  9391. will make the assembler issue a warning when an unwind directive
  9392. check fails. This is the default. '-munwind-check=error' will
  9393. make the assembler issue an error when an unwind directive check
  9394. fails.
  9395. '-mhint.b=ok'
  9396. '-mhint.b=warning'
  9397. '-mhint.b=error'
  9398. These options control what the assembler will do when the 'hint.b'
  9399. instruction is used. '-mhint.b=ok' will make the assembler accept
  9400. 'hint.b'. '-mint.b=warning' will make the assembler issue a
  9401. warning when 'hint.b' is used. '-mhint.b=error' will make the
  9402. assembler treat 'hint.b' as an error, which is the default.
  9403. '-x'
  9404. '-xexplicit'
  9405. These options turn on dependency violation checking.
  9406. '-xauto'
  9407. This option instructs the assembler to automatically insert stop
  9408. bits where necessary to remove dependency violations. This is the
  9409. default mode.
  9410. '-xnone'
  9411. This option turns off dependency violation checking.
  9412. '-xdebug'
  9413. This turns on debug output intended to help tracking down bugs in
  9414. the dependency violation checker.
  9415. '-xdebugn'
  9416. This is a shortcut for -xnone -xdebug.
  9417. '-xdebugx'
  9418. This is a shortcut for -xexplicit -xdebug.
  9419. 
  9420. File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent
  9421. 9.18.2 Syntax
  9422. -------------
  9423. The assembler syntax closely follows the IA-64 Assembly Language
  9424. Reference Guide.
  9425. * Menu:
  9426. * IA-64-Chars:: Special Characters
  9427. * IA-64-Regs:: Register Names
  9428. * IA-64-Bits:: Bit Names
  9429. * IA-64-Relocs:: Relocations
  9430. 
  9431. File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax
  9432. 9.18.2.1 Special Characters
  9433. ...........................
  9434. '//' is the line comment token.
  9435. ';' can be used instead of a newline to separate statements.
  9436. 
  9437. File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax
  9438. 9.18.2.2 Register Names
  9439. .......................
  9440. The 128 integer registers are referred to as 'rN'. The 128
  9441. floating-point registers are referred to as 'fN'. The 128 application
  9442. registers are referred to as 'arN'. The 128 control registers are
  9443. referred to as 'crN'. The 64 one-bit predicate registers are referred
  9444. to as 'pN'. The 8 branch registers are referred to as 'bN'. In
  9445. addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp'
  9446. ('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'),
  9447. 'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N').
  9448. For convenience, the assembler also defines aliases for all named
  9449. application and control registers. For example, 'ar.bsp' refers to the
  9450. register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to
  9451. the end-of-interrupt register ('cr67').
  9452. 
  9453. File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax
  9454. 9.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
  9455. ........................................................
  9456. The assembler defines bit masks for each of the bits in the IA-64
  9457. processor status register. For example, 'psr.ic' corresponds to a value
  9458. of 0x2000. These masks are primarily intended for use with the
  9459. 'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere
  9460. else where an integer constant is expected.
  9461. 
  9462. File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax
  9463. 9.18.2.4 Relocations
  9464. ....................
  9465. In addition to the standard IA-64 relocations, the following relocations
  9466. are implemented by 'as':
  9467. '@slotcount(V)'
  9468. Convert the address offset V into a slot count. This pseudo
  9469. function is available only on VMS. The expression V must be known
  9470. at assembly time: it can't reference undefined symbols or symbols
  9471. in different sections.
  9472. 
  9473. File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent
  9474. 9.18.3 Opcodes
  9475. --------------
  9476. For detailed information on the IA-64 machine instruction set, see the
  9477. IA-64 Architecture Handbook
  9478. (http://developer.intel.com/design/itanium/arch_spec.htm).
  9479. 
  9480. File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
  9481. 9.19 IP2K Dependent Features
  9482. ============================
  9483. * Menu:
  9484. * IP2K-Opts:: IP2K Options
  9485. * IP2K-Syntax:: IP2K Syntax
  9486. 
  9487. File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent
  9488. 9.19.1 IP2K Options
  9489. -------------------
  9490. The Ubicom IP2K version of 'as' has a few machine dependent options:
  9491. '-mip2022ext'
  9492. 'as' can assemble the extended IP2022 instructions, but it will
  9493. only do so if this is specifically allowed via this command line
  9494. option.
  9495. '-mip2022'
  9496. This option restores the assembler's default behaviour of not
  9497. permitting the extended IP2022 instructions to be assembled.
  9498. 
  9499. File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent
  9500. 9.19.2 IP2K Syntax
  9501. ------------------
  9502. * Menu:
  9503. * IP2K-Chars:: Special Characters
  9504. 
  9505. File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax
  9506. 9.19.2.1 Special Characters
  9507. ...........................
  9508. The presence of a ';' on a line indicates the start of a comment that
  9509. extends to the end of the current line.
  9510. If a '#' appears as the first character of a line, the whole line is
  9511. treated as a comment, but in this case the line can also be a logical
  9512. line number directive (*note Comments::) or a preprocessor control
  9513. command (*note Preprocessing::).
  9514. The IP2K assembler does not currently support a line separator
  9515. character.
  9516. 
  9517. File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
  9518. 9.20 LM32 Dependent Features
  9519. ============================
  9520. * Menu:
  9521. * LM32 Options:: Options
  9522. * LM32 Syntax:: Syntax
  9523. * LM32 Opcodes:: Opcodes
  9524. 
  9525. File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent
  9526. 9.20.1 Options
  9527. --------------
  9528. '-mmultiply-enabled'
  9529. Enable multiply instructions.
  9530. '-mdivide-enabled'
  9531. Enable divide instructions.
  9532. '-mbarrel-shift-enabled'
  9533. Enable barrel-shift instructions.
  9534. '-msign-extend-enabled'
  9535. Enable sign extend instructions.
  9536. '-muser-enabled'
  9537. Enable user defined instructions.
  9538. '-micache-enabled'
  9539. Enable instruction cache related CSRs.
  9540. '-mdcache-enabled'
  9541. Enable data cache related CSRs.
  9542. '-mbreak-enabled'
  9543. Enable break instructions.
  9544. '-mall-enabled'
  9545. Enable all instructions and CSRs.
  9546. 
  9547. File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent
  9548. 9.20.2 Syntax
  9549. -------------
  9550. * Menu:
  9551. * LM32-Regs:: Register Names
  9552. * LM32-Modifiers:: Relocatable Expression Modifiers
  9553. * LM32-Chars:: Special Characters
  9554. 
  9555. File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax
  9556. 9.20.2.1 Register Names
  9557. .......................
  9558. LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'.
  9559. The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' -
  9560. 'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'.
  9561. LM32 has the following Control and Status Registers (CSRs).
  9562. 'IE'
  9563. Interrupt enable.
  9564. 'IM'
  9565. Interrupt mask.
  9566. 'IP'
  9567. Interrupt pending.
  9568. 'ICC'
  9569. Instruction cache control.
  9570. 'DCC'
  9571. Data cache control.
  9572. 'CC'
  9573. Cycle counter.
  9574. 'CFG'
  9575. Configuration.
  9576. 'EBA'
  9577. Exception base address.
  9578. 'DC'
  9579. Debug control.
  9580. 'DEBA'
  9581. Debug exception base address.
  9582. 'JTX'
  9583. JTAG transmit.
  9584. 'JRX'
  9585. JTAG receive.
  9586. 'BP0'
  9587. Breakpoint 0.
  9588. 'BP1'
  9589. Breakpoint 1.
  9590. 'BP2'
  9591. Breakpoint 2.
  9592. 'BP3'
  9593. Breakpoint 3.
  9594. 'WP0'
  9595. Watchpoint 0.
  9596. 'WP1'
  9597. Watchpoint 1.
  9598. 'WP2'
  9599. Watchpoint 2.
  9600. 'WP3'
  9601. Watchpoint 3.
  9602. 
  9603. File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax
  9604. 9.20.2.2 Relocatable Expression Modifiers
  9605. .........................................
  9606. The assembler supports several modifiers when using relocatable
  9607. addresses in LM32 instruction operands. The general syntax is the
  9608. following:
  9609. modifier(relocatable-expression)
  9610. 'lo'
  9611. This modifier allows you to use bits 0 through 15 of an address
  9612. expression as 16 bit relocatable expression.
  9613. 'hi'
  9614. This modifier allows you to use bits 16 through 23 of an address
  9615. expression as 16 bit relocatable expression.
  9616. For example
  9617. ori r4, r4, lo(sym+10)
  9618. orhi r4, r4, hi(sym+10)
  9619. 'gp'
  9620. This modified creates a 16-bit relocatable expression that is the
  9621. offset of the symbol from the global pointer.
  9622. mva r4, gp(sym)
  9623. 'got'
  9624. This modifier places a symbol in the GOT and creates a 16-bit
  9625. relocatable expression that is the offset into the GOT of this
  9626. symbol.
  9627. lw r4, (gp+got(sym))
  9628. 'gotofflo16'
  9629. This modifier allows you to use the bits 0 through 15 of an address
  9630. which is an offset from the GOT.
  9631. 'gotoffhi16'
  9632. This modifier allows you to use the bits 16 through 31 of an
  9633. address which is an offset from the GOT.
  9634. orhi r4, r4, gotoffhi16(lsym)
  9635. addi r4, r4, gotofflo16(lsym)
  9636. 
  9637. File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax
  9638. 9.20.2.3 Special Characters
  9639. ...........................
  9640. The presence of a '#' on a line indicates the start of a comment that
  9641. extends to the end of the current line. Note that if a line starts with
  9642. a '#' character then it can also be a logical line number directive
  9643. (*note Comments::) or a preprocessor control command (*note
  9644. Preprocessing::).
  9645. A semicolon (';') can be used to separate multiple statements on the
  9646. same line.
  9647. 
  9648. File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent
  9649. 9.20.3 Opcodes
  9650. --------------
  9651. For detailed information on the LM32 machine instruction set, see
  9652. <http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>.
  9653. 'as' implements all the standard LM32 opcodes.
  9654. 
  9655. File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies
  9656. 9.21 M32C Dependent Features
  9657. ============================
  9658. 'as' can assemble code for several different members of the Renesas M32C
  9659. family. Normally the default is to assemble code for the M16C
  9660. microprocessor. The '-m32c' option may be used to change the default to
  9661. the M32C microprocessor.
  9662. * Menu:
  9663. * M32C-Opts:: M32C Options
  9664. * M32C-Syntax:: M32C Syntax
  9665. 
  9666. File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent
  9667. 9.21.1 M32C Options
  9668. -------------------
  9669. The Renesas M32C version of 'as' has these machine-dependent options:
  9670. '-m32c'
  9671. Assemble M32C instructions.
  9672. '-m16c'
  9673. Assemble M16C instructions (default).
  9674. '-relax'
  9675. Enable support for link-time relaxations.
  9676. '-h-tick-hex'
  9677. Support H'00 style hex constants in addition to 0x00 style.
  9678. 
  9679. File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent
  9680. 9.21.2 M32C Syntax
  9681. ------------------
  9682. * Menu:
  9683. * M32C-Modifiers:: Symbolic Operand Modifiers
  9684. * M32C-Chars:: Special Characters
  9685. 
  9686. File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax
  9687. 9.21.2.1 Symbolic Operand Modifiers
  9688. ...................................
  9689. The assembler supports several modifiers when using symbol addresses in
  9690. M32C instruction operands. The general syntax is the following:
  9691. %modifier(symbol)
  9692. '%dsp8'
  9693. '%dsp16'
  9694. These modifiers override the assembler's assumptions about how big
  9695. a symbol's address is. Normally, when it sees an operand like
  9696. 'sym[a0]' it assumes 'sym' may require the widest displacement
  9697. field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers
  9698. tell it to assume the address will fit in an 8 or 16 bit
  9699. (respectively) unsigned displacement. Note that, of course, if it
  9700. doesn't actually fit you will get linker errors. Example:
  9701. mov.w %dsp8(sym)[a0],r1
  9702. mov.b #0,%dsp8(sym)[a0]
  9703. '%hi8'
  9704. This modifier allows you to load bits 16 through 23 of a 24 bit
  9705. address into an 8 bit register. This is useful with, for example,
  9706. the M16C 'smovf' instruction, which expects a 20 bit address in
  9707. 'r1h' and 'a0'. Example:
  9708. mov.b #%hi8(sym),r1h
  9709. mov.w #%lo16(sym),a0
  9710. smovf.b
  9711. '%lo16'
  9712. Likewise, this modifier allows you to load bits 0 through 15 of a
  9713. 24 bit address into a 16 bit register.
  9714. '%hi16'
  9715. This modifier allows you to load bits 16 through 31 of a 32 bit
  9716. address into a 16 bit register. While the M32C family only has 24
  9717. bits of address space, it does support addresses in pairs of 16 bit
  9718. registers (like 'a1a0' for the 'lde' instruction). This modifier
  9719. is for loading the upper half in such cases. Example:
  9720. mov.w #%hi16(sym),a1
  9721. mov.w #%lo16(sym),a0
  9722. ...
  9723. lde.w [a1a0],r1
  9724. 
  9725. File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax
  9726. 9.21.2.2 Special Characters
  9727. ...........................
  9728. The presence of a ';' character on a line indicates the start of a
  9729. comment that extends to the end of that line.
  9730. If a '#' appears as the first character of a line, the whole line is
  9731. treated as a comment, but in this case the line can also be a logical
  9732. line number directive (*note Comments::) or a preprocessor control
  9733. command (*note Preprocessing::).
  9734. The '|' character can be used to separate statements on the same
  9735. line.
  9736. 
  9737. File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies
  9738. 9.22 M32R Dependent Features
  9739. ============================
  9740. * Menu:
  9741. * M32R-Opts:: M32R Options
  9742. * M32R-Directives:: M32R Directives
  9743. * M32R-Warnings:: M32R Warnings
  9744. 
  9745. File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent
  9746. 9.22.1 M32R Options
  9747. -------------------
  9748. The Renease M32R version of 'as' has a few machine dependent options:
  9749. '-m32rx'
  9750. 'as' can assemble code for several different members of the Renesas
  9751. M32R family. Normally the default is to assemble code for the M32R
  9752. microprocessor. This option may be used to change the default to
  9753. the M32RX microprocessor, which adds some more instructions to the
  9754. basic M32R instruction set, and some additional parameters to some
  9755. of the original instructions.
  9756. '-m32r2'
  9757. This option changes the target processor to the M32R2
  9758. microprocessor.
  9759. '-m32r'
  9760. This option can be used to restore the assembler's default
  9761. behaviour of assembling for the M32R microprocessor. This can be
  9762. useful if the default has been changed by a previous command line
  9763. option.
  9764. '-little'
  9765. This option tells the assembler to produce little-endian code and
  9766. data. The default is dependent upon how the toolchain was
  9767. configured.
  9768. '-EL'
  9769. This is a synonym for _-little_.
  9770. '-big'
  9771. This option tells the assembler to produce big-endian code and
  9772. data.
  9773. '-EB'
  9774. This is a synonum for _-big_.
  9775. '-KPIC'
  9776. This option specifies that the output of the assembler should be
  9777. marked as position-independent code (PIC).
  9778. '-parallel'
  9779. This option tells the assembler to attempts to combine two
  9780. sequential instructions into a single, parallel instruction, where
  9781. it is legal to do so.
  9782. '-no-parallel'
  9783. This option disables a previously enabled _-parallel_ option.
  9784. '-no-bitinst'
  9785. This option disables the support for the extended bit-field
  9786. instructions provided by the M32R2. If this support needs to be
  9787. re-enabled the _-bitinst_ switch can be used to restore it.
  9788. '-O'
  9789. This option tells the assembler to attempt to optimize the
  9790. instructions that it produces. This includes filling delay slots
  9791. and converting sequential instructions into parallel ones. This
  9792. option implies _-parallel_.
  9793. '-warn-explicit-parallel-conflicts'
  9794. Instructs 'as' to produce warning messages when questionable
  9795. parallel instructions are encountered. This option is enabled by
  9796. default, but 'gcc' disables it when it invokes 'as' directly.
  9797. Questionable instructions are those whose behaviour would be
  9798. different if they were executed sequentially. For example the code
  9799. fragment 'mv r1, r2 || mv r3, r1' produces a different result from
  9800. 'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then
  9801. r2 into r1, whereas the later moves r2 into r1 and r3.
  9802. '-Wp'
  9803. This is a shorter synonym for the
  9804. _-warn-explicit-parallel-conflicts_ option.
  9805. '-no-warn-explicit-parallel-conflicts'
  9806. Instructs 'as' not to produce warning messages when questionable
  9807. parallel instructions are encountered.
  9808. '-Wnp'
  9809. This is a shorter synonym for the
  9810. _-no-warn-explicit-parallel-conflicts_ option.
  9811. '-ignore-parallel-conflicts'
  9812. This option tells the assembler's to stop checking parallel
  9813. instructions for constraint violations. This ability is provided
  9814. for hardware vendors testing chip designs and should not be used
  9815. under normal circumstances.
  9816. '-no-ignore-parallel-conflicts'
  9817. This option restores the assembler's default behaviour of checking
  9818. parallel instructions to detect constraint violations.
  9819. '-Ip'
  9820. This is a shorter synonym for the _-ignore-parallel-conflicts_
  9821. option.
  9822. '-nIp'
  9823. This is a shorter synonym for the _-no-ignore-parallel-conflicts_
  9824. option.
  9825. '-warn-unmatched-high'
  9826. This option tells the assembler to produce a warning message if a
  9827. '.high' pseudo op is encountered without a matching '.low' pseudo
  9828. op. The presence of such an unmatched pseudo op usually indicates
  9829. a programming error.
  9830. '-no-warn-unmatched-high'
  9831. Disables a previously enabled _-warn-unmatched-high_ option.
  9832. '-Wuh'
  9833. This is a shorter synonym for the _-warn-unmatched-high_ option.
  9834. '-Wnuh'
  9835. This is a shorter synonym for the _-no-warn-unmatched-high_ option.
  9836. 
  9837. File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent
  9838. 9.22.2 M32R Directives
  9839. ----------------------
  9840. The Renease M32R version of 'as' has a few architecture specific
  9841. directives:
  9842. 'low EXPRESSION'
  9843. The 'low' directive computes the value of its expression and places
  9844. the lower 16-bits of the result into the immediate-field of the
  9845. instruction. For example:
  9846. or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
  9847. add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
  9848. 'high EXPRESSION'
  9849. The 'high' directive computes the value of its expression and
  9850. places the upper 16-bits of the result into the immediate-field of
  9851. the instruction. For example:
  9852. seth r0, #high(0x12345678) ; compute r0 = 0x12340000
  9853. seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
  9854. 'shigh EXPRESSION'
  9855. The 'shigh' directive is very similar to the 'high' directive. It
  9856. also computes the value of its expression and places the upper
  9857. 16-bits of the result into the immediate-field of the instruction.
  9858. The difference is that 'shigh' also checks to see if the lower
  9859. 16-bits could be interpreted as a signed number, and if so it
  9860. assumes that a borrow will occur from the upper-16 bits. To
  9861. compensate for this the 'shigh' directive pre-biases the upper 16
  9862. bit value by adding one to it. For example:
  9863. For example:
  9864. seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
  9865. seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
  9866. In the second example the lower 16-bits are 0x8000. If these are
  9867. treated as a signed value and sign extended to 32-bits then the
  9868. value becomes 0xffff8000. If this value is then added to
  9869. 0x00010000 then the result is 0x00008000.
  9870. This behaviour is to allow for the different semantics of the 'or3'
  9871. and 'add3' instructions. The 'or3' instruction treats its 16-bit
  9872. immediate argument as unsigned whereas the 'add3' treats its 16-bit
  9873. immediate as a signed value. So for example:
  9874. seth r0, #shigh(0x00008000)
  9875. add3 r0, r0, #low(0x00008000)
  9876. Produces the correct result in r0, whereas:
  9877. seth r0, #shigh(0x00008000)
  9878. or3 r0, r0, #low(0x00008000)
  9879. Stores 0xffff8000 into r0.
  9880. Note - the 'shigh' directive does not know where in the assembly
  9881. source code the lower 16-bits of the value are going set, so it
  9882. cannot check to make sure that an 'or3' instruction is being used
  9883. rather than an 'add3' instruction. It is up to the programmer to
  9884. make sure that correct directives are used.
  9885. '.m32r'
  9886. The directive performs a similar thing as the _-m32r_ command line
  9887. option. It tells the assembler to only accept M32R instructions
  9888. from now on. An instructions from later M32R architectures are
  9889. refused.
  9890. '.m32rx'
  9891. The directive performs a similar thing as the _-m32rx_ command line
  9892. option. It tells the assembler to start accepting the extra
  9893. instructions in the M32RX ISA as well as the ordinary M32R ISA.
  9894. '.m32r2'
  9895. The directive performs a similar thing as the _-m32r2_ command line
  9896. option. It tells the assembler to start accepting the extra
  9897. instructions in the M32R2 ISA as well as the ordinary M32R ISA.
  9898. '.little'
  9899. The directive performs a similar thing as the _-little_ command
  9900. line option. It tells the assembler to start producing
  9901. little-endian code and data. This option should be used with care
  9902. as producing mixed-endian binary files is fraught with danger.
  9903. '.big'
  9904. The directive performs a similar thing as the _-big_ command line
  9905. option. It tells the assembler to start producing big-endian code
  9906. and data. This option should be used with care as producing
  9907. mixed-endian binary files is fraught with danger.
  9908. 
  9909. File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent
  9910. 9.22.3 M32R Warnings
  9911. --------------------
  9912. There are several warning and error messages that can be produced by
  9913. 'as' which are specific to the M32R:
  9914. 'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
  9915. This message is only produced if warnings for explicit parallel
  9916. conflicts have been enabled. It indicates that the assembler has
  9917. encountered a parallel instruction in which the destination
  9918. register of the left hand instruction is used as an input register
  9919. in the right hand instruction. For example in this code fragment
  9920. 'mv r1, r2 || neg r3, r1' register r1 is the destination of the
  9921. move instruction and the input to the neg instruction.
  9922. 'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
  9923. This message is only produced if warnings for explicit parallel
  9924. conflicts have been enabled. It indicates that the assembler has
  9925. encountered a parallel instruction in which the destination
  9926. register of the right hand instruction is used as an input register
  9927. in the left hand instruction. For example in this code fragment
  9928. 'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg
  9929. instruction and the input to the move instruction.
  9930. 'instruction '...' is for the M32RX only'
  9931. This message is produced when the assembler encounters an
  9932. instruction which is only supported by the M32Rx processor, and the
  9933. '-m32rx' command line flag has not been specified to allow assembly
  9934. of such instructions.
  9935. 'unknown instruction '...''
  9936. This message is produced when the assembler encounters an
  9937. instruction which it does not recognize.
  9938. 'only the NOP instruction can be issued in parallel on the m32r'
  9939. This message is produced when the assembler encounters a parallel
  9940. instruction which does not involve a NOP instruction and the
  9941. '-m32rx' command line flag has not been specified. Only the M32Rx
  9942. processor is able to execute two instructions in parallel.
  9943. 'instruction '...' cannot be executed in parallel.'
  9944. This message is produced when the assembler encounters a parallel
  9945. instruction which is made up of one or two instructions which
  9946. cannot be executed in parallel.
  9947. 'Instructions share the same execution pipeline'
  9948. This message is produced when the assembler encounters a parallel
  9949. instruction whoes components both use the same execution pipeline.
  9950. 'Instructions write to the same destination register.'
  9951. This message is produced when the assembler encounters a parallel
  9952. instruction where both components attempt to modify the same
  9953. register. For example these code fragments will produce this
  9954. message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2,
  9955. @-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx
  9956. r3, r4' (Both write to the condition bit)
  9957. 
  9958. File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies
  9959. 9.23 M680x0 Dependent Features
  9960. ==============================
  9961. * Menu:
  9962. * M68K-Opts:: M680x0 Options
  9963. * M68K-Syntax:: Syntax
  9964. * M68K-Moto-Syntax:: Motorola Syntax
  9965. * M68K-Float:: Floating Point
  9966. * M68K-Directives:: 680x0 Machine Directives
  9967. * M68K-opcodes:: Opcodes
  9968. 
  9969. File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
  9970. 9.23.1 M680x0 Options
  9971. ---------------------
  9972. The Motorola 680x0 version of 'as' has a few machine dependent options:
  9973. '-march=ARCHITECTURE'
  9974. This option specifies a target architecture. The following
  9975. architectures are recognized: '68000', '68010', '68020', '68030',
  9976. '68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and
  9977. 'cfv4e'.
  9978. '-mcpu=CPU'
  9979. This option specifies a target cpu. When used in conjunction with
  9980. the '-march' option, the cpu must be within the specified
  9981. architecture. Also, the generic features of the architecture are
  9982. used for instruction generation, rather than those of the specific
  9983. chip.
  9984. '-m[no-]68851'
  9985. '-m[no-]68881'
  9986. '-m[no-]div'
  9987. '-m[no-]usp'
  9988. '-m[no-]float'
  9989. '-m[no-]mac'
  9990. '-m[no-]emac'
  9991. Enable or disable various architecture specific features. If a
  9992. chip or architecture by default supports an option (for instance
  9993. '-march=isaaplus' includes the '-mdiv' option), explicitly
  9994. disabling the option will override the default.
  9995. '-l'
  9996. You can use the '-l' option to shorten the size of references to
  9997. undefined symbols. If you do not use the '-l' option, references
  9998. to undefined symbols are wide enough for a full 'long' (32 bits).
  9999. (Since 'as' cannot know where these symbols end up, 'as' can only
  10000. allocate space for the linker to fill in later. Since 'as' does
  10001. not know how far away these symbols are, it allocates as much space
  10002. as it can.) If you use this option, the references are only one
  10003. word wide (16 bits). This may be useful if you want the object
  10004. file to be as small as possible, and you know that the relevant
  10005. symbols are always less than 17 bits away.
  10006. '--register-prefix-optional'
  10007. For some configurations, especially those where the compiler
  10008. normally does not prepend an underscore to the names of user
  10009. variables, the assembler requires a '%' before any use of a
  10010. register name. This is intended to let the assembler distinguish
  10011. between C variables and functions named 'a0' through 'a7', and so
  10012. on. The '%' is always accepted, but is not required for certain
  10013. configurations, notably 'sun3'. The '--register-prefix-optional'
  10014. option may be used to permit omitting the '%' even for
  10015. configurations for which it is normally required. If this is done,
  10016. it will generally be impossible to refer to C variables and
  10017. functions with the same names as register names.
  10018. '--bitwise-or'
  10019. Normally the character '|' is treated as a comment character, which
  10020. means that it can not be used in expressions. The '--bitwise-or'
  10021. option turns '|' into a normal character. In this mode, you must
  10022. either use C style comments, or start comments with a '#' character
  10023. at the beginning of a line.
  10024. '--base-size-default-16 --base-size-default-32'
  10025. If you use an addressing mode with a base register without
  10026. specifying the size, 'as' will normally use the full 32 bit value.
  10027. For example, the addressing mode '%a0@(%d0)' is equivalent to
  10028. '%a0@(%d0:l)'. You may use the '--base-size-default-16' option to
  10029. tell 'as' to default to using the 16 bit value. In this case,
  10030. '%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the
  10031. '--base-size-default-32' option to restore the default behaviour.
  10032. '--disp-size-default-16 --disp-size-default-32'
  10033. If you use an addressing mode with a displacement, and the value of
  10034. the displacement is not known, 'as' will normally assume that the
  10035. value is 32 bits. For example, if the symbol 'disp' has not been
  10036. defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as
  10037. though 'disp' is a 32 bit value. You may use the
  10038. '--disp-size-default-16' option to tell 'as' to instead assume that
  10039. the displacement is 16 bits. In this case, 'as' will assemble
  10040. '%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use
  10041. the '--disp-size-default-32' option to restore the default
  10042. behaviour.
  10043. '--pcrel'
  10044. Always keep branches PC-relative. In the M680x0 architecture all
  10045. branches are defined as PC-relative. However, on some processors
  10046. they are limited to word displacements maximum. When 'as' needs a
  10047. long branch that is not available, it normally emits an absolute
  10048. jump instead. This option disables this substitution. When this
  10049. option is given and no long branches are available, only word
  10050. branches will be emitted. An error message will be generated if a
  10051. word branch cannot reach its target. This option has no effect on
  10052. 68020 and other processors that have long branches. *note Branch
  10053. Improvement: M68K-Branch.
  10054. '-m68000'
  10055. 'as' can assemble code for several different members of the
  10056. Motorola 680x0 family. The default depends upon how 'as' was
  10057. configured when it was built; normally, the default is to assemble
  10058. code for the 68020 microprocessor. The following options may be
  10059. used to change the default. These options control which
  10060. instructions and addressing modes are permitted. The members of
  10061. the 680x0 family are very similar. For detailed information about
  10062. the differences, see the Motorola manuals.
  10063. '-m68000'
  10064. '-m68ec000'
  10065. '-m68hc000'
  10066. '-m68hc001'
  10067. '-m68008'
  10068. '-m68302'
  10069. '-m68306'
  10070. '-m68307'
  10071. '-m68322'
  10072. '-m68356'
  10073. Assemble for the 68000. '-m68008', '-m68302', and so on are
  10074. synonyms for '-m68000', since the chips are the same from the
  10075. point of view of the assembler.
  10076. '-m68010'
  10077. Assemble for the 68010.
  10078. '-m68020'
  10079. '-m68ec020'
  10080. Assemble for the 68020. This is normally the default.
  10081. '-m68030'
  10082. '-m68ec030'
  10083. Assemble for the 68030.
  10084. '-m68040'
  10085. '-m68ec040'
  10086. Assemble for the 68040.
  10087. '-m68060'
  10088. '-m68ec060'
  10089. Assemble for the 68060.
  10090. '-mcpu32'
  10091. '-m68330'
  10092. '-m68331'
  10093. '-m68332'
  10094. '-m68333'
  10095. '-m68334'
  10096. '-m68336'
  10097. '-m68340'
  10098. '-m68341'
  10099. '-m68349'
  10100. '-m68360'
  10101. Assemble for the CPU32 family of chips.
  10102. '-m5200'
  10103. '-m5202'
  10104. '-m5204'
  10105. '-m5206'
  10106. '-m5206e'
  10107. '-m521x'
  10108. '-m5249'
  10109. '-m528x'
  10110. '-m5307'
  10111. '-m5407'
  10112. '-m547x'
  10113. '-m548x'
  10114. '-mcfv4'
  10115. '-mcfv4e'
  10116. Assemble for the ColdFire family of chips.
  10117. '-m68881'
  10118. '-m68882'
  10119. Assemble 68881 floating point instructions. This is the
  10120. default for the 68020, 68030, and the CPU32. The 68040 and
  10121. 68060 always support floating point instructions.
  10122. '-mno-68881'
  10123. Do not assemble 68881 floating point instructions. This is
  10124. the default for 68000 and the 68010. The 68040 and 68060
  10125. always support floating point instructions, even if this
  10126. option is used.
  10127. '-m68851'
  10128. Assemble 68851 MMU instructions. This is the default for the
  10129. 68020, 68030, and 68060. The 68040 accepts a somewhat
  10130. different set of MMU instructions; '-m68851' and '-m68040'
  10131. should not be used together.
  10132. '-mno-68851'
  10133. Do not assemble 68851 MMU instructions. This is the default
  10134. for the 68000, 68010, and the CPU32. The 68040 accepts a
  10135. somewhat different set of MMU instructions.
  10136. 
  10137. File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
  10138. 9.23.2 Syntax
  10139. -------------
  10140. This syntax for the Motorola 680x0 was developed at MIT.
  10141. The 680x0 version of 'as' uses instructions names and syntax
  10142. compatible with the Sun assembler. Intervening periods are ignored; for
  10143. example, 'movl' is equivalent to 'mov.l'.
  10144. In the following table APC stands for any of the address registers
  10145. ('%a0' through '%a7'), the program counter ('%pc'), the zero-address
  10146. relative to the program counter ('%zpc'), a suppressed address register
  10147. ('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE
  10148. means one of 'w' or 'l', and it may be omitted, along with the leading
  10149. colon, unless a scale is also specified. The use of SCALE means one of
  10150. '1', '2', '4', or '8', and it may always be omitted along with the
  10151. leading colon.
  10152. The following addressing modes are understood:
  10153. "Immediate"
  10154. '#NUMBER'
  10155. "Data Register"
  10156. '%d0' through '%d7'
  10157. "Address Register"
  10158. '%a0' through '%a7'
  10159. '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is
  10160. also known as '%fp', the Frame Pointer.
  10161. "Address Register Indirect"
  10162. '%a0@' through '%a7@'
  10163. "Address Register Postincrement"
  10164. '%a0@+' through '%a7@+'
  10165. "Address Register Predecrement"
  10166. '%a0@-' through '%a7@-'
  10167. "Indirect Plus Offset"
  10168. 'APC@(NUMBER)'
  10169. "Index"
  10170. 'APC@(NUMBER,REGISTER:SIZE:SCALE)'
  10171. The NUMBER may be omitted.
  10172. "Postindex"
  10173. 'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
  10174. The ONUMBER or the REGISTER, but not both, may be omitted.
  10175. "Preindex"
  10176. 'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
  10177. The NUMBER may be omitted. Omitting the REGISTER produces the
  10178. Postindex addressing mode.
  10179. "Absolute"
  10180. 'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'.
  10181. 
  10182. File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
  10183. 9.23.3 Motorola Syntax
  10184. ----------------------
  10185. The standard Motorola syntax for this chip differs from the syntax
  10186. already discussed (*note Syntax: M68K-Syntax.). 'as' can accept
  10187. Motorola syntax for operands, even if MIT syntax is used for other
  10188. operands in the same instruction. The two kinds of syntax are fully
  10189. compatible.
  10190. In the following table APC stands for any of the address registers
  10191. ('%a0' through '%a7'), the program counter ('%pc'), the zero-address
  10192. relative to the program counter ('%zpc'), or a suppressed address
  10193. register ('%za0' through '%za7'). The use of SIZE means one of 'w' or
  10194. 'l', and it may always be omitted along with the leading dot. The use
  10195. of SCALE means one of '1', '2', '4', or '8', and it may always be
  10196. omitted along with the leading asterisk.
  10197. The following additional addressing modes are understood:
  10198. "Address Register Indirect"
  10199. '(%a0)' through '(%a7)'
  10200. '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is
  10201. also known as '%fp', the Frame Pointer.
  10202. "Address Register Postincrement"
  10203. '(%a0)+' through '(%a7)+'
  10204. "Address Register Predecrement"
  10205. '-(%a0)' through '-(%a7)'
  10206. "Indirect Plus Offset"
  10207. 'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'.
  10208. The NUMBER may also appear within the parentheses, as in
  10209. '(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted
  10210. (with an address register, omitting the NUMBER produces Address
  10211. Register Indirect mode).
  10212. "Index"
  10213. 'NUMBER(APC,REGISTER.SIZE*SCALE)'
  10214. The NUMBER may be omitted, or it may appear within the parentheses.
  10215. The APC may be omitted. The REGISTER and the APC may appear in
  10216. either order. If both APC and REGISTER are address registers, and
  10217. the SIZE and SCALE are omitted, then the first register is taken as
  10218. the base register, and the second as the index register.
  10219. "Postindex"
  10220. '([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
  10221. The ONUMBER, or the REGISTER, or both, may be omitted. Either the
  10222. NUMBER or the APC may be omitted, but not both.
  10223. "Preindex"
  10224. '([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
  10225. The NUMBER, or the APC, or the REGISTER, or any two of them, may be
  10226. omitted. The ONUMBER may be omitted. The REGISTER and the APC may
  10227. appear in either order. If both APC and REGISTER are address
  10228. registers, and the SIZE and SCALE are omitted, then the first
  10229. register is taken as the base register, and the second as the index
  10230. register.
  10231. 
  10232. File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
  10233. 9.23.4 Floating Point
  10234. ---------------------
  10235. Packed decimal (P) format floating literals are not supported. Feel
  10236. free to add the code!
  10237. The floating point formats generated by directives are these.
  10238. '.float'
  10239. 'Single' precision floating point constants.
  10240. '.double'
  10241. 'Double' precision floating point constants.
  10242. '.extend'
  10243. '.ldouble'
  10244. 'Extended' precision ('long double') floating point constants.
  10245. 
  10246. File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
  10247. 9.23.5 680x0 Machine Directives
  10248. -------------------------------
  10249. In order to be compatible with the Sun assembler the 680x0 assembler
  10250. understands the following directives.
  10251. '.data1'
  10252. This directive is identical to a '.data 1' directive.
  10253. '.data2'
  10254. This directive is identical to a '.data 2' directive.
  10255. '.even'
  10256. This directive is a special case of the '.align' directive; it
  10257. aligns the output to an even byte boundary.
  10258. '.skip'
  10259. This directive is identical to a '.space' directive.
  10260. '.arch NAME'
  10261. Select the target architecture and extension features. Valid
  10262. values for NAME are the same as for the '-march' command line
  10263. option. This directive cannot be specified after any instructions
  10264. have been assembled. If it is given multiple times, or in
  10265. conjunction with the '-march' option, all uses must be for the same
  10266. architecture and extension set.
  10267. '.cpu NAME'
  10268. Select the target cpu. Valid valuse for NAME are the same as for
  10269. the '-mcpu' command line option. This directive cannot be
  10270. specified after any instructions have been assembled. If it is
  10271. given multiple times, or in conjunction with the '-mopt' option,
  10272. all uses must be for the same cpu.
  10273. 
  10274. File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
  10275. 9.23.6 Opcodes
  10276. --------------
  10277. * Menu:
  10278. * M68K-Branch:: Branch Improvement
  10279. * M68K-Chars:: Special Characters
  10280. 
  10281. File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
  10282. 9.23.6.1 Branch Improvement
  10283. ...........................
  10284. Certain pseudo opcodes are permitted for branch instructions. They
  10285. expand to the shortest branch instruction that reach the target.
  10286. Generally these mnemonics are made by substituting 'j' for 'b' at the
  10287. start of a Motorola mnemonic.
  10288. The following table summarizes the pseudo-operations. A '*' flags
  10289. cases that are more fully described after the table:
  10290. Displacement
  10291. +------------------------------------------------------------
  10292. | 68020 68000/10, not PC-relative OK
  10293. Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
  10294. +------------------------------------------------------------
  10295. jbsr |bsrs bsrw bsrl jsr
  10296. jra |bras braw bral jmp
  10297. * jXX |bXXs bXXw bXXl bNXs;jmp
  10298. * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
  10299. fjXX | N/A fbXXw fbXXl N/A
  10300. XX: condition
  10301. NX: negative of condition XX
  10302. '*'--see full description below
  10303. '**'--this expansion mode is disallowed by '--pcrel'
  10304. 'jbsr'
  10305. 'jra'
  10306. These are the simplest jump pseudo-operations; they always map to
  10307. one particular machine instruction, depending on the displacement
  10308. to the branch target. This instruction will be a byte or word
  10309. branch is that is sufficient. Otherwise, a long branch will be
  10310. emitted if available. If no long branches are available and the
  10311. '--pcrel' option is not given, an absolute long jump will be
  10312. emitted instead. If no long branches are available, the '--pcrel'
  10313. option is given, and a word branch cannot reach the target, an
  10314. error message is generated.
  10315. In addition to standard branch operands, 'as' allows these
  10316. pseudo-operations to have all operands that are allowed for jsr and
  10317. jmp, substituting these instructions if the operand given is not
  10318. valid for a branch instruction.
  10319. 'jXX'
  10320. Here, 'jXX' stands for an entire family of pseudo-operations, where
  10321. XX is a conditional branch or condition-code test. The full list
  10322. of pseudo-ops in this family is:
  10323. jhi jls jcc jcs jne jeq jvc
  10324. jvs jpl jmi jge jlt jgt jle
  10325. Usually, each of these pseudo-operations expands to a single branch
  10326. instruction. However, if a word branch is not sufficient, no long
  10327. branches are available, and the '--pcrel' option is not given, 'as'
  10328. issues a longer code fragment in terms of NX, the opposite
  10329. condition to XX. For example, under these conditions:
  10330. jXX foo
  10331. gives
  10332. bNXs oof
  10333. jmp foo
  10334. oof:
  10335. 'dbXX'
  10336. The full family of pseudo-operations covered here is
  10337. dbhi dbls dbcc dbcs dbne dbeq dbvc
  10338. dbvs dbpl dbmi dbge dblt dbgt dble
  10339. dbf dbra dbt
  10340. Motorola 'dbXX' instructions allow word displacements only. When a
  10341. word displacement is sufficient, each of these pseudo-operations
  10342. expands to the corresponding Motorola instruction. When a word
  10343. displacement is not sufficient and long branches are available,
  10344. when the source reads 'dbXX foo', 'as' emits
  10345. dbXX oo1
  10346. bras oo2
  10347. oo1:bral foo
  10348. oo2:
  10349. If, however, long branches are not available and the '--pcrel'
  10350. option is not given, 'as' emits
  10351. dbXX oo1
  10352. bras oo2
  10353. oo1:jmp foo
  10354. oo2:
  10355. 'fjXX'
  10356. This family includes
  10357. fjne fjeq fjge fjlt fjgt fjle fjf
  10358. fjt fjgl fjgle fjnge fjngl fjngle fjngt
  10359. fjnle fjnlt fjoge fjogl fjogt fjole fjolt
  10360. fjor fjseq fjsf fjsne fjst fjueq fjuge
  10361. fjugt fjule fjult fjun
  10362. Each of these pseudo-operations always expands to a single Motorola
  10363. coprocessor branch instruction, word or long. All Motorola
  10364. coprocessor branch instructions allow both word and long
  10365. displacements.
  10366. 
  10367. File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
  10368. 9.23.6.2 Special Characters
  10369. ...........................
  10370. Line comments are introduced by the '|' character appearing anywhere on
  10371. a line, unless the '--bitwise-or' command line option has been
  10372. specified.
  10373. An asterisk ('*') as the first character on a line marks the start of
  10374. a line comment as well.
  10375. A hash character ('#') as the first character on a line also marks
  10376. the start of a line comment, but in this case it could also be a logical
  10377. line number directive (*note Comments::) or a preprocessor control
  10378. command (*note Preprocessing::). If the hash character appears
  10379. elsewhere on a line it is used to introduce an immediate value. (This
  10380. is for compatibility with Sun's assembler).
  10381. Multiple statements on the same line can appear if they are separated
  10382. by the ';' character.
  10383. 
  10384. File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
  10385. 9.24 M68HC11 and M68HC12 Dependent Features
  10386. ===========================================
  10387. * Menu:
  10388. * M68HC11-Opts:: M68HC11 and M68HC12 Options
  10389. * M68HC11-Syntax:: Syntax
  10390. * M68HC11-Modifiers:: Symbolic Operand Modifiers
  10391. * M68HC11-Directives:: Assembler Directives
  10392. * M68HC11-Float:: Floating Point
  10393. * M68HC11-opcodes:: Opcodes
  10394. 
  10395. File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent
  10396. 9.24.1 M68HC11 and M68HC12 Options
  10397. ----------------------------------
  10398. The Motorola 68HC11 and 68HC12 version of 'as' have a few machine
  10399. dependent options.
  10400. '-m68hc11'
  10401. This option switches the assembler into the M68HC11 mode. In this
  10402. mode, the assembler only accepts 68HC11 operands and mnemonics. It
  10403. produces code for the 68HC11.
  10404. '-m68hc12'
  10405. This option switches the assembler into the M68HC12 mode. In this
  10406. mode, the assembler also accepts 68HC12 operands and mnemonics. It
  10407. produces code for the 68HC12. A few 68HC11 instructions are
  10408. replaced by some 68HC12 instructions as recommended by Motorola
  10409. specifications.
  10410. '-m68hcs12'
  10411. This option switches the assembler into the M68HCS12 mode. This
  10412. mode is similar to '-m68hc12' but specifies to assemble for the
  10413. 68HCS12 series. The only difference is on the assembling of the
  10414. 'movb' and 'movw' instruction when a PC-relative operand is used.
  10415. '-mm9s12x'
  10416. This option switches the assembler into the M9S12X mode. This mode
  10417. is similar to '-m68hc12' but specifies to assemble for the S12X
  10418. series which is a superset of the HCS12.
  10419. '-mm9s12xg'
  10420. This option switches the assembler into the XGATE mode for the RISC
  10421. co-processor featured on some S12X-family chips.
  10422. '--xgate-ramoffset'
  10423. This option instructs the linker to offset RAM addresses from S12X
  10424. address space into XGATE address space.
  10425. '-mshort'
  10426. This option controls the ABI and indicates to use a 16-bit integer
  10427. ABI. It has no effect on the assembled instructions. This is the
  10428. default.
  10429. '-mlong'
  10430. This option controls the ABI and indicates to use a 32-bit integer
  10431. ABI.
  10432. '-mshort-double'
  10433. This option controls the ABI and indicates to use a 32-bit float
  10434. ABI. This is the default.
  10435. '-mlong-double'
  10436. This option controls the ABI and indicates to use a 64-bit float
  10437. ABI.
  10438. '--strict-direct-mode'
  10439. You can use the '--strict-direct-mode' option to disable the
  10440. automatic translation of direct page mode addressing into extended
  10441. mode when the instruction does not support direct mode. For
  10442. example, the 'clr' instruction does not support direct page mode
  10443. addressing. When it is used with the direct page mode, 'as' will
  10444. ignore it and generate an absolute addressing. This option
  10445. prevents 'as' from doing this, and the wrong usage of the direct
  10446. page mode will raise an error.
  10447. '--short-branches'
  10448. The '--short-branches' option turns off the translation of relative
  10449. branches into absolute branches when the branch offset is out of
  10450. range. By default 'as' transforms the relative branch ('bsr',
  10451. 'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls',
  10452. 'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the
  10453. offset is out of the -128 .. 127 range. In that case, the 'bsr'
  10454. instruction is translated into a 'jsr', the 'bra' instruction is
  10455. translated into a 'jmp' and the conditional branches instructions
  10456. are inverted and followed by a 'jmp'. This option disables these
  10457. translations and 'as' will generate an error if a relative branch
  10458. is out of range. This option does not affect the optimization
  10459. associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes.
  10460. '--force-long-branches'
  10461. The '--force-long-branches' option forces the translation of
  10462. relative branches into absolute branches. This option does not
  10463. affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX'
  10464. pseudo opcodes.
  10465. '--print-insn-syntax'
  10466. You can use the '--print-insn-syntax' option to obtain the syntax
  10467. description of the instruction when an error is detected.
  10468. '--print-opcodes'
  10469. The '--print-opcodes' option prints the list of all the
  10470. instructions with their syntax. The first item of each line
  10471. represents the instruction name and the rest of the line indicates
  10472. the possible operands for that instruction. The list is printed in
  10473. alphabetical order. Once the list is printed 'as' exits.
  10474. '--generate-example'
  10475. The '--generate-example' option is similar to '--print-opcodes' but
  10476. it generates an example for each instruction instead.
  10477. 
  10478. File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent
  10479. 9.24.2 Syntax
  10480. -------------
  10481. In the M68HC11 syntax, the instruction name comes first and it may be
  10482. followed by one or several operands (up to three). Operands are
  10483. separated by comma (','). In the normal mode, 'as' will complain if too
  10484. many operands are specified for a given instruction. In the MRI mode
  10485. (turned on with '-M' option), it will treat them as comments. Example:
  10486. inx
  10487. lda #23
  10488. bset 2,x #4
  10489. brclr *bot #8 foo
  10490. The presence of a ';' character or a '!' character anywhere on a line
  10491. indicates the start of a comment that extends to the end of that line.
  10492. A '*' or a '#' character at the start of a line also introduces a
  10493. line comment, but these characters do not work elsewhere on the line.
  10494. If the first character of the line is a '#' then as well as starting a
  10495. comment, the line could also be logical line number directive (*note
  10496. Comments::) or a preprocessor control command (*note Preprocessing::).
  10497. The M68HC11 assembler does not currently support a line separator
  10498. character.
  10499. The following addressing modes are understood for 68HC11 and 68HC12:
  10500. "Immediate"
  10501. '#NUMBER'
  10502. "Address Register"
  10503. 'NUMBER,X', 'NUMBER,Y'
  10504. The NUMBER may be omitted in which case 0 is assumed.
  10505. "Direct Addressing mode"
  10506. '*SYMBOL', or '*DIGITS'
  10507. "Absolute"
  10508. 'SYMBOL', or 'DIGITS'
  10509. The M68HC12 has other more complex addressing modes. All of them are
  10510. supported and they are represented below:
  10511. "Constant Offset Indexed Addressing Mode"
  10512. 'NUMBER,REG'
  10513. The NUMBER may be omitted in which case 0 is assumed. The register
  10514. can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the
  10515. smaller post-byte definition according to the constant value (5-bit
  10516. constant offset, 9-bit constant offset or 16-bit constant offset).
  10517. If the constant is not known by the assembler it will use the
  10518. 16-bit constant offset post-byte and the value will be resolved at
  10519. link time.
  10520. "Offset Indexed Indirect"
  10521. '[NUMBER,REG]'
  10522. The register can be either 'X', 'Y', 'SP' or 'PC'.
  10523. "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
  10524. 'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+'
  10525. The number must be in the range '-8'..'+8' and must not be 0. The
  10526. register can be either 'X', 'Y', 'SP' or 'PC'.
  10527. "Accumulator Offset"
  10528. 'ACC,REG'
  10529. The accumulator register can be either 'A', 'B' or 'D'. The
  10530. register can be either 'X', 'Y', 'SP' or 'PC'.
  10531. "Accumulator D offset indexed-indirect"
  10532. '[D,REG]'
  10533. The register can be either 'X', 'Y', 'SP' or 'PC'.
  10534. For example:
  10535. ldab 1024,sp
  10536. ldd [10,x]
  10537. orab 3,+x
  10538. stab -2,y-
  10539. ldx a,pc
  10540. sty [d,sp]
  10541. 
  10542. File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent
  10543. 9.24.3 Symbolic Operand Modifiers
  10544. ---------------------------------
  10545. The assembler supports several modifiers when using symbol addresses in
  10546. 68HC11 and 68HC12 instruction operands. The general syntax is the
  10547. following:
  10548. %modifier(symbol)
  10549. '%addr'
  10550. This modifier indicates to the assembler and linker to use the
  10551. 16-bit physical address corresponding to the symbol. This is
  10552. intended to be used on memory window systems to map a symbol in the
  10553. memory bank window. If the symbol is in a memory expansion part,
  10554. the physical address corresponds to the symbol address within the
  10555. memory bank window. If the symbol is not in a memory expansion
  10556. part, this is the symbol address (using or not using the %addr
  10557. modifier has no effect in that case).
  10558. '%page'
  10559. This modifier indicates to use the memory page number corresponding
  10560. to the symbol. If the symbol is in a memory expansion part, its
  10561. page number is computed by the linker as a number used to map the
  10562. page containing the symbol in the memory bank window. If the
  10563. symbol is not in a memory expansion part, the page number is 0.
  10564. '%hi'
  10565. This modifier indicates to use the 8-bit high part of the physical
  10566. address of the symbol.
  10567. '%lo'
  10568. This modifier indicates to use the 8-bit low part of the physical
  10569. address of the symbol.
  10570. For example a 68HC12 call to a function 'foo_example' stored in
  10571. memory expansion part could be written as follows:
  10572. call %addr(foo_example),%page(foo_example)
  10573. and this is equivalent to
  10574. call foo_example
  10575. And for 68HC11 it could be written as follows:
  10576. ldab #%page(foo_example)
  10577. stab _page_switch
  10578. jsr %addr(foo_example)
  10579. 
  10580. File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent
  10581. 9.24.4 Assembler Directives
  10582. ---------------------------
  10583. The 68HC11 and 68HC12 version of 'as' have the following specific
  10584. assembler directives:
  10585. '.relax'
  10586. The relax directive is used by the 'GNU Compiler' to emit a
  10587. specific relocation to mark a group of instructions for linker
  10588. relaxation. The sequence of instructions within the group must be
  10589. known to the linker so that relaxation can be performed.
  10590. '.mode [mshort|mlong|mshort-double|mlong-double]'
  10591. This directive specifies the ABI. It overrides the '-mshort',
  10592. '-mlong', '-mshort-double' and '-mlong-double' options.
  10593. '.far SYMBOL'
  10594. This directive marks the symbol as a 'far' symbol meaning that it
  10595. uses a 'call/rtc' calling convention as opposed to 'jsr/rts'.
  10596. During a final link, the linker will identify references to the
  10597. 'far' symbol and will verify the proper calling convention.
  10598. '.interrupt SYMBOL'
  10599. This directive marks the symbol as an interrupt entry point. This
  10600. information is then used by the debugger to correctly unwind the
  10601. frame across interrupts.
  10602. '.xrefb SYMBOL'
  10603. This directive is defined for compatibility with the 'Specification
  10604. for Motorola 8 and 16-Bit Assembly Language Input Standard' and is
  10605. ignored.
  10606. 
  10607. File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent
  10608. 9.24.5 Floating Point
  10609. ---------------------
  10610. Packed decimal (P) format floating literals are not supported. Feel
  10611. free to add the code!
  10612. The floating point formats generated by directives are these.
  10613. '.float'
  10614. 'Single' precision floating point constants.
  10615. '.double'
  10616. 'Double' precision floating point constants.
  10617. '.extend'
  10618. '.ldouble'
  10619. 'Extended' precision ('long double') floating point constants.
  10620. 
  10621. File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent
  10622. 9.24.6 Opcodes
  10623. --------------
  10624. * Menu:
  10625. * M68HC11-Branch:: Branch Improvement
  10626. 
  10627. File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes
  10628. 9.24.6.1 Branch Improvement
  10629. ...........................
  10630. Certain pseudo opcodes are permitted for branch instructions. They
  10631. expand to the shortest branch instruction that reach the target.
  10632. Generally these mnemonics are made by prepending 'j' to the start of
  10633. Motorola mnemonic. These pseudo opcodes are not affected by the
  10634. '--short-branches' or '--force-long-branches' options.
  10635. The following table summarizes the pseudo-operations.
  10636. Displacement Width
  10637. +-------------------------------------------------------------+
  10638. | Options |
  10639. | --short-branches --force-long-branches |
  10640. +--------------------------+----------------------------------+
  10641. Op |BYTE WORD | BYTE WORD |
  10642. +--------------------------+----------------------------------+
  10643. bsr | bsr <pc-rel> <error> | jsr <abs> |
  10644. bra | bra <pc-rel> <error> | jmp <abs> |
  10645. jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
  10646. jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
  10647. bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
  10648. jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
  10649. | jmp <abs> | |
  10650. +--------------------------+----------------------------------+
  10651. XX: condition
  10652. NX: negative of condition XX
  10653. 'jbsr'
  10654. 'jbra'
  10655. These are the simplest jump pseudo-operations; they always map to
  10656. one particular machine instruction, depending on the displacement
  10657. to the branch target.
  10658. 'jbXX'
  10659. Here, 'jbXX' stands for an entire family of pseudo-operations,
  10660. where XX is a conditional branch or condition-code test. The full
  10661. list of pseudo-ops in this family is:
  10662. jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
  10663. jbcs jbne jblt jble jbls jbvc jbmi
  10664. For the cases of non-PC relative displacements and long
  10665. displacements, 'as' issues a longer code fragment in terms of NX,
  10666. the opposite condition to XX. For example, for the non-PC relative
  10667. case:
  10668. jbXX foo
  10669. gives
  10670. bNXs oof
  10671. jmp foo
  10672. oof:
  10673. 
  10674. File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
  10675. 9.25 Meta Dependent Features
  10676. ============================
  10677. * Menu:
  10678. * Meta Options:: Options
  10679. * Meta Syntax:: Meta Assembler Syntax
  10680. 
  10681. File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent
  10682. 9.25.1 Options
  10683. --------------
  10684. The Imagination Technologies Meta architecture is implemented in a
  10685. number of versions, with each new version adding new features such as
  10686. instructions and registers. For precise details of what instructions
  10687. each core supports, please see the chip's technical reference manual.
  10688. The following table lists all available Meta options.
  10689. '-mcpu=metac11'
  10690. Generate code for Meta 1.1.
  10691. '-mcpu=metac12'
  10692. Generate code for Meta 1.2.
  10693. '-mcpu=metac21'
  10694. Generate code for Meta 2.1.
  10695. '-mfpu=metac21'
  10696. Allow code to use FPU hardware of Meta 2.1.
  10697. 
  10698. File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent
  10699. 9.25.2 Syntax
  10700. -------------
  10701. * Menu:
  10702. * Meta-Chars:: Special Characters
  10703. * Meta-Regs:: Register Names
  10704. 
  10705. File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax
  10706. 9.25.2.1 Special Characters
  10707. ...........................
  10708. '!' is the line comment character.
  10709. You can use ';' instead of a newline to separate statements.
  10710. Since '$' has no special meaning, you may use it in symbol names.
  10711. 
  10712. File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax
  10713. 9.25.2.2 Register Names
  10714. .......................
  10715. Registers can be specified either using their mnemonic names, such as
  10716. 'D0Re0', or using the unit plus register number separated by a '.', such
  10717. as 'D0.0'.
  10718. 
  10719. File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies
  10720. 9.26 MicroBlaze Dependent Features
  10721. ==================================
  10722. The Xilinx MicroBlaze processor family includes several variants, all
  10723. using the same core instruction set. This chapter covers features of
  10724. the GNU assembler that are specific to the MicroBlaze architecture. For
  10725. details about the MicroBlaze instruction set, please see the 'MicroBlaze
  10726. Processor Reference Guide (UG081)' available at www.xilinx.com.
  10727. * Menu:
  10728. * MicroBlaze Directives:: Directives for MicroBlaze Processors.
  10729. * MicroBlaze Syntax:: Syntax for the MicroBlaze
  10730. 
  10731. File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent
  10732. 9.26.1 Directives
  10733. -----------------
  10734. A number of assembler directives are available for MicroBlaze.
  10735. '.data8 EXPRESSION,...'
  10736. This directive is an alias for '.byte'. Each expression is
  10737. assembled into an eight-bit value.
  10738. '.data16 EXPRESSION,...'
  10739. This directive is an alias for '.hword'. Each expression is
  10740. assembled into an 16-bit value.
  10741. '.data32 EXPRESSION,...'
  10742. This directive is an alias for '.word'. Each expression is
  10743. assembled into an 32-bit value.
  10744. '.ent NAME[,LABEL]'
  10745. This directive is an alias for '.func' denoting the start of
  10746. function NAME at (optional) LABEL.
  10747. '.end NAME[,LABEL]'
  10748. This directive is an alias for '.endfunc' denoting the end of
  10749. function NAME.
  10750. '.gpword LABEL,...'
  10751. This directive is an alias for '.rva'. The resolved address of
  10752. LABEL is stored in the data section.
  10753. '.weakext LABEL'
  10754. Declare that LABEL is a weak external symbol.
  10755. '.rodata'
  10756. Switch to .rodata section. Equivalent to '.section .rodata'
  10757. '.sdata2'
  10758. Switch to .sdata2 section. Equivalent to '.section .sdata2'
  10759. '.sdata'
  10760. Switch to .sdata section. Equivalent to '.section .sdata'
  10761. '.bss'
  10762. Switch to .bss section. Equivalent to '.section .bss'
  10763. '.sbss'
  10764. Switch to .sbss section. Equivalent to '.section .sbss'
  10765. 
  10766. File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent
  10767. 9.26.2 Syntax for the MicroBlaze
  10768. --------------------------------
  10769. * Menu:
  10770. * MicroBlaze-Chars:: Special Characters
  10771. 
  10772. File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax
  10773. 9.26.2.1 Special Characters
  10774. ...........................
  10775. The presence of a '#' on a line indicates the start of a comment that
  10776. extends to the end of the current line.
  10777. If a '#' appears as the first character of a line, the whole line is
  10778. treated as a comment, but in this case the line can also be a logical
  10779. line number directive (*note Comments::) or a preprocessor control
  10780. command (*note Preprocessing::).
  10781. The ';' character can be used to separate statements on the same
  10782. line.
  10783. 
  10784. File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies
  10785. 9.27 MIPS Dependent Features
  10786. ============================
  10787. GNU 'as' for MIPS architectures supports several different MIPS
  10788. processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For
  10789. information about the MIPS instruction set, see 'MIPS RISC
  10790. Architecture', by Kane and Heindrich (Prentice-Hall). For an overview
  10791. of MIPS assembly conventions, see "Appendix D: Assembly Language
  10792. Programming" in the same work.
  10793. * Menu:
  10794. * MIPS Options:: Assembler options
  10795. * MIPS Macros:: High-level assembly macros
  10796. * MIPS Symbol Sizes:: Directives to override the size of symbols
  10797. * MIPS Small Data:: Controlling the use of small data accesses
  10798. * MIPS ISA:: Directives to override the ISA level
  10799. * MIPS assembly options:: Directives to control code generation
  10800. * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
  10801. * MIPS insn:: Directive to mark data as an instruction
  10802. * MIPS FP ABIs:: Marking which FP ABI is in use
  10803. * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
  10804. * MIPS Option Stack:: Directives to save and restore options
  10805. * MIPS ASE Instruction Generation Overrides:: Directives to control
  10806. generation of MIPS ASE instructions
  10807. * MIPS Floating-Point:: Directives to override floating-point options
  10808. * MIPS Syntax:: MIPS specific syntactical considerations
  10809. 
  10810. File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent
  10811. 9.27.1 Assembler options
  10812. ------------------------
  10813. The MIPS configurations of GNU 'as' support these special options:
  10814. '-G NUM'
  10815. Set the "small data" limit to N bytes. The default limit is 8
  10816. bytes. *Note Controlling the use of small data accesses: MIPS
  10817. Small Data.
  10818. '-EB'
  10819. '-EL'
  10820. Any MIPS configuration of 'as' can select big-endian or
  10821. little-endian output at run time (unlike the other GNU development
  10822. tools, which must be configured for one or the other). Use '-EB'
  10823. to select big-endian output, and '-EL' for little-endian.
  10824. '-KPIC'
  10825. Generate SVR4-style PIC. This option tells the assembler to
  10826. generate SVR4-style position-independent macro expansions. It also
  10827. tells the assembler to mark the output file as PIC.
  10828. '-mvxworks-pic'
  10829. Generate VxWorks PIC. This option tells the assembler to generate
  10830. VxWorks-style position-independent macro expansions.
  10831. '-mips1'
  10832. '-mips2'
  10833. '-mips3'
  10834. '-mips4'
  10835. '-mips5'
  10836. '-mips32'
  10837. '-mips32r2'
  10838. '-mips32r3'
  10839. '-mips32r5'
  10840. '-mips32r6'
  10841. '-mips64'
  10842. '-mips64r2'
  10843. '-mips64r3'
  10844. '-mips64r5'
  10845. '-mips64r6'
  10846. Generate code for a particular MIPS Instruction Set Architecture
  10847. level. '-mips1' corresponds to the R2000 and R3000 processors,
  10848. '-mips2' to the R6000 processor, '-mips3' to the R4000 processor,
  10849. and '-mips4' to the R8000 and R10000 processors. '-mips5',
  10850. '-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6',
  10851. '-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6'
  10852. correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
  10853. Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
  10854. Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6
  10855. ISA processors, respectively. You can also switch instruction sets
  10856. during the assembly; see *note Directives to override the ISA
  10857. level: MIPS ISA.
  10858. '-mgp32'
  10859. '-mfp32'
  10860. Some macros have different expansions for 32-bit and 64-bit
  10861. registers. The register sizes are normally inferred from the ISA
  10862. and ABI, but these flags force a certain group of registers to be
  10863. treated as 32 bits wide at all times. '-mgp32' controls the size
  10864. of general-purpose registers and '-mfp32' controls the size of
  10865. floating-point registers.
  10866. The '.set gp=32' and '.set fp=32' directives allow the size of
  10867. registers to be changed for parts of an object. The default value
  10868. is restored by '.set gp=default' and '.set fp=default'.
  10869. On some MIPS variants there is a 32-bit mode flag; when this flag
  10870. is set, 64-bit instructions generate a trap. Also, some 32-bit
  10871. OSes only save the 32-bit registers on a context switch, so it is
  10872. essential never to use the 64-bit registers.
  10873. '-mgp64'
  10874. '-mfp64'
  10875. Assume that 64-bit registers are available. This is provided in
  10876. the interests of symmetry with '-mgp32' and '-mfp32'.
  10877. The '.set gp=64' and '.set fp=64' directives allow the size of
  10878. registers to be changed for parts of an object. The default value
  10879. is restored by '.set gp=default' and '.set fp=default'.
  10880. '-mfpxx'
  10881. Make no assumptions about whether 32-bit or 64-bit floating-point
  10882. registers are available. This is provided to support having
  10883. modules compatible with either '-mfp32' or '-mfp64'. This option
  10884. can only be used with MIPS II and above.
  10885. The '.set fp=xx' directive allows a part of an object to be marked
  10886. as not making assumptions about 32-bit or 64-bit FP registers. The
  10887. default value is restored by '.set fp=default'.
  10888. '-modd-spreg'
  10889. '-mno-odd-spreg'
  10890. Enable use of floating-point operations on odd-numbered
  10891. single-precision registers when supported by the ISA. '-mfpxx'
  10892. implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'
  10893. '-mips16'
  10894. '-no-mips16'
  10895. Generate code for the MIPS 16 processor. This is equivalent to
  10896. putting '.set mips16' at the start of the assembly file.
  10897. '-no-mips16' turns off this option.
  10898. '-mmicromips'
  10899. '-mno-micromips'
  10900. Generate code for the microMIPS processor. This is equivalent to
  10901. putting '.set micromips' at the start of the assembly file.
  10902. '-mno-micromips' turns off this option. This is equivalent to
  10903. putting '.set nomicromips' at the start of the assembly file.
  10904. '-msmartmips'
  10905. '-mno-smartmips'
  10906. Enables the SmartMIPS extensions to the MIPS32 instruction set,
  10907. which provides a number of new instructions which target smartcard
  10908. and cryptographic applications. This is equivalent to putting
  10909. '.set smartmips' at the start of the assembly file.
  10910. '-mno-smartmips' turns off this option.
  10911. '-mips3d'
  10912. '-no-mips3d'
  10913. Generate code for the MIPS-3D Application Specific Extension. This
  10914. tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
  10915. turns off this option.
  10916. '-mdmx'
  10917. '-no-mdmx'
  10918. Generate code for the MDMX Application Specific Extension. This
  10919. tells the assembler to accept MDMX instructions. '-no-mdmx' turns
  10920. off this option.
  10921. '-mdsp'
  10922. '-mno-dsp'
  10923. Generate code for the DSP Release 1 Application Specific Extension.
  10924. This tells the assembler to accept DSP Release 1 instructions.
  10925. '-mno-dsp' turns off this option.
  10926. '-mdspr2'
  10927. '-mno-dspr2'
  10928. Generate code for the DSP Release 2 Application Specific Extension.
  10929. This option implies '-mdsp'. This tells the assembler to accept
  10930. DSP Release 2 instructions. '-mno-dspr2' turns off this option.
  10931. '-mdspr3'
  10932. '-mno-dspr3'
  10933. Generate code for the DSP Release 3 Application Specific Extension.
  10934. This option implies '-mdsp' and '-mdspr2'. This tells the
  10935. assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns
  10936. off this option.
  10937. '-mmt'
  10938. '-mno-mt'
  10939. Generate code for the MT Application Specific Extension. This
  10940. tells the assembler to accept MT instructions. '-mno-mt' turns off
  10941. this option.
  10942. '-mmcu'
  10943. '-mno-mcu'
  10944. Generate code for the MCU Application Specific Extension. This
  10945. tells the assembler to accept MCU instructions. '-mno-mcu' turns
  10946. off this option.
  10947. '-mmsa'
  10948. '-mno-msa'
  10949. Generate code for the MIPS SIMD Architecture Extension. This tells
  10950. the assembler to accept MSA instructions. '-mno-msa' turns off
  10951. this option.
  10952. '-mxpa'
  10953. '-mno-xpa'
  10954. Generate code for the MIPS eXtended Physical Address (XPA)
  10955. Extension. This tells the assembler to accept XPA instructions.
  10956. '-mno-xpa' turns off this option.
  10957. '-mvirt'
  10958. '-mno-virt'
  10959. Generate code for the Virtualization Application Specific
  10960. Extension. This tells the assembler to accept Virtualization
  10961. instructions. '-mno-virt' turns off this option.
  10962. '-minsn32'
  10963. '-mno-insn32'
  10964. Only use 32-bit instruction encodings when generating code for the
  10965. microMIPS processor. This option inhibits the use of any 16-bit
  10966. instructions. This is equivalent to putting '.set insn32' at the
  10967. start of the assembly file. '-mno-insn32' turns off this option.
  10968. This is equivalent to putting '.set noinsn32' at the start of the
  10969. assembly file. By default '-mno-insn32' is selected, allowing all
  10970. instructions to be used.
  10971. '-mfix7000'
  10972. '-mno-fix7000'
  10973. Cause nops to be inserted if the read of the destination register
  10974. of an mfhi or mflo instruction occurs in the following two
  10975. instructions.
  10976. '-mfix-rm7000'
  10977. '-mno-fix-rm7000'
  10978. Cause nops to be inserted if a dmult or dmultu instruction is
  10979. followed by a load instruction.
  10980. '-mfix-loongson2f-jump'
  10981. '-mno-fix-loongson2f-jump'
  10982. Eliminate instruction fetch from outside 256M region to work around
  10983. the Loongson2F 'jump' instructions. Without it, under extreme
  10984. cases, the kernel may crash. The issue has been solved in latest
  10985. processor batches, but this fix has no side effect to them.
  10986. '-mfix-loongson2f-nop'
  10987. '-mno-fix-loongson2f-nop'
  10988. Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop'
  10989. errata. Without it, under extreme cases, the CPU might deadlock.
  10990. The issue has been solved in later Loongson2F batches, but this fix
  10991. has no side effect to them.
  10992. '-mfix-vr4120'
  10993. '-mno-fix-vr4120'
  10994. Insert nops to work around certain VR4120 errata. This option is
  10995. intended to be used on GCC-generated code: it is not designed to
  10996. catch all problems in hand-written assembler code.
  10997. '-mfix-vr4130'
  10998. '-mno-fix-vr4130'
  10999. Insert nops to work around the VR4130 'mflo'/'mfhi' errata.
  11000. '-mfix-24k'
  11001. '-mno-fix-24k'
  11002. Insert nops to work around the 24K 'eret'/'deret' errata.
  11003. '-mfix-cn63xxp1'
  11004. '-mno-fix-cn63xxp1'
  11005. Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
  11006. certain CN63XXP1 errata.
  11007. '-m4010'
  11008. '-no-m4010'
  11009. Generate code for the LSI R4010 chip. This tells the assembler to
  11010. accept the R4010-specific instructions ('addciu', 'ffc', etc.), and
  11011. to not schedule 'nop' instructions around accesses to the 'HI' and
  11012. 'LO' registers. '-no-m4010' turns off this option.
  11013. '-m4650'
  11014. '-no-m4650'
  11015. Generate code for the MIPS R4650 chip. This tells the assembler to
  11016. accept the 'mad' and 'madu' instruction, and to not schedule 'nop'
  11017. instructions around accesses to the 'HI' and 'LO' registers.
  11018. '-no-m4650' turns off this option.
  11019. '-m3900'
  11020. '-no-m3900'
  11021. '-m4100'
  11022. '-no-m4100'
  11023. For each option '-mNNNN', generate code for the MIPS RNNNN chip.
  11024. This tells the assembler to accept instructions specific to that
  11025. chip, and to schedule for that chip's hazards.
  11026. '-march=CPU'
  11027. Generate code for a particular MIPS CPU. It is exactly equivalent
  11028. to '-mCPU', except that there are more value of CPU understood.
  11029. Valid CPU value are:
  11030. 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
  11031. vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
  11032. rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
  11033. 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
  11034. 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
  11035. 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
  11036. 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
  11037. 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1,
  11038. interaptiv, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1,
  11039. sb1a, i6400, p6600, loongson2e, loongson2f, loongson3a,
  11040. octeon, octeon+, octeon2, octeon3, xlr, xlp
  11041. For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms
  11042. for 'Nf1_1'. These values are deprecated.
  11043. '-mtune=CPU'
  11044. Schedule and tune for a particular MIPS CPU. Valid CPU values are
  11045. identical to '-march=CPU'.
  11046. '-mabi=ABI'
  11047. Record which ABI the source code uses. The recognized arguments
  11048. are: '32', 'n32', 'o64', '64' and 'eabi'.
  11049. '-msym32'
  11050. '-mno-sym32'
  11051. Equivalent to adding '.set sym32' or '.set nosym32' to the
  11052. beginning of the assembler input. *Note MIPS Symbol Sizes::.
  11053. '-nocpp'
  11054. This option is ignored. It is accepted for command-line
  11055. compatibility with other assemblers, which use it to turn off C
  11056. style preprocessing. With GNU 'as', there is no need for '-nocpp',
  11057. because the GNU assembler itself never runs the C preprocessor.
  11058. '-msoft-float'
  11059. '-mhard-float'
  11060. Disable or enable floating-point instructions. Note that by
  11061. default floating-point instructions are always allowed even with
  11062. CPU targets that don't have support for these instructions.
  11063. '-msingle-float'
  11064. '-mdouble-float'
  11065. Disable or enable double-precision floating-point operations. Note
  11066. that by default double-precision floating-point operations are
  11067. always allowed even with CPU targets that don't have support for
  11068. these operations.
  11069. '--construct-floats'
  11070. '--no-construct-floats'
  11071. The '--no-construct-floats' option disables the construction of
  11072. double width floating point constants by loading the two halves of
  11073. the value into the two single width floating point registers that
  11074. make up the double width register. This feature is useful if the
  11075. processor support the FR bit in its status register, and this bit
  11076. is known (by the programmer) to be set. This bit prevents the
  11077. aliasing of the double width register by the single width
  11078. registers.
  11079. By default '--construct-floats' is selected, allowing construction
  11080. of these floating point constants.
  11081. '--relax-branch'
  11082. '--no-relax-branch'
  11083. The '--relax-branch' option enables the relaxation of out-of-range
  11084. branches. Any branches whose target cannot be reached directly are
  11085. converted to a small instruction sequence including an
  11086. inverse-condition branch to the physically next instruction, and a
  11087. jump to the original target is inserted between the two
  11088. instructions. In PIC code the jump will involve further
  11089. instructions for address calculation.
  11090. The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and
  11091. 'BPOSGE64' instructions are excluded from relaxation, because they
  11092. have no complementing counterparts. They could be relaxed with the
  11093. use of a longer sequence involving another branch, however this has
  11094. not been implemented and if their target turns out of reach, they
  11095. produce an error even if branch relaxation is enabled.
  11096. Also no MIPS16 branches are ever relaxed.
  11097. By default '--no-relax-branch' is selected, causing any
  11098. out-of-range branches to produce an error.
  11099. '-mignore-branch-isa'
  11100. '-mno-ignore-branch-isa'
  11101. Ignore branch checks for invalid transitions between ISA modes.
  11102. The semantics of branches does not provide for an ISA mode switch,
  11103. so in most cases the ISA mode a branch has been encoded for has to
  11104. be the same as the ISA mode of the branch's target label. If the
  11105. ISA modes do not match, then such a branch, if taken, will cause
  11106. the ISA mode to remain unchanged and instructions that follow will
  11107. be executed in the wrong ISA mode causing the program to misbehave
  11108. or crash.
  11109. In the case of the 'BAL' instruction it may be possible to relax it
  11110. to an equivalent 'JALX' instruction so that the ISA mode is
  11111. switched at the run time as required. For other branches no
  11112. relaxation is possible and therefore GAS has checks implemented
  11113. that verify in branch assembly that the two ISA modes match, and
  11114. report an error otherwise so that the problem with code can be
  11115. diagnosed at the assembly time rather than at the run time.
  11116. However some assembly code, including generated code produced by
  11117. some versions of GCC, may incorrectly include branches to data
  11118. labels, which appear to require a mode switch but are either dead
  11119. or immediately followed by valid instructions encoded for the same
  11120. ISA the branch has been encoded for. While not strictly correct at
  11121. the source level such code will execute as intended, so to help
  11122. with these cases '-mignore-branch-isa' is supported which disables
  11123. ISA mode checks for branches.
  11124. By default '-mno-ignore-branch-isa' is selected, causing any
  11125. invalid branch requiring a transition between ISA modes to produce
  11126. an error.
  11127. '-mnan=ENCODING'
  11128. This option indicates whether the source code uses the IEEE 2008
  11129. NaN encoding ('-mnan=2008') or the original MIPS encoding
  11130. ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to
  11131. the beginning of the source file. *Note MIPS NaN Encodings::.
  11132. '-mnan=legacy' is the default if no '-mnan' option or '.nan'
  11133. directive is used.
  11134. '--trap'
  11135. '--no-break'
  11136. 'as' automatically macro expands certain division and
  11137. multiplication instructions to check for overflow and division by
  11138. zero. This option causes 'as' to generate code to take a trap
  11139. exception rather than a break exception when an error is detected.
  11140. The trap instructions are only supported at Instruction Set
  11141. Architecture level 2 and higher.
  11142. '--break'
  11143. '--no-trap'
  11144. Generate code to take a break exception rather than a trap
  11145. exception when an error is detected. This is the default.
  11146. '-mpdr'
  11147. '-mno-pdr'
  11148. Control generation of '.pdr' sections. Off by default on IRIX, on
  11149. elsewhere.
  11150. '-mshared'
  11151. '-mno-shared'
  11152. When generating code using the Unix calling conventions (selected
  11153. by '-KPIC' or '-mcall_shared'), gas will normally generate code
  11154. which can go into a shared library. The '-mno-shared' option tells
  11155. gas to generate code which uses the calling convention, but can not
  11156. go into a shared library. The resulting code is slightly more
  11157. efficient. This option only affects the handling of the '.cpload'
  11158. and '.cpsetup' pseudo-ops.
  11159. 
  11160. File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent
  11161. 9.27.2 High-level assembly macros
  11162. ---------------------------------
  11163. MIPS assemblers have traditionally provided a wider range of
  11164. instructions than the MIPS architecture itself. These extra
  11165. instructions are usually referred to as "macro" instructions (1).
  11166. Some MIPS macro instructions extend an underlying architectural
  11167. instruction while others are entirely new. An example of the former
  11168. type is 'and', which allows the third operand to be either a register or
  11169. an arbitrary immediate value. Examples of the latter type include
  11170. 'bgt', which branches to the third operand when the first operand is
  11171. greater than the second operand, and 'ulh', which implements an
  11172. unaligned 2-byte load.
  11173. One of the most common extensions provided by macros is to expand
  11174. memory offsets to the full address range (32 or 64 bits) and to allow
  11175. symbolic offsets such as 'my_data + 4' to be used in place of integer
  11176. constants. For example, the architectural instruction 'lbu' allows only
  11177. a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu
  11178. $4,array+32769($5)'. The implementation of these symbolic offsets
  11179. depends on several factors, such as whether the assembler is generating
  11180. SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS
  11181. Options.), the size of symbols (*note Directives to override the size of
  11182. symbols: MIPS Symbol Sizes.), and the small data limit (*note
  11183. Controlling the use of small data accesses: MIPS Small Data.).
  11184. Sometimes it is undesirable to have one assembly instruction expand
  11185. to several machine instructions. The directive '.set nomacro' tells the
  11186. assembler to warn when this happens. '.set macro' restores the default
  11187. behavior.
  11188. Some macro instructions need a temporary register to store
  11189. intermediate results. This register is usually '$1', also known as
  11190. '$at', but it can be changed to any core register REG using '.set
  11191. at=REG'. Note that '$at' always refers to '$1' regardless of which
  11192. register is being used as the temporary register.
  11193. Implicit uses of the temporary register in macros could interfere
  11194. with explicit uses in the assembly code. The assembler therefore warns
  11195. whenever it sees an explicit use of the temporary register. The
  11196. directive '.set noat' silences this warning while '.set at' restores the
  11197. default behavior. It is safe to use '.set noat' while '.set nomacro' is
  11198. in effect since single-instruction macros never need a temporary
  11199. register.
  11200. Note that while the GNU assembler provides these macros for
  11201. compatibility, it does not make any attempt to optimize them with the
  11202. surrounding code.
  11203. ---------- Footnotes ----------
  11204. (1) The term "macro" is somewhat overloaded here, since these macros
  11205. have no relation to those defined by '.macro', *note '.macro': Macro.
  11206. 
  11207. File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent
  11208. 9.27.3 Directives to override the size of symbols
  11209. -------------------------------------------------
  11210. The n64 ABI allows symbols to have any 64-bit value. Although this
  11211. provides a great deal of flexibility, it means that some macros have
  11212. much longer expansions than their 32-bit counterparts. For example, the
  11213. non-PIC expansion of 'dla $4,sym' is usually:
  11214. lui $4,%highest(sym)
  11215. lui $1,%hi(sym)
  11216. daddiu $4,$4,%higher(sym)
  11217. daddiu $1,$1,%lo(sym)
  11218. dsll32 $4,$4,0
  11219. daddu $4,$4,$1
  11220. whereas the 32-bit expansion is simply:
  11221. lui $4,%hi(sym)
  11222. daddiu $4,$4,%lo(sym)
  11223. n64 code is sometimes constructed in such a way that all symbolic
  11224. constants are known to have 32-bit values, and in such cases, it's
  11225. preferable to use the 32-bit expansion instead of the 64-bit expansion.
  11226. You can use the '.set sym32' directive to tell the assembler that,
  11227. from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL +
  11228. OFFSET' have 32-bit values. For example:
  11229. .set sym32
  11230. dla $4,sym
  11231. lw $4,sym+16
  11232. sw $4,sym+0x8000($4)
  11233. will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as
  11234. 32-bit values. The handling of non-symbolic addresses is not affected.
  11235. The directive '.set nosym32' ends a '.set sym32' block and reverts to
  11236. the normal behavior. It is also possible to change the symbol size
  11237. using the command-line options '-msym32' and '-mno-sym32'.
  11238. These options and directives are always accepted, but at present,
  11239. they have no effect for anything other than n64.
  11240. 
  11241. File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent
  11242. 9.27.4 Controlling the use of small data accesses
  11243. -------------------------------------------------
  11244. It often takes several instructions to load the address of a symbol.
  11245. For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of
  11246. 'dla $4,addr' is usually:
  11247. lui $4,%hi(addr)
  11248. daddiu $4,$4,%lo(addr)
  11249. The sequence is much longer when 'addr' is a 64-bit symbol. *Note
  11250. Directives to override the size of symbols: MIPS Symbol Sizes.
  11251. In order to cut down on this overhead, most embedded MIPS systems set
  11252. aside a 64-kilobyte "small data" area and guarantee that all data of
  11253. size N and smaller will be placed in that area. The limit N is passed
  11254. to both the assembler and the linker using the command-line option '-G
  11255. N', *note Assembler options: MIPS Options. Note that the same value of
  11256. N must be used when linking and when assembling all input files to the
  11257. link; any inconsistency could cause a relocation overflow error.
  11258. The size of an object in the '.bss' section is set by the '.comm' or
  11259. '.lcomm' directive that defines it. The size of an external object may
  11260. be set with the '.extern' directive. For example, '.extern sym,4'
  11261. declares that the object at 'sym' is 4 bytes in length, while leaving
  11262. 'sym' otherwise undefined.
  11263. When no '-G' option is given, the default limit is 8 bytes. The
  11264. option '-G 0' prevents any data from being automatically classified as
  11265. small.
  11266. It is also possible to mark specific objects as small by putting them
  11267. in the special sections '.sdata' and '.sbss', which are "small"
  11268. counterparts of '.data' and '.bss' respectively. The toolchain will
  11269. treat such data as small regardless of the '-G' setting.
  11270. On startup, systems that support a small data area are expected to
  11271. initialize register '$28', also known as '$gp', in such a way that small
  11272. data can be accessed using a 16-bit offset from that register. For
  11273. example, when 'addr' is small data, the 'dla $4,addr' instruction above
  11274. is equivalent to:
  11275. daddiu $4,$28,%gp_rel(addr)
  11276. Small data is not supported for SVR4-style PIC.
  11277. 
  11278. File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent
  11279. 9.27.5 Directives to override the ISA level
  11280. -------------------------------------------
  11281. GNU 'as' supports an additional directive to change the MIPS Instruction
  11282. Set Architecture level on the fly: '.set mipsN'. N should be a number
  11283. from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or
  11284. 64r6. The values other than 0 make the assembler accept instructions
  11285. for the corresponding ISA level, from that point on in the assembly.
  11286. '.set mipsN' affects not only which instructions are permitted, but also
  11287. how certain macros are expanded. '.set mips0' restores the ISA level to
  11288. its original level: either the level you selected with command line
  11289. options, or the default for your configuration. You can use this
  11290. feature to permit specific MIPS III instructions while assembling in 32
  11291. bit mode. Use this directive with care!
  11292. The '.set arch=CPU' directive provides even finer control. It
  11293. changes the effective CPU target and allows the assembler to use
  11294. instructions specific to a particular CPU. All CPUs supported by the
  11295. '-march' command line option are also selectable by this directive. The
  11296. original value is restored by '.set arch=default'.
  11297. The directive '.set mips16' puts the assembler into MIPS 16 mode, in
  11298. which it will assemble instructions for the MIPS 16 processor. Use
  11299. '.set nomips16' to return to normal 32 bit mode.
  11300. Traditional MIPS assemblers do not support this directive.
  11301. The directive '.set micromips' puts the assembler into microMIPS
  11302. mode, in which it will assemble instructions for the microMIPS
  11303. processor. Use '.set nomicromips' to return to normal 32 bit mode.
  11304. Traditional MIPS assemblers do not support this directive.
  11305. 
  11306. File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent
  11307. 9.27.6 Directives to control code generation
  11308. --------------------------------------------
  11309. The '.module' directive allows command line options to be set directly
  11310. from assembly. The format of the directive matches the '.set' directive
  11311. but only those options which are relevant to a whole module are
  11312. supported. The effect of a '.module' directive is the same as the
  11313. corresponding command line option. Where '.set' directives support
  11314. returning to a default then the '.module' directives do not as they
  11315. define the defaults.
  11316. These module-level directives must appear first in assembly.
  11317. Traditional MIPS assemblers do not support this directive.
  11318. The directive '.set insn32' makes the assembler only use 32-bit
  11319. instruction encodings when generating code for the microMIPS processor.
  11320. This directive inhibits the use of any 16-bit instructions from that
  11321. point on in the assembly. The '.set noinsn32' directive allows 16-bit
  11322. instructions to be accepted.
  11323. Traditional MIPS assemblers do not support this directive.
  11324. 
  11325. File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent
  11326. 9.27.7 Directives for extending MIPS 16 bit instructions
  11327. --------------------------------------------------------
  11328. By default, MIPS 16 instructions are automatically extended to 32 bits
  11329. when necessary. The directive '.set noautoextend' will turn this off.
  11330. When '.set noautoextend' is in effect, any 32 bit instruction must be
  11331. explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The
  11332. directive '.set autoextend' may be used to once again automatically
  11333. extend instructions when necessary.
  11334. This directive is only meaningful when in MIPS 16 mode. Traditional
  11335. MIPS assemblers do not support this directive.
  11336. 
  11337. File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent
  11338. 9.27.8 Directive to mark data as an instruction
  11339. -----------------------------------------------
  11340. The '.insn' directive tells 'as' that the following data is actually
  11341. instructions. This makes a difference in MIPS 16 and microMIPS modes:
  11342. when loading the address of a label which precedes instructions, 'as'
  11343. automatically adds 1 to the value, so that jumping to the loaded address
  11344. will do the right thing.
  11345. The '.global' and '.globl' directives supported by 'as' will by
  11346. default mark the symbol as pointing to a region of data not code. This
  11347. means that, for example, any instructions following such a symbol will
  11348. not be disassembled by 'objdump' as it will regard them as data. To
  11349. change this behavior an optional section name can be placed after the
  11350. symbol name in the '.global' directive. If this section exists and is
  11351. known to be a code section, then the symbol will be marked as pointing
  11352. at code not data. Ie the syntax for the directive is:
  11353. '.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
  11354. Here is a short example:
  11355. .global foo .text, bar, baz .data
  11356. foo:
  11357. nop
  11358. bar:
  11359. .word 0x0
  11360. baz:
  11361. .word 0x1
  11362. 
  11363. File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent
  11364. 9.27.9 Directives to control the FP ABI
  11365. ---------------------------------------
  11366. * Menu:
  11367. * MIPS FP ABI History:: History of FP ABIs
  11368. * MIPS FP ABI Variants:: Supported FP ABIs
  11369. * MIPS FP ABI Selection:: Automatic selection of FP ABI
  11370. * MIPS FP ABI Compatibility:: Linking different FP ABI variants
  11371. 
  11372. File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs
  11373. 9.27.9.1 History of FP ABIs
  11374. ...........................
  11375. The MIPS ABIs support a variety of different floating-point extensions
  11376. where calling-convention and register sizes vary for floating-point
  11377. data. The extensions exist to support a wide variety of optional
  11378. architecture features. The resulting ABI variants are generally
  11379. incompatible with each other and must be tracked carefully.
  11380. Traditionally the use of an explicit '.gnu_attribute 4, N' directive
  11381. is used to indicate which ABI is in use by a specific module. It was
  11382. then left to the user to ensure that command line options and the
  11383. selected ABI were compatible with some potential for inconsistencies.
  11384. 
  11385. File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs
  11386. 9.27.9.2 Supported FP ABIs
  11387. ..........................
  11388. The supported floating-point ABI variants are:
  11389. '0 - No floating-point'
  11390. This variant is used to indicate that floating-point is not used
  11391. within the module at all and therefore has no impact on the ABI.
  11392. This is the default.
  11393. '1 - Double-precision'
  11394. This variant indicates that double-precision support is used. For
  11395. 64-bit ABIs this means that 64-bit wide floating-point registers
  11396. are required. For 32-bit ABIs this means that 32-bit wide
  11397. floating-point registers are required and double-precision
  11398. operations use pairs of registers.
  11399. '2 - Single-precision'
  11400. This variant indicates that single-precision support is used.
  11401. Double precision operations will be supported via soft-float
  11402. routines.
  11403. '3 - Soft-float'
  11404. This variant indicates that although floating-point support is used
  11405. all operations are emulated in software. This means the ABI is
  11406. modified to pass all floating-point data in general-purpose
  11407. registers.
  11408. '4 - Deprecated'
  11409. This variant existed as an initial attempt at supporting 64-bit
  11410. wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This
  11411. has been superseded by 5, 6 and 7.
  11412. '5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU'
  11413. This variant is used by 32-bit ABIs to indicate that the
  11414. floating-point code in the module has been designed to operate
  11415. correctly with either 32-bit wide or 64-bit wide floating-point
  11416. registers. Double-precision support is used. Only O32 currently
  11417. supports this variant and requires a minimum architecture of MIPS
  11418. II.
  11419. '6 - Double-precision 32-bit FPU, 64-bit FPU'
  11420. This variant is used by 32-bit ABIs to indicate that the
  11421. floating-point code in the module requires 64-bit wide
  11422. floating-point registers. Double-precision support is used. Only
  11423. O32 currently supports this variant and requires a minimum
  11424. architecture of MIPS32r2.
  11425. '7 - Double-precision compat 32-bit FPU, 64-bit FPU'
  11426. This variant is used by 32-bit ABIs to indicate that the
  11427. floating-point code in the module requires 64-bit wide
  11428. floating-point registers. Double-precision support is used. This
  11429. differs from the previous ABI as it restricts use of odd-numbered
  11430. single-precision registers. Only O32 currently supports this
  11431. variant and requires a minimum architecture of MIPS32r2.
  11432. 
  11433. File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs
  11434. 9.27.9.3 Automatic selection of FP ABI
  11435. ......................................
  11436. In order to simplify and add safety to the process of selecting the
  11437. correct floating-point ABI, the assembler will automatically infer the
  11438. correct '.gnu_attribute 4, N' directive based on command line options
  11439. and '.module' overrides. Where an explicit '.gnu_attribute 4, N'
  11440. directive has been seen then a warning will be raised if it does not
  11441. match an inferred setting.
  11442. The floating-point ABI is inferred as follows. If '-msoft-float' has
  11443. been used the module will be marked as soft-float. If '-msingle-float'
  11444. has been used then the module will be marked as single-precision. The
  11445. remaining ABIs are then selected based on the FP register width.
  11446. Double-precision is selected if the width of GP and FP registers match
  11447. and the special double-precision variants for 32-bit ABIs are then
  11448. selected depending on '-mfpxx', '-mfp64' and '-mno-odd-spreg'.
  11449. 
  11450. File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs
  11451. 9.27.9.4 Linking different FP ABI variants
  11452. ..........................................
  11453. Modules using the default FP ABI (no floating-point) can be linked with
  11454. any other (singular) FP ABI variant.
  11455. Special compatibility support exists for O32 with the four
  11456. double-precision FP ABI variants. The '-mfpxx' FP ABI is specifically
  11457. designed to be compatible with the standard double-precision ABI and the
  11458. '-mfp64' FP ABIs. This makes it desirable for O32 modules to be built
  11459. as '-mfpxx' to ensure the maximum compatibility with other modules
  11460. produced for more specific needs. The only FP ABIs which cannot be
  11461. linked together are the standard double-precision ABI and the full
  11462. '-mfp64' ABI with '-modd-spreg'.
  11463. 
  11464. File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent
  11465. 9.27.10 Directives to record which NaN encoding is being used
  11466. -------------------------------------------------------------
  11467. The IEEE 754 floating-point standard defines two types of not-a-number
  11468. (NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of
  11469. the standard did not specify how these two types should be
  11470. distinguished. Most implementations followed the i387 model, in which
  11471. the first bit of the significand is set for quiet NaNs and clear for
  11472. signalling NaNs. However, the original MIPS implementation assigned the
  11473. opposite meaning to the bit, so that it was set for signalling NaNs and
  11474. clear for quiet NaNs.
  11475. The 2008 revision of the standard formally suggested the i387 choice
  11476. and as from Sep 2012 the current release of the MIPS architecture
  11477. therefore optionally supports that form. Code that uses one NaN
  11478. encoding would usually be incompatible with code that uses the other NaN
  11479. encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record
  11480. which encoding is being used.
  11481. Assembly files can use the '.nan' directive to select between the two
  11482. encodings. '.nan 2008' says that the assembly file uses the IEEE
  11483. 754-2008 encoding while '.nan legacy' says that the file uses the
  11484. original MIPS encoding. If several '.nan' directives are given, the
  11485. final setting is the one that is used.
  11486. The command-line options '-mnan=legacy' and '-mnan=2008' can be used
  11487. instead of '.nan legacy' and '.nan 2008' respectively. However, any
  11488. '.nan' directive overrides the command-line setting.
  11489. '.nan legacy' is the default if no '.nan' directive or '-mnan' option
  11490. is given.
  11491. Note that GNU 'as' does not produce NaNs itself and therefore these
  11492. directives do not affect code generation. They simply control the
  11493. setting of the 'EF_MIPS_NAN2008' flag.
  11494. Traditional MIPS assemblers do not support these directives.
  11495. 
  11496. File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent
  11497. 9.27.11 Directives to save and restore options
  11498. ----------------------------------------------
  11499. The directives '.set push' and '.set pop' may be used to save and
  11500. restore the current settings for all the options which are controlled by
  11501. '.set'. The '.set push' directive saves the current settings on a
  11502. stack. The '.set pop' directive pops the stack and restores the
  11503. settings.
  11504. These directives can be useful inside an macro which must change an
  11505. option such as the ISA level or instruction reordering but does not want
  11506. to change the state of the code which invoked the macro.
  11507. Traditional MIPS assemblers do not support these directives.
  11508. 
  11509. File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent
  11510. 9.27.12 Directives to control generation of MIPS ASE instructions
  11511. -----------------------------------------------------------------
  11512. The directive '.set mips3d' makes the assembler accept instructions from
  11513. the MIPS-3D Application Specific Extension from that point on in the
  11514. assembly. The '.set nomips3d' directive prevents MIPS-3D instructions
  11515. from being accepted.
  11516. The directive '.set smartmips' makes the assembler accept
  11517. instructions from the SmartMIPS Application Specific Extension to the
  11518. MIPS32 ISA from that point on in the assembly. The '.set nosmartmips'
  11519. directive prevents SmartMIPS instructions from being accepted.
  11520. The directive '.set mdmx' makes the assembler accept instructions
  11521. from the MDMX Application Specific Extension from that point on in the
  11522. assembly. The '.set nomdmx' directive prevents MDMX instructions from
  11523. being accepted.
  11524. The directive '.set dsp' makes the assembler accept instructions from
  11525. the DSP Release 1 Application Specific Extension from that point on in
  11526. the assembly. The '.set nodsp' directive prevents DSP Release 1
  11527. instructions from being accepted.
  11528. The directive '.set dspr2' makes the assembler accept instructions
  11529. from the DSP Release 2 Application Specific Extension from that point on
  11530. in the assembly. This directive implies '.set dsp'. The '.set nodspr2'
  11531. directive prevents DSP Release 2 instructions from being accepted.
  11532. The directive '.set dspr3' makes the assembler accept instructions
  11533. from the DSP Release 3 Application Specific Extension from that point on
  11534. in the assembly. This directive implies '.set dsp' and '.set dspr2'.
  11535. The '.set nodspr3' directive prevents DSP Release 3 instructions from
  11536. being accepted.
  11537. The directive '.set mt' makes the assembler accept instructions from
  11538. the MT Application Specific Extension from that point on in the
  11539. assembly. The '.set nomt' directive prevents MT instructions from being
  11540. accepted.
  11541. The directive '.set mcu' makes the assembler accept instructions from
  11542. the MCU Application Specific Extension from that point on in the
  11543. assembly. The '.set nomcu' directive prevents MCU instructions from
  11544. being accepted.
  11545. The directive '.set msa' makes the assembler accept instructions from
  11546. the MIPS SIMD Architecture Extension from that point on in the assembly.
  11547. The '.set nomsa' directive prevents MSA instructions from being
  11548. accepted.
  11549. The directive '.set virt' makes the assembler accept instructions
  11550. from the Virtualization Application Specific Extension from that point
  11551. on in the assembly. The '.set novirt' directive prevents Virtualization
  11552. instructions from being accepted.
  11553. The directive '.set xpa' makes the assembler accept instructions from
  11554. the XPA Extension from that point on in the assembly. The '.set noxpa'
  11555. directive prevents XPA instructions from being accepted.
  11556. Traditional MIPS assemblers do not support these directives.
  11557. 
  11558. File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent
  11559. 9.27.13 Directives to override floating-point options
  11560. -----------------------------------------------------
  11561. The directives '.set softfloat' and '.set hardfloat' provide finer
  11562. control of disabling and enabling float-point instructions. These
  11563. directives always override the default (that hard-float instructions are
  11564. accepted) or the command-line options ('-msoft-float' and
  11565. '-mhard-float').
  11566. The directives '.set singlefloat' and '.set doublefloat' provide
  11567. finer control of disabling and enabling double-precision float-point
  11568. operations. These directives always override the default (that
  11569. double-precision operations are accepted) or the command-line options
  11570. ('-msingle-float' and '-mdouble-float').
  11571. Traditional MIPS assemblers do not support these directives.
  11572. 
  11573. File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent
  11574. 9.27.14 Syntactical considerations for the MIPS assembler
  11575. ---------------------------------------------------------
  11576. * Menu:
  11577. * MIPS-Chars:: Special Characters
  11578. 
  11579. File: as.info, Node: MIPS-Chars, Up: MIPS Syntax
  11580. 9.27.14.1 Special Characters
  11581. ............................
  11582. The presence of a '#' on a line indicates the start of a comment that
  11583. extends to the end of the current line.
  11584. If a '#' appears as the first character of a line, the whole line is
  11585. treated as a comment, but in this case the line can also be a logical
  11586. line number directive (*note Comments::) or a preprocessor control
  11587. command (*note Preprocessing::).
  11588. The ';' character can be used to separate statements on the same
  11589. line.
  11590. 
  11591. File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
  11592. 9.28 MMIX Dependent Features
  11593. ============================
  11594. * Menu:
  11595. * MMIX-Opts:: Command-line Options
  11596. * MMIX-Expand:: Instruction expansion
  11597. * MMIX-Syntax:: Syntax
  11598. * MMIX-mmixal:: Differences to 'mmixal' syntax and semantics
  11599. 
  11600. File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent
  11601. 9.28.1 Command-line Options
  11602. ---------------------------
  11603. The MMIX version of 'as' has some machine-dependent options.
  11604. When '--fixed-special-register-names' is specified, only the register
  11605. names specified in *note MMIX-Regs:: are recognized in the instructions
  11606. 'PUT' and 'GET'.
  11607. You can use the '--globalize-symbols' to make all symbols global.
  11608. This option is useful when splitting up a 'mmixal' program into several
  11609. files.
  11610. The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'.
  11611. Its usability is currently doubtful.
  11612. The '--relax' option is not fully supported, but will eventually make
  11613. the object file prepared for linker relaxation.
  11614. If you want to avoid inadvertently calling a predefined symbol and
  11615. would rather get an error, for example when using 'as' with a compiler
  11616. or other machine-generated code, specify '--no-predefined-syms'. This
  11617. turns off built-in predefined definitions of all such symbols, including
  11618. rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP'
  11619. symbols used in 'mmix' "system calls". It also turns off predefined
  11620. special-register names, except when used in 'PUT' and 'GET'
  11621. instructions.
  11622. By default, some instructions are expanded to fit the size of the
  11623. operand or an external symbol (*note MMIX-Expand::). By passing
  11624. '--no-expand', no such expansion will be done, instead causing errors at
  11625. link time if the operand does not fit.
  11626. The 'mmixal' documentation (*note mmixsite::) specifies that global
  11627. registers allocated with the 'GREG' directive (*note MMIX-greg::) and
  11628. initialized to the same non-zero value, will refer to the same global
  11629. register. This isn't strictly enforceable in 'as' since the final
  11630. addresses aren't known until link-time, but it will do an effort unless
  11631. the '--no-merge-gregs' option is specified. (Register merging isn't yet
  11632. implemented in 'ld'.)
  11633. 'as' will warn every time it expands an instruction to fit an operand
  11634. unless the option '-x' is specified. It is believed that this behaviour
  11635. is more useful than just mimicking 'mmixal''s behaviour, in which
  11636. instructions are only expanded if the '-x' option is specified, and
  11637. assembly fails otherwise, when an instruction needs to be expanded. It
  11638. needs to be kept in mind that 'mmixal' is both an assembler and linker,
  11639. while 'as' will expand instructions that at link stage can be
  11640. contracted. (Though linker relaxation isn't yet implemented in 'ld'.)
  11641. The option '-x' also imples '--linker-allocated-gregs'.
  11642. If instruction expansion is enabled, 'as' can expand a 'PUSHJ'
  11643. instruction into a series of instructions. The shortest expansion is to
  11644. not expand it, but just mark the call as redirectable to a stub, which
  11645. 'ld' creates at link-time, but only if the original 'PUSHJ' instruction
  11646. is found not to reach the target. The stub consists of the necessary
  11647. instructions to form a jump to the target. This happens if 'as' can
  11648. assert that the 'PUSHJ' instruction can reach such a stub. The option
  11649. '--no-pushj-stubs' disables this shorter expansion, and the longer
  11650. series of instructions is then created at assembly-time. The option
  11651. '--no-stubs' is a synonym, intended for compatibility with future
  11652. releases, where generation of stubs for other instructions may be
  11653. implemented.
  11654. Usually a two-operand-expression (*note GREG-base::) without a
  11655. matching 'GREG' directive is treated as an error by 'as'. When the
  11656. option '--linker-allocated-gregs' is in effect, they are instead passed
  11657. through to the linker, which will allocate as many global registers as
  11658. is needed.
  11659. 
  11660. File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent
  11661. 9.28.2 Instruction expansion
  11662. ----------------------------
  11663. When 'as' encounters an instruction with an operand that is either not
  11664. known or does not fit the operand size of the instruction, 'as' (and
  11665. 'ld') will expand the instruction into a sequence of instructions
  11666. semantically equivalent to the operand fitting the instruction.
  11667. Expansion will take place for the following instructions:
  11668. 'GETA'
  11669. Expands to a sequence of four instructions: 'SETL', 'INCML',
  11670. 'INCMH' and 'INCH'. The operand must be a multiple of four.
  11671. Conditional branches
  11672. A branch instruction is turned into a branch with the complemented
  11673. condition and prediction bit over five instructions; four
  11674. instructions setting '$255' to the operand value, which like with
  11675. 'GETA' must be a multiple of four, and a final 'GO $255,$255,0'.
  11676. 'PUSHJ'
  11677. Similar to expansion for conditional branches; four instructions
  11678. set '$255' to the operand value, followed by a 'PUSHGO
  11679. $255,$255,0'.
  11680. 'JMP'
  11681. Similar to conditional branches and 'PUSHJ'. The final instruction
  11682. is 'GO $255,$255,0'.
  11683. The linker 'ld' is expected to shrink these expansions for code
  11684. assembled with '--relax' (though not currently implemented).
  11685. 
  11686. File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent
  11687. 9.28.3 Syntax
  11688. -------------
  11689. The assembly syntax is supposed to be upward compatible with that
  11690. described in Sections 1.3 and 1.4 of 'The Art of Computer Programming,
  11691. Volume 1'. Draft versions of those chapters as well as other MMIX
  11692. information is located at
  11693. <http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code
  11694. examples from the mmixal package located there should work unmodified
  11695. when assembled and linked as single files, with a few noteworthy
  11696. exceptions (*note MMIX-mmixal::).
  11697. Before an instruction is emitted, the current location is aligned to
  11698. the next four-byte boundary. If a label is defined at the beginning of
  11699. the line, its value will be the aligned value.
  11700. In addition to the traditional hex-prefix '0x', a hexadecimal number
  11701. can also be specified by the prefix character '#'.
  11702. After all operands to an MMIX instruction or directive have been
  11703. specified, the rest of the line is ignored, treated as a comment.
  11704. * Menu:
  11705. * MMIX-Chars:: Special Characters
  11706. * MMIX-Symbols:: Symbols
  11707. * MMIX-Regs:: Register Names
  11708. * MMIX-Pseudos:: Assembler Directives
  11709. 
  11710. File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax
  11711. 9.28.3.1 Special Characters
  11712. ...........................
  11713. The characters '*' and '#' are line comment characters; each start a
  11714. comment at the beginning of a line, but only at the beginning of a line.
  11715. A '#' prefixes a hexadecimal number if found elsewhere on a line. If a
  11716. '#' appears at the start of a line the whole line is treated as a
  11717. comment, but the line can also act as a logical line number directive
  11718. (*note Comments::) or a preprocessor control command (*note
  11719. Preprocessing::).
  11720. Two other characters, '%' and '!', each start a comment anywhere on
  11721. the line. Thus you can't use the 'modulus' and 'not' operators in
  11722. expressions normally associated with these two characters.
  11723. A ';' is a line separator, treated as a new-line, so separate
  11724. instructions can be specified on a single line.
  11725. 
  11726. File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax
  11727. 9.28.3.2 Symbols
  11728. ................
  11729. The character ':' is permitted in identifiers. There are two exceptions
  11730. to it being treated as any other symbol character: if a symbol begins
  11731. with ':', it means that the symbol is in the global namespace and that
  11732. the current prefix should not be prepended to that symbol (*note
  11733. MMIX-prefix::). The ':' is then not considered part of the symbol. For
  11734. a symbol in the label position (first on a line), a ':' at the end of a
  11735. symbol is silently stripped off. A label is permitted, but not
  11736. required, to be followed by a ':', as with many other assembly formats.
  11737. The character '@' in an expression, is a synonym for '.', the current
  11738. location.
  11739. In addition to the common forward and backward local symbol formats
  11740. (*note Symbol Names::), they can be specified with upper-case 'B' and
  11741. 'F', as in '8B' and '9F'. A local label defined for the current
  11742. position is written with a 'H' appended to the number:
  11743. 3H LDB $0,$1,2
  11744. This and traditional local-label formats cannot be mixed: a label
  11745. must be defined and referred to using the same format.
  11746. There's a minor caveat: just as for the ordinary local symbols, the
  11747. local symbols are translated into ordinary symbols using control
  11748. characters are to hide the ordinal number of the symbol. Unfortunately,
  11749. these symbols are not translated back in error messages. Thus you may
  11750. see confusing error messages when local symbols are used. Control
  11751. characters '\003' (control-C) and '\004' (control-D) are used for the
  11752. MMIX-specific local-symbol syntax.
  11753. The symbol 'Main' is handled specially; it is always global.
  11754. By defining the symbols '__.MMIX.start..text' and
  11755. '__.MMIX.start..data', the address of respectively the '.text' and
  11756. '.data' segments of the final program can be defined, though when
  11757. linking more than one object file, the code or data in the object file
  11758. containing the symbol is not guaranteed to be start at that position;
  11759. just the final executable. *Note MMIX-loc::.
  11760. 
  11761. File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax
  11762. 9.28.3.3 Register names
  11763. .......................
  11764. Local and global registers are specified as '$0' to '$255'. The
  11765. recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD',
  11766. 'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ',
  11767. 'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT',
  11768. 'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special
  11769. register names.
  11770. Local and global symbols can be equated to register names and used in
  11771. place of ordinary registers.
  11772. Similarly for special registers, local and global symbols can be
  11773. used. Also, symbols equated from numbers and constant expressions are
  11774. allowed in place of a special register, except when either of the
  11775. options '--no-predefined-syms' and '--fixed-special-register-names' are
  11776. specified. Then only the special register names above are allowed for
  11777. the instructions having a special register operand; 'GET' and 'PUT'.
  11778. 
  11779. File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax
  11780. 9.28.3.4 Assembler Directives
  11781. .............................
  11782. 'LOC'
  11783. The 'LOC' directive sets the current location to the value of the
  11784. operand field, which may include changing sections. If the operand
  11785. is a constant, the section is set to either '.data' if the value is
  11786. '0x2000000000000000' or larger, else it is set to '.text'. Within
  11787. a section, the current location may only be changed to
  11788. monotonically higher addresses. A LOC expression must be a
  11789. previously defined symbol or a "pure" constant.
  11790. An example, which sets the label PREV to the current location, and
  11791. updates the current location to eight bytes forward:
  11792. prev LOC @+8
  11793. When a LOC has a constant as its operand, a symbol
  11794. '__.MMIX.start..text' or '__.MMIX.start..data' is defined depending
  11795. on the address as mentioned above. Each such symbol is interpreted
  11796. as special by the linker, locating the section at that address.
  11797. Note that if multiple files are linked, the first object file with
  11798. that section will be mapped to that address (not necessarily the
  11799. file with the LOC definition).
  11800. 'LOCAL'
  11801. Example:
  11802. LOCAL external_symbol
  11803. LOCAL 42
  11804. .local asymbol
  11805. This directive-operation generates a link-time assertion that the
  11806. operand does not correspond to a global register. The operand is
  11807. an expression that at link-time resolves to a register symbol or a
  11808. number. A number is treated as the register having that number.
  11809. There is one restriction on the use of this directive: the
  11810. pseudo-directive must be placed in a section with contents, code or
  11811. data.
  11812. 'IS'
  11813. The 'IS' directive:
  11814. asymbol IS an_expression
  11815. sets the symbol 'asymbol' to 'an_expression'. A symbol may not be
  11816. set more than once using this directive. Local labels may be set
  11817. using this directive, for example:
  11818. 5H IS @+4
  11819. 'GREG'
  11820. This directive reserves a global register, gives it an initial
  11821. value and optionally gives it a symbolic name. Some examples:
  11822. areg GREG
  11823. breg GREG data_value
  11824. GREG data_buffer
  11825. .greg creg, another_data_value
  11826. The symbolic register name can be used in place of a (non-special)
  11827. register. If a value isn't provided, it defaults to zero. Unless
  11828. the option '--no-merge-gregs' is specified, non-zero registers
  11829. allocated with this directive may be eliminated by 'as'; another
  11830. register with the same value used in its place. Any of the
  11831. instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU',
  11832. 'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW',
  11833. 'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT',
  11834. 'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have
  11835. a value nearby an initial value in place of its second and third
  11836. operands. Here, "nearby" is defined as within the range 0...255
  11837. from the initial value of such an allocated register.
  11838. buffer1 BYTE 0,0,0,0,0
  11839. buffer2 BYTE 0,0,0,0,0
  11840. ...
  11841. GREG buffer1
  11842. LDOU $42,buffer2
  11843. In the example above, the 'Y' field of the 'LDOUI' instruction
  11844. (LDOU with a constant Z) will be replaced with the global register
  11845. allocated for 'buffer1', and the 'Z' field will have the value 5,
  11846. the offset from 'buffer1' to 'buffer2'. The result is equivalent
  11847. to this code:
  11848. buffer1 BYTE 0,0,0,0,0
  11849. buffer2 BYTE 0,0,0,0,0
  11850. ...
  11851. tmpreg GREG buffer1
  11852. LDOU $42,tmpreg,(buffer2-buffer1)
  11853. Global registers allocated with this directive are allocated in
  11854. order higher-to-lower within a file. Other than that, the exact
  11855. order of register allocation and elimination is undefined. For
  11856. example, the order is undefined when more than one file with such
  11857. directives are linked together. With the options '-x' and
  11858. '--linker-allocated-gregs', 'GREG' directives for two-operand cases
  11859. like the one mentioned above can be omitted. Sufficient global
  11860. registers will then be allocated by the linker.
  11861. 'BYTE'
  11862. The 'BYTE' directive takes a series of operands separated by a
  11863. comma. If an operand is a string (*note Strings::), each character
  11864. of that string is emitted as a byte. Other operands must be
  11865. constant expressions without forward references, in the range
  11866. 0...255. If you need operands having expressions with forward
  11867. references, use '.byte' (*note Byte::). An operand can be omitted,
  11868. defaulting to a zero value.
  11869. 'WYDE'
  11870. 'TETRA'
  11871. 'OCTA'
  11872. The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two,
  11873. four and eight bytes size respectively. Before anything else
  11874. happens for the directive, the current location is aligned to the
  11875. respective constant-size boundary. If a label is defined at the
  11876. beginning of the line, its value will be that after the alignment.
  11877. A single operand can be omitted, defaulting to a zero value emitted
  11878. for the directive. Operands can be expressed as strings (*note
  11879. Strings::), in which case each character in the string is emitted
  11880. as a separate constant of the size indicated by the directive.
  11881. 'PREFIX'
  11882. The 'PREFIX' directive sets a symbol name prefix to be prepended to
  11883. all symbols (except local symbols, *note MMIX-Symbols::), that are
  11884. not prefixed with ':', until the next 'PREFIX' directive. Such
  11885. prefixes accumulate. For example,
  11886. PREFIX a
  11887. PREFIX b
  11888. c IS 0
  11889. defines a symbol 'abc' with the value 0.
  11890. 'BSPEC'
  11891. 'ESPEC'
  11892. A pair of 'BSPEC' and 'ESPEC' directives delimit a section of
  11893. special contents (without specified semantics). Example:
  11894. BSPEC 42
  11895. TETRA 1,2,3
  11896. ESPEC
  11897. The single operand to 'BSPEC' must be number in the range 0...255.
  11898. The 'BSPEC' number 80 is used by the GNU binutils implementation.
  11899. 
  11900. File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent
  11901. 9.28.4 Differences to 'mmixal'
  11902. ------------------------------
  11903. The binutils 'as' and 'ld' combination has a few differences in function
  11904. compared to 'mmixal' (*note mmixsite::).
  11905. The replacement of a symbol with a GREG-allocated register (*note
  11906. GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'.
  11907. This is apparent in the 'mmixal' example file 'inout.mms', where
  11908. different registers with different offsets, eventually yielding the same
  11909. address, are used in the first instruction. This type of difference
  11910. should however not affect the function of any program unless it has
  11911. specific assumptions about the allocated register number.
  11912. Line numbers (in the 'mmo' object format) are currently not
  11913. supported.
  11914. Expression operator precedence is not that of mmixal: operator
  11915. precedence is that of the C programming language. It's recommended to
  11916. use parentheses to explicitly specify wanted operator precedence
  11917. whenever more than one type of operators are used.
  11918. The serialize unary operator '&', the fractional division operator
  11919. '//', the logical not operator '!' and the modulus operator '%' are not
  11920. available.
  11921. Symbols are not global by default, unless the option
  11922. '--globalize-symbols' is passed. Use the '.global' directive to
  11923. globalize symbols (*note Global::).
  11924. Operand syntax is a bit stricter with 'as' than 'mmixal'. For
  11925. example, you can't say 'addu 1,2,3', instead you must write 'addu
  11926. $1,$2,3'.
  11927. You can't LOC to a lower address than those already visited (i.e.,
  11928. "backwards").
  11929. A LOC directive must come before any emitted code.
  11930. Predefined symbols are visible as file-local symbols after use. (In
  11931. the ELF file, that is--the linked mmo file has no notion of a file-local
  11932. symbol.)
  11933. Some mapping of constant expressions to sections in LOC expressions
  11934. is attempted, but that functionality is easily confused and should be
  11935. avoided unless compatibility with 'mmixal' is required. A LOC
  11936. expression to '0x2000000000000000' or higher, maps to the '.data'
  11937. section and lower addresses map to the '.text' section (*note
  11938. MMIX-loc::).
  11939. The code and data areas are each contiguous. Sparse programs with
  11940. far-away LOC directives will take up the same amount of space as a
  11941. contiguous program with zeros filled in the gaps between the LOC
  11942. directives. If you need sparse programs, you might try and get the
  11943. wanted effect with a linker script and splitting up the code parts into
  11944. sections (*note Section::). Assembly code for this, to be compatible
  11945. with 'mmixal', would look something like:
  11946. .if 0
  11947. LOC away_expression
  11948. .else
  11949. .section away,"ax"
  11950. .fi
  11951. 'as' will not execute the LOC directive and 'mmixal' ignores the
  11952. lines with '.'. This construct can be used generally to help
  11953. compatibility.
  11954. Symbols can't be defined twice-not even to the same value.
  11955. Instruction mnemonics are recognized case-insensitive, though the
  11956. 'IS' and 'GREG' pseudo-operations must be specified in upper-case
  11957. characters.
  11958. There's no unicode support.
  11959. The following is a list of programs in 'mmix.tar.gz', available at
  11960. <http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked
  11961. with the version dated 2001-08-25 (md5sum
  11962. c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not
  11963. assemble with 'as':
  11964. 'silly.mms'
  11965. LOC to a previous address.
  11966. 'sim.mms'
  11967. Redefines symbol 'Done'.
  11968. 'test.mms'
  11969. Uses the serial operator '&'.
  11970. 
  11971. File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies
  11972. 9.29 MSP 430 Dependent Features
  11973. ===============================
  11974. * Menu:
  11975. * MSP430 Options:: Options
  11976. * MSP430 Syntax:: Syntax
  11977. * MSP430 Floating Point:: Floating Point
  11978. * MSP430 Directives:: MSP 430 Machine Directives
  11979. * MSP430 Opcodes:: Opcodes
  11980. * MSP430 Profiling Capability:: Profiling Capability
  11981. 
  11982. File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent
  11983. 9.29.1 Options
  11984. --------------
  11985. '-mmcu'
  11986. selects the mcu architecture. If the architecture is 430Xv2 then
  11987. this also enables NOP generation unless the '-mN' is also
  11988. specified.
  11989. '-mcpu'
  11990. selects the cpu architecture. If the architecture is 430Xv2 then
  11991. this also enables NOP generation unless the '-mN' is also
  11992. specified.
  11993. '-msilicon-errata=NAME[,NAME...]'
  11994. Implements a fixup for named silicon errata. Multiple silicon
  11995. errata can be specified by multiple uses of the '-msilicon-errata'
  11996. option and/or by including the errata names, separated by commas,
  11997. on an individual '-msilicon-errata' option. Errata names currently
  11998. recognised by the assembler are:
  11999. 'cpu4'
  12000. 'PUSH #4' and 'PUSH #8' need longer encodings on the MSP430.
  12001. This option is enabled by default, and cannot be disabled.
  12002. 'cpu8'
  12003. Do not set the 'SP' to an odd value.
  12004. 'cpu11'
  12005. Do not update the 'SR' and the 'PC' in the same instruction.
  12006. 'cpu12'
  12007. Do not use the 'PC' in a 'CMP' or 'BIT' instruction.
  12008. 'cpu13'
  12009. Do not use an arithmetic instruction to modify the 'SR'.
  12010. 'cpu19'
  12011. Insert 'NOP' after 'CPUOFF'.
  12012. '-msilicon-errata-warn=NAME[,NAME...]'
  12013. Like the '-msilicon-errata' option except that instead of fixing
  12014. the specified errata, a warning message is issued instead. This
  12015. option can be used alongside '-msilicon-errata' to generate
  12016. messages whenever a problem is fixed, or on its own in order to
  12017. inspect code for potential problems.
  12018. '-mP'
  12019. enables polymorph instructions handler.
  12020. '-mQ'
  12021. enables relaxation at assembly time. DANGEROUS!
  12022. '-ml'
  12023. indicates that the input uses the large code model.
  12024. '-mn'
  12025. enables the generation of a NOP instruction following any
  12026. instruction that might change the interrupts enabled/disabled
  12027. state. The pipelined nature of the MSP430 core means that any
  12028. instruction that changes the interrupt state ('EINT', 'DINT', 'BIC
  12029. #8, SR', 'BIS #8, SR' or 'MOV.W <>, SR') must be followed by a NOP
  12030. instruction in order to ensure the correct processing of
  12031. interrupts. By default it is up to the programmer to supply these
  12032. NOP instructions, but this command line option enables the
  12033. automatic insertion by the assembler, if they are missing.
  12034. '-mN'
  12035. disables the generation of a NOP instruction following any
  12036. instruction that might change the interrupts enabled/disabled
  12037. state. This is the default behaviour.
  12038. '-my'
  12039. tells the assembler to generate a warning message if a NOP does not
  12040. immediately forllow an instruction that enables or disables
  12041. interrupts. This is the default.
  12042. Note that this option can be stacked with the '-mn' option so that
  12043. the assembler will both warn about missing NOP instructions and
  12044. then insert them automatically.
  12045. '-mY'
  12046. disables warnings about missing NOP instructions.
  12047. '-md'
  12048. mark the object file as one that requires data to copied from ROM
  12049. to RAM at execution startup. Disabled by default.
  12050. 
  12051. File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent
  12052. 9.29.2 Syntax
  12053. -------------
  12054. * Menu:
  12055. * MSP430-Macros:: Macros
  12056. * MSP430-Chars:: Special Characters
  12057. * MSP430-Regs:: Register Names
  12058. * MSP430-Ext:: Assembler Extensions
  12059. 
  12060. File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax
  12061. 9.29.2.1 Macros
  12062. ...............
  12063. The macro syntax used on the MSP 430 is like that described in the MSP
  12064. 430 Family Assembler Specification. Normal 'as' macros should still
  12065. work.
  12066. Additional built-in macros are:
  12067. 'llo(exp)'
  12068. Extracts least significant word from 32-bit expression 'exp'.
  12069. 'lhi(exp)'
  12070. Extracts most significant word from 32-bit expression 'exp'.
  12071. 'hlo(exp)'
  12072. Extracts 3rd word from 64-bit expression 'exp'.
  12073. 'hhi(exp)'
  12074. Extracts 4rd word from 64-bit expression 'exp'.
  12075. They normally being used as an immediate source operand.
  12076. mov #llo(1), r10 ; == mov #1, r10
  12077. mov #lhi(1), r10 ; == mov #0, r10
  12078. 
  12079. File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax
  12080. 9.29.2.2 Special Characters
  12081. ...........................
  12082. A semicolon (';') appearing anywhere on a line starts a comment that
  12083. extends to the end of that line.
  12084. If a '#' appears as the first character of a line then the whole line
  12085. is treated as a comment, but it can also be a logical line number
  12086. directive (*note Comments::) or a preprocessor control command (*note
  12087. Preprocessing::).
  12088. Multiple statements can appear on the same line provided that they
  12089. are separated by the '{' character.
  12090. The character '$' in jump instructions indicates current location and
  12091. implemented only for TI syntax compatibility.
  12092. 
  12093. File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax
  12094. 9.29.2.3 Register Names
  12095. .......................
  12096. General-purpose registers are represented by predefined symbols of the
  12097. form 'rN' (for global registers), where N represents a number between
  12098. '0' and '15'. The leading letters may be in either upper or lower case;
  12099. for example, 'r13' and 'R7' are both valid register names.
  12100. Register names 'PC', 'SP' and 'SR' cannot be used as register names
  12101. and will be treated as variables. Use 'r0', 'r1', and 'r2' instead.
  12102. 
  12103. File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax
  12104. 9.29.2.4 Assembler Extensions
  12105. .............................
  12106. '@rN'
  12107. As destination operand being treated as '0(rn)'
  12108. '0(rN)'
  12109. As source operand being treated as '@rn'
  12110. 'jCOND +N'
  12111. Skips next N bytes followed by jump instruction and equivalent to
  12112. 'jCOND $+N+2'
  12113. Also, there are some instructions, which cannot be found in other
  12114. assemblers. These are branch instructions, which has different opcodes
  12115. upon jump distance. They all got PC relative addressing mode.
  12116. 'beq label'
  12117. A polymorph instruction which is 'jeq label' in case if jump
  12118. distance within allowed range for cpu's jump instruction. If not,
  12119. this unrolls into a sequence of
  12120. jne $+6
  12121. br label
  12122. 'bne label'
  12123. A polymorph instruction which is 'jne label' or 'jeq +4; br label'
  12124. 'blt label'
  12125. A polymorph instruction which is 'jl label' or 'jge +4; br label'
  12126. 'bltn label'
  12127. A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br
  12128. label'
  12129. 'bltu label'
  12130. A polymorph instruction which is 'jlo label' or 'jhs +2; br label'
  12131. 'bge label'
  12132. A polymorph instruction which is 'jge label' or 'jl +4; br label'
  12133. 'bgeu label'
  12134. A polymorph instruction which is 'jhs label' or 'jlo +4; br label'
  12135. 'bgt label'
  12136. A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl
  12137. +4; br label'
  12138. 'bgtu label'
  12139. A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6;
  12140. jlo +4; br label'
  12141. 'bleu label'
  12142. A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2;
  12143. jhs +4; br label'
  12144. 'ble label'
  12145. A polymorph instruction which is 'jeq label; jl label' or 'jeq +2;
  12146. jge +4; br label'
  12147. 'jump label'
  12148. A polymorph instruction which is 'jmp label' or 'br label'
  12149. 
  12150. File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent
  12151. 9.29.3 Floating Point
  12152. ---------------------
  12153. The MSP 430 family uses IEEE 32-bit floating-point numbers.
  12154. 
  12155. File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent
  12156. 9.29.4 MSP 430 Machine Directives
  12157. ---------------------------------
  12158. '.file'
  12159. This directive is ignored; it is accepted for compatibility with
  12160. other MSP 430 assemblers.
  12161. _Warning:_ in other versions of the GNU assembler, '.file' is
  12162. used for the directive called '.app-file' in the MSP 430
  12163. support.
  12164. '.line'
  12165. This directive is ignored; it is accepted for compatibility with
  12166. other MSP 430 assemblers.
  12167. '.arch'
  12168. Sets the target microcontroller in the same way as the '-mmcu'
  12169. command line option.
  12170. '.cpu'
  12171. Sets the target architecture in the same way as the '-mcpu' command
  12172. line option.
  12173. '.profiler'
  12174. This directive instructs assembler to add new profile entry to the
  12175. object file.
  12176. '.refsym'
  12177. This directive instructs assembler to add an undefined reference to
  12178. the symbol following the directive. The maximum symbol name length
  12179. is 1023 characters. No relocation is created for this symbol; it
  12180. will exist purely for pulling in object files from archives. Note
  12181. that this reloc is not sufficient to prevent garbage collection;
  12182. use a KEEP() directive in the linker file to preserve such objects.
  12183. 
  12184. File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent
  12185. 9.29.5 Opcodes
  12186. --------------
  12187. 'as' implements all the standard MSP 430 opcodes. No additional
  12188. pseudo-instructions are needed on this family.
  12189. For information on the 430 machine instruction set, see 'MSP430
  12190. User's Manual, document slau049d', Texas Instrument, Inc.
  12191. 
  12192. File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent
  12193. 9.29.6 Profiling Capability
  12194. ---------------------------
  12195. It is a performance hit to use gcc's profiling approach for this tiny
  12196. target. Even more - jtag hardware facility does not perform any
  12197. profiling functions. However we've got gdb's built-in simulator where
  12198. we can do anything.
  12199. We define new section '.profiler' which holds all profiling
  12200. information. We define new pseudo operation '.profiler' which will
  12201. instruct assembler to add new profile entry to the object file. Profile
  12202. should take place at the present address.
  12203. Pseudo operation format:
  12204. '.profiler flags,function_to_profile [, cycle_corrector, extra]'
  12205. where:
  12206. 'flags' is a combination of the following characters:
  12207. 's'
  12208. function entry
  12209. 'x'
  12210. function exit
  12211. 'i'
  12212. function is in init section
  12213. 'f'
  12214. function is in fini section
  12215. 'l'
  12216. library call
  12217. 'c'
  12218. libc standard call
  12219. 'd'
  12220. stack value demand
  12221. 'I'
  12222. interrupt service routine
  12223. 'P'
  12224. prologue start
  12225. 'p'
  12226. prologue end
  12227. 'E'
  12228. epilogue start
  12229. 'e'
  12230. epilogue end
  12231. 'j'
  12232. long jump / sjlj unwind
  12233. 'a'
  12234. an arbitrary code fragment
  12235. 't'
  12236. extra parameter saved (a constant value like frame size)
  12237. 'function_to_profile'
  12238. a function address
  12239. 'cycle_corrector'
  12240. a value which should be added to the cycle counter, zero if
  12241. omitted.
  12242. 'extra'
  12243. any extra parameter, zero if omitted.
  12244. For example:
  12245. .global fxx
  12246. .type fxx,@function
  12247. fxx:
  12248. .LFrameOffset_fxx=0x08
  12249. .profiler "scdP", fxx ; function entry.
  12250. ; we also demand stack value to be saved
  12251. push r11
  12252. push r10
  12253. push r9
  12254. push r8
  12255. .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
  12256. ; (this is a prologue end)
  12257. ; note, that spare var filled with
  12258. ; the farme size
  12259. mov r15,r8
  12260. ...
  12261. .profiler cdE,fxx ; check stack
  12262. pop r8
  12263. pop r9
  12264. pop r10
  12265. pop r11
  12266. .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
  12267. ret ; cause 'ret' insn takes 3 cycles
  12268. 
  12269. File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies
  12270. 9.30 NDS32 Dependent Features
  12271. =============================
  12272. The NDS32 processors family includes high-performance and low-power
  12273. 32-bit processors for high-end to low-end. GNU 'as' for NDS32
  12274. architectures supports NDS32 ISA version 3. For detail about NDS32
  12275. instruction set, please see the AndeStar ISA User Manual which is
  12276. availible at http://www.andestech.com/en/index/index.htm
  12277. * Menu:
  12278. * NDS32 Options:: Assembler options
  12279. * NDS32 Syntax:: High-level assembly macros
  12280. 
  12281. File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent
  12282. 9.30.1 NDS32 Options
  12283. --------------------
  12284. The NDS32 configurations of GNU 'as' support these special options:
  12285. '-O1'
  12286. Optimize for performance.
  12287. '-Os'
  12288. Optimize for space.
  12289. '-EL'
  12290. Produce little endian data output.
  12291. '-EB'
  12292. Produce little endian data output.
  12293. '-mpic'
  12294. Generate PIC.
  12295. '-mno-fp-as-gp-relax'
  12296. Suppress fp-as-gp relaxation for this file.
  12297. '-mb2bb-relax'
  12298. Back-to-back branch optimization.
  12299. '-mno-all-relax'
  12300. Suppress all relaxation for this file.
  12301. '-march=<arch name>'
  12302. Assemble for architecture <arch name> which could be v3, v3j, v3m,
  12303. v3f, v3s, v2, v2j, v2f, v2s.
  12304. '-mbaseline=<baseline>'
  12305. Assemble for baseline <baseline> which could be v2, v3, v3m.
  12306. '-mfpu-freg=FREG'
  12307. Specify a FPU configuration.
  12308. '0 8 SP / 4 DP registers'
  12309. '1 16 SP / 8 DP registers'
  12310. '2 32 SP / 16 DP registers'
  12311. '3 32 SP / 32 DP registers'
  12312. '-mabi=ABI'
  12313. Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
  12314. '-m[no-]mac'
  12315. Enable/Disable Multiply instructions support.
  12316. '-m[no-]div'
  12317. Enable/Disable Divide instructions support.
  12318. '-m[no-]16bit-ext'
  12319. Enable/Disable 16-bit extension
  12320. '-m[no-]dx-regs'
  12321. Enable/Disable d0/d1 registers
  12322. '-m[no-]perf-ext'
  12323. Enable/Disable Performance extension
  12324. '-m[no-]perf2-ext'
  12325. Enable/Disable Performance extension 2
  12326. '-m[no-]string-ext'
  12327. Enable/Disable String extension
  12328. '-m[no-]reduced-regs'
  12329. Enable/Disable Reduced Register configuration (GPR16) option
  12330. '-m[no-]audio-isa-ext'
  12331. Enable/Disable AUDIO ISA extension
  12332. '-m[no-]fpu-sp-ext'
  12333. Enable/Disable FPU SP extension
  12334. '-m[no-]fpu-dp-ext'
  12335. Enable/Disable FPU DP extension
  12336. '-m[no-]fpu-fma'
  12337. Enable/Disable FPU fused-multiply-add instructions
  12338. '-mall-ext'
  12339. Turn on all extensions and instructions support
  12340. 
  12341. File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent
  12342. 9.30.2 Syntax
  12343. -------------
  12344. * Menu:
  12345. * NDS32-Chars:: Special Characters
  12346. * NDS32-Regs:: Register Names
  12347. * NDS32-Ops:: Pseudo Instructions
  12348. 
  12349. File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax
  12350. 9.30.2.1 Special Characters
  12351. ...........................
  12352. Use '#' at column 1 and '!' anywhere in the line except inside quotes.
  12353. Multiple instructions in a line are allowed though not recommended
  12354. and should be separated by ';'.
  12355. Assembler is not case-sensitive in general except user defined label.
  12356. For example, 'jral F1' is different from 'jral f1' while it is the same
  12357. as 'JRAL F1'.
  12358. 
  12359. File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax
  12360. 9.30.2.2 Register Names
  12361. .......................
  12362. 'General purpose registers (GPR)'
  12363. There are 32 32-bit general purpose registers $r0 to $r31.
  12364. 'Accumulators d0 and d1'
  12365. 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
  12366. 'Assembler reserved register $ta'
  12367. Register $ta ($r15) is reserved for assembler using.
  12368. 'Operating system reserved registers $p0 and $p1'
  12369. Registers $p0 ($r26) and $p1 ($r27) are used by operating system as
  12370. scratch registers.
  12371. 'Frame pointer $fp'
  12372. Register $r28 is regarded as the frame pointer.
  12373. 'Global pointer'
  12374. Register $r29 is regarded as the global pointer.
  12375. 'Link pointer'
  12376. Register $r30 is regarded as the link pointer.
  12377. 'Stack pointer'
  12378. Register $r31 is regarded as the stack pointer.
  12379. 
  12380. File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax
  12381. 9.30.2.3 Pseudo Instructions
  12382. ............................
  12383. 'li rt5,imm32'
  12384. load 32-bit integer into register rt5. 'sethi rt5,hi20(imm32)' and
  12385. then 'ori rt5,reg,lo12(imm32)'.
  12386. 'la rt5,var'
  12387. Load 32-bit address of var into register rt5. 'sethi
  12388. rt5,hi20(var)' and then 'ori reg,rt5,lo12(var)'
  12389. 'l.[bhw] rt5,var'
  12390. Load value of var into register rt5. 'sethi $ta,hi20(var)' and
  12391. then 'l[bhw]i rt5,[$ta+lo12(var)]'
  12392. 'l.[bh]s rt5,var'
  12393. Load value of var into register rt5. 'sethi $ta,hi20(var)' and
  12394. then 'l[bh]si rt5,[$ta+lo12(var)]'
  12395. 'l.[bhw]p rt5,var,inc'
  12396. Load value of var into register rt5 and increment $ta by amount
  12397. inc. 'la $ta,var' and then 'l[bhw]i.bi rt5,[$ta],inc'
  12398. 'l.[bhw]pc rt5,inc'
  12399. Continue loading value of var into register rt5 and increment $ta
  12400. by amount inc. 'l[bhw]i.bi rt5,[$ta],inc.'
  12401. 'l.[bh]sp rt5,var,inc'
  12402. Load value of var into register rt5 and increment $ta by amount
  12403. inc. 'la $ta,var' and then 'l[bh]si.bi rt5,[$ta],inc'
  12404. 'l.[bh]spc rt5,inc'
  12405. Continue loading value of var into register rt5 and increment $ta
  12406. by amount inc. 'l[bh]si.bi rt5,[$ta],inc.'
  12407. 's.[bhw] rt5,var'
  12408. Store register rt5 to var. 'sethi $ta,hi20(var)' and then 's[bhw]i
  12409. rt5,[$ta+lo12(var)]'
  12410. 's.[bhw]p rt5,var,inc'
  12411. Store register rt5 to var and increment $ta by amount inc. 'la
  12412. $ta,var' and then 's[bhw]i.bi rt5,[$ta],inc'
  12413. 's.[bhw]pc rt5,inc'
  12414. Continue storing register rt5 to var and increment $ta by amount
  12415. inc. 's[bhw]i.bi rt5,[$ta],inc.'
  12416. 'not rt5,ra5'
  12417. Alias of 'nor rt5,ra5,ra5'.
  12418. 'neg rt5,ra5'
  12419. Alias of 'subri rt5,ra5,0'.
  12420. 'br rb5'
  12421. Depending on how it is assembled, it is translated into 'r5 rb5' or
  12422. 'jr rb5'.
  12423. 'b label'
  12424. Branch to label depending on how it is assembled, it is translated
  12425. into 'j8 label', 'j label', or "'la $ta,label' 'br $ta'".
  12426. 'bral rb5'
  12427. Alias of jral br5 depending on how it is assembled, it is
  12428. translated into 'jral5 rb5' or 'jral rb5'.
  12429. 'bal fname'
  12430. Alias of jal fname depending on how it is assembled, it is
  12431. translated into 'jal fname' or "'la $ta,fname' 'bral $ta'".
  12432. 'call fname'
  12433. Call function fname same as 'jal fname'.
  12434. 'move rt5,ra5'
  12435. For 16-bit, this is 'mov55 rt5,ra5'. For no 16-bit, this is 'ori
  12436. rt5,ra5,0'.
  12437. 'move rt5,var'
  12438. This is the same as 'l.w rt5,var'.
  12439. 'move rt5,imm32'
  12440. This is the same as 'li rt5,imm32'.
  12441. 'pushm ra5,rb5'
  12442. Push contents of registers from ra5 to rb5 into stack.
  12443. 'push ra5'
  12444. Push content of register ra5 into stack. (same 'pushm ra5,ra5').
  12445. 'push.d var'
  12446. Push value of double-word variable var into stack.
  12447. 'push.w var'
  12448. Push value of word variable var into stack.
  12449. 'push.h var'
  12450. Push value of half-word variable var into stack.
  12451. 'push.b var'
  12452. Push value of byte variable var into stack.
  12453. 'pusha var'
  12454. Push 32-bit address of variable var into stack.
  12455. 'pushi imm32'
  12456. Push 32-bit immediate value into stack.
  12457. 'popm ra5,rb5'
  12458. Pop top of stack values into registers ra5 to rb5.
  12459. 'pop rt5'
  12460. Pop top of stack value into register. (same as 'popm rt5,rt5'.)
  12461. 'pop.d var,ra5'
  12462. Pop value of double-word variable var from stack using register ra5
  12463. as 2nd scratch register. (1st is $ta)
  12464. 'pop.w var,ra5'
  12465. Pop value of word variable var from stack using register ra5.
  12466. 'pop.h var,ra5'
  12467. Pop value of half-word variable var from stack using register ra5.
  12468. 'pop.b var,ra5'
  12469. Pop value of byte variable var from stack using register ra5.
  12470. 
  12471. File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies
  12472. 9.31 Nios II Dependent Features
  12473. ===============================
  12474. * Menu:
  12475. * Nios II Options:: Options
  12476. * Nios II Syntax:: Syntax
  12477. * Nios II Relocations:: Relocations
  12478. * Nios II Directives:: Nios II Machine Directives
  12479. * Nios II Opcodes:: Opcodes
  12480. 
  12481. File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent
  12482. 9.31.1 Options
  12483. --------------
  12484. '-relax-section'
  12485. Replace identified out-of-range branches with PC-relative 'jmp'
  12486. sequences when possible. The generated code sequences are suitable
  12487. for use in position-independent code, but there is a practical
  12488. limit on the extended branch range because of the length of the
  12489. sequences. This option is the default.
  12490. '-relax-all'
  12491. Replace branch instructions not determinable to be in range and all
  12492. call instructions with 'jmp' and 'callr' sequences (respectively).
  12493. This option generates absolute relocations against the target
  12494. symbols and is not appropriate for position-independent code.
  12495. '-no-relax'
  12496. Do not replace any branches or calls.
  12497. '-EB'
  12498. Generate big-endian output.
  12499. '-EL'
  12500. Generate little-endian output. This is the default.
  12501. '-march=ARCHITECTURE'
  12502. This option specifies the target architecture. The assembler
  12503. issues an error message if an attempt is made to assemble an
  12504. instruction which will not execute on the target architecture. The
  12505. following architecture names are recognized: 'r1', 'r2'. The
  12506. default is 'r1'.
  12507. 
  12508. File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent
  12509. 9.31.2 Syntax
  12510. -------------
  12511. * Menu:
  12512. * Nios II Chars:: Special Characters
  12513. 
  12514. File: as.info, Node: Nios II Chars, Up: Nios II Syntax
  12515. 9.31.2.1 Special Characters
  12516. ...........................
  12517. '#' is the line comment character. ';' is the line separator character.
  12518. 
  12519. File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent
  12520. 9.31.3 Nios II Machine Relocations
  12521. ----------------------------------
  12522. '%hiadj(EXPRESSION)'
  12523. Extract the upper 16 bits of EXPRESSION and add one if the 15th bit
  12524. is set.
  12525. The value of '%hiadj(EXPRESSION)' is:
  12526. ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01)
  12527. The '%hiadj' relocation is intended to be used with the 'addi',
  12528. 'ld' or 'st' instructions along with a '%lo', in order to load a
  12529. 32-bit constant.
  12530. movhi r2, %hiadj(symbol)
  12531. addi r2, r2, %lo(symbol)
  12532. '%hi(EXPRESSION)'
  12533. Extract the upper 16 bits of EXPRESSION.
  12534. '%lo(EXPRESSION)'
  12535. Extract the lower 16 bits of EXPRESSION.
  12536. '%gprel(EXPRESSION)'
  12537. Subtract the value of the symbol '_gp' from EXPRESSION.
  12538. The intention of the '%gprel' relocation is to have a fast small
  12539. area of memory which only takes a 16-bit immediate to access.
  12540. .section .sdata
  12541. fastint:
  12542. .int 123
  12543. .section .text
  12544. ldw r4, %gprel(fastint)(gp)
  12545. '%call(EXPRESSION)'
  12546. '%call_lo(EXPRESSION)'
  12547. '%call_hiadj(EXPRESSION)'
  12548. '%got(EXPRESSION)'
  12549. '%got_lo(EXPRESSION)'
  12550. '%got_hiadj(EXPRESSION)'
  12551. '%gotoff(EXPRESSION)'
  12552. '%gotoff_lo(EXPRESSION)'
  12553. '%gotoff_hiadj(EXPRESSION)'
  12554. '%tls_gd(EXPRESSION)'
  12555. '%tls_ie(EXPRESSION)'
  12556. '%tls_le(EXPRESSION)'
  12557. '%tls_ldm(EXPRESSION)'
  12558. '%tls_ldo(EXPRESSION)'
  12559. These relocations support the ABI for Linux Systems documented in
  12560. the 'Nios II Processor Reference Handbook'.
  12561. 
  12562. File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent
  12563. 9.31.4 Nios II Machine Directives
  12564. ---------------------------------
  12565. '.align EXPRESSION [, EXPRESSION]'
  12566. This is the generic '.align' directive, however this aligns to a
  12567. power of two.
  12568. '.half EXPRESSION'
  12569. Create an aligned constant 2 bytes in size.
  12570. '.word EXPRESSION'
  12571. Create an aligned constant 4 bytes in size.
  12572. '.dword EXPRESSION'
  12573. Create an aligned constant 8 bytes in size.
  12574. '.2byte EXPRESSION'
  12575. Create an unaligned constant 2 bytes in size.
  12576. '.4byte EXPRESSION'
  12577. Create an unaligned constant 4 bytes in size.
  12578. '.8byte EXPRESSION'
  12579. Create an unaligned constant 8 bytes in size.
  12580. '.16byte EXPRESSION'
  12581. Create an unaligned constant 16 bytes in size.
  12582. '.set noat'
  12583. Allows assembly code to use 'at' register without warning. Macro
  12584. or relaxation expansions generate warnings.
  12585. '.set at'
  12586. Assembly code using 'at' register generates warnings, and macro
  12587. expansion and relaxation are enabled.
  12588. '.set nobreak'
  12589. Allows assembly code to use 'ba' and 'bt' registers without
  12590. warning.
  12591. '.set break'
  12592. Turns warnings back on for using 'ba' and 'bt' registers.
  12593. '.set norelax'
  12594. Do not replace any branches or calls.
  12595. '.set relaxsection'
  12596. Replace identified out-of-range branches with 'jmp' sequences
  12597. (default).
  12598. '.set relaxsection'
  12599. Replace all branch and call instructions with 'jmp' and 'callr'
  12600. sequences.
  12601. '.set ...'
  12602. All other '.set' are the normal use.
  12603. 
  12604. File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent
  12605. 9.31.5 Opcodes
  12606. --------------
  12607. 'as' implements all the standard Nios II opcodes documented in the 'Nios
  12608. II Processor Reference Handbook', including the assembler
  12609. pseudo-instructions.
  12610. 
  12611. File: as.info, Node: NS32K-Dependent, Next: PDP-11-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies
  12612. 9.32 NS32K Dependent Features
  12613. =============================
  12614. * Menu:
  12615. * NS32K Syntax:: Syntax
  12616. 
  12617. File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent
  12618. 9.32.1 Syntax
  12619. -------------
  12620. * Menu:
  12621. * NS32K-Chars:: Special Characters
  12622. 
  12623. File: as.info, Node: NS32K-Chars, Up: NS32K Syntax
  12624. 9.32.1.1 Special Characters
  12625. ...........................
  12626. The presence of a '#' appearing anywhere on a line indicates the start
  12627. of a comment that extends to the end of that line.
  12628. If a '#' appears as the first character of a line then the whole line
  12629. is treated as a comment, but in this case the line can also be a logical
  12630. line number directive (*note Comments::) or a preprocessor control
  12631. command (*note Preprocessing::).
  12632. If Sequent compatibility has been configured into the assembler then
  12633. the '|' character appearing as the first character on a line will also
  12634. indicate the start of a line comment.
  12635. The ';' character can be used to separate statements on the same
  12636. line.
  12637. 
  12638. File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies
  12639. 9.33 PDP-11 Dependent Features
  12640. ==============================
  12641. * Menu:
  12642. * PDP-11-Options:: Options
  12643. * PDP-11-Pseudos:: Assembler Directives
  12644. * PDP-11-Syntax:: DEC Syntax versus BSD Syntax
  12645. * PDP-11-Mnemonics:: Instruction Naming
  12646. * PDP-11-Synthetic:: Synthetic Instructions
  12647. 
  12648. File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent
  12649. 9.33.1 Options
  12650. --------------
  12651. The PDP-11 version of 'as' has a rich set of machine dependent options.
  12652. 9.33.1.1 Code Generation Options
  12653. ................................
  12654. '-mpic | -mno-pic'
  12655. Generate position-independent (or position-dependent) code.
  12656. The default is to generate position-independent code.
  12657. 9.33.1.2 Instruction Set Extension Options
  12658. ..........................................
  12659. These options enables or disables the use of extensions over the base
  12660. line instruction set as introduced by the first PDP-11 CPU: the KA11.
  12661. Most options come in two variants: a '-m'EXTENSION that enables
  12662. EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION.
  12663. The default is to enable all extensions.
  12664. '-mall | -mall-extensions'
  12665. Enable all instruction set extensions.
  12666. '-mno-extensions'
  12667. Disable all instruction set extensions.
  12668. '-mcis | -mno-cis'
  12669. Enable (or disable) the use of the commercial instruction set,
  12670. which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI',
  12671. 'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI',
  12672. 'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP',
  12673. 'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI',
  12674. 'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI',
  12675. 'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC',
  12676. 'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI',
  12677. 'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'.
  12678. '-mcsm | -mno-csm'
  12679. Enable (or disable) the use of the 'CSM' instruction.
  12680. '-meis | -mno-eis'
  12681. Enable (or disable) the use of the extended instruction set, which
  12682. consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK',
  12683. 'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'.
  12684. '-mfis | -mkev11'
  12685. '-mno-fis | -mno-kev11'
  12686. Enable (or disable) the use of the KEV11 floating-point
  12687. instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'.
  12688. '-mfpp | -mfpu | -mfp-11'
  12689. '-mno-fpp | -mno-fpu | -mno-fp-11'
  12690. Enable (or disable) the use of FP-11 floating-point instructions:
  12691. 'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF',
  12692. 'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF',
  12693. 'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST',
  12694. 'SUBF', and 'TSTF'.
  12695. '-mlimited-eis | -mno-limited-eis'
  12696. Enable (or disable) the use of the limited extended instruction
  12697. set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'.
  12698. The -mno-limited-eis options also implies -mno-eis.
  12699. '-mmfpt | -mno-mfpt'
  12700. Enable (or disable) the use of the 'MFPT' instruction.
  12701. '-mmultiproc | -mno-multiproc'
  12702. Enable (or disable) the use of multiprocessor instructions:
  12703. 'TSTSET' and 'WRTLCK'.
  12704. '-mmxps | -mno-mxps'
  12705. Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions.
  12706. '-mspl | -mno-spl'
  12707. Enable (or disable) the use of the 'SPL' instruction.
  12708. Enable (or disable) the use of the microcode instructions: 'LDUB',
  12709. 'MED', and 'XFC'.
  12710. 9.33.1.3 CPU Model Options
  12711. ..........................
  12712. These options enable the instruction set extensions supported by a
  12713. particular CPU, and disables all other extensions.
  12714. '-mka11'
  12715. KA11 CPU. Base line instruction set only.
  12716. '-mkb11'
  12717. KB11 CPU. Enable extended instruction set and 'SPL'.
  12718. '-mkd11a'
  12719. KD11-A CPU. Enable limited extended instruction set.
  12720. '-mkd11b'
  12721. KD11-B CPU. Base line instruction set only.
  12722. '-mkd11d'
  12723. KD11-D CPU. Base line instruction set only.
  12724. '-mkd11e'
  12725. KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'.
  12726. '-mkd11f | -mkd11h | -mkd11q'
  12727. KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction
  12728. set, 'MFPS', and 'MTPS'.
  12729. '-mkd11k'
  12730. KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS',
  12731. 'MFPT', 'MTPS', and 'XFC'.
  12732. '-mkd11z'
  12733. KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT',
  12734. 'MTPS', and 'SPL'.
  12735. '-mf11'
  12736. F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and
  12737. 'MTPS'.
  12738. '-mj11'
  12739. J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT',
  12740. 'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'.
  12741. '-mt11'
  12742. T11 CPU. Enable limited extended instruction set, 'MFPS', and
  12743. 'MTPS'.
  12744. 9.33.1.4 Machine Model Options
  12745. ..............................
  12746. These options enable the instruction set extensions supported by a
  12747. particular machine model, and disables all other extensions.
  12748. '-m11/03'
  12749. Same as '-mkd11f'.
  12750. '-m11/04'
  12751. Same as '-mkd11d'.
  12752. '-m11/05 | -m11/10'
  12753. Same as '-mkd11b'.
  12754. '-m11/15 | -m11/20'
  12755. Same as '-mka11'.
  12756. '-m11/21'
  12757. Same as '-mt11'.
  12758. '-m11/23 | -m11/24'
  12759. Same as '-mf11'.
  12760. '-m11/34'
  12761. Same as '-mkd11e'.
  12762. '-m11/34a'
  12763. Ame as '-mkd11e' '-mfpp'.
  12764. '-m11/35 | -m11/40'
  12765. Same as '-mkd11a'.
  12766. '-m11/44'
  12767. Same as '-mkd11z'.
  12768. '-m11/45 | -m11/50 | -m11/55 | -m11/70'
  12769. Same as '-mkb11'.
  12770. '-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
  12771. Same as '-mj11'.
  12772. '-m11/60'
  12773. Same as '-mkd11k'.
  12774. 
  12775. File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent
  12776. 9.33.2 Assembler Directives
  12777. ---------------------------
  12778. The PDP-11 version of 'as' has a few machine dependent assembler
  12779. directives.
  12780. '.bss'
  12781. Switch to the 'bss' section.
  12782. '.even'
  12783. Align the location counter to an even number.
  12784. 
  12785. File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent
  12786. 9.33.3 PDP-11 Assembly Language Syntax
  12787. --------------------------------------
  12788. 'as' supports both DEC syntax and BSD syntax. The only difference is
  12789. that in DEC syntax, a '#' character is used to denote an immediate
  12790. constants, while in BSD syntax the character for this purpose is '$'.
  12791. general-purpose registers are named 'r0' through 'r7'. Mnemonic
  12792. alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively.
  12793. Floating-point registers are named 'ac0' through 'ac3', or
  12794. alternatively 'fr0' through 'fr3'.
  12795. Comments are started with a '#' or a '/' character, and extend to the
  12796. end of the line. (FIXME: clash with immediates?)
  12797. Multiple statements on the same line can be separated by the ';'
  12798. character.
  12799. 
  12800. File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent
  12801. 9.33.4 Instruction Naming
  12802. -------------------------
  12803. Some instructions have alternative names.
  12804. 'BCC'
  12805. 'BHIS'
  12806. 'BCS'
  12807. 'BLO'
  12808. 'L2DR'
  12809. 'L2D'
  12810. 'L3DR'
  12811. 'L3D'
  12812. 'SYS'
  12813. 'TRAP'
  12814. 
  12815. File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent
  12816. 9.33.5 Synthetic Instructions
  12817. -----------------------------
  12818. The 'JBR' and 'J'CC synthetic instructions are not supported yet.
  12819. 
  12820. File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies
  12821. 9.34 picoJava Dependent Features
  12822. ================================
  12823. * Menu:
  12824. * PJ Options:: Options
  12825. * PJ Syntax:: PJ Syntax
  12826. 
  12827. File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent
  12828. 9.34.1 Options
  12829. --------------
  12830. 'as' has two additional command-line options for the picoJava
  12831. architecture.
  12832. '-ml'
  12833. This option selects little endian data output.
  12834. '-mb'
  12835. This option selects big endian data output.
  12836. 
  12837. File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent
  12838. 9.34.2 PJ Syntax
  12839. ----------------
  12840. * Menu:
  12841. * PJ-Chars:: Special Characters
  12842. 
  12843. File: as.info, Node: PJ-Chars, Up: PJ Syntax
  12844. 9.34.2.1 Special Characters
  12845. ...........................
  12846. The presence of a '!' or '/' on a line indicates the start of a comment
  12847. that extends to the end of the current line.
  12848. If a '#' appears as the first character of a line then the whole line
  12849. is treated as a comment, but in this case the line could also be a
  12850. logical line number directive (*note Comments::) or a preprocessor
  12851. control command (*note Preprocessing::).
  12852. The ';' character can be used to separate statements on the same
  12853. line.
  12854. 
  12855. File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
  12856. 9.35 PowerPC Dependent Features
  12857. ===============================
  12858. * Menu:
  12859. * PowerPC-Opts:: Options
  12860. * PowerPC-Pseudo:: PowerPC Assembler Directives
  12861. * PowerPC-Syntax:: PowerPC Syntax
  12862. 
  12863. File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent
  12864. 9.35.1 Options
  12865. --------------
  12866. The PowerPC chip family includes several successive levels, using the
  12867. same core instruction set, but including a few additional instructions
  12868. at each level. There are exceptions to this however. For details on
  12869. what instructions each variant supports, please see the chip's
  12870. architecture reference manual.
  12871. The following table lists all available PowerPC options.
  12872. '-a32'
  12873. Generate ELF32 or XCOFF32.
  12874. '-a64'
  12875. Generate ELF64 or XCOFF64.
  12876. '-K PIC'
  12877. Set EF_PPC_RELOCATABLE_LIB in ELF flags.
  12878. '-mpwrx | -mpwr2'
  12879. Generate code for POWER/2 (RIOS2).
  12880. '-mpwr'
  12881. Generate code for POWER (RIOS1)
  12882. '-m601'
  12883. Generate code for PowerPC 601.
  12884. '-mppc, -mppc32, -m603, -m604'
  12885. Generate code for PowerPC 603/604.
  12886. '-m403, -m405'
  12887. Generate code for PowerPC 403/405.
  12888. '-m440'
  12889. Generate code for PowerPC 440. BookE and some 405 instructions.
  12890. '-m464'
  12891. Generate code for PowerPC 464.
  12892. '-m476'
  12893. Generate code for PowerPC 476.
  12894. '-m7400, -m7410, -m7450, -m7455'
  12895. Generate code for PowerPC 7400/7410/7450/7455.
  12896. '-m750cl'
  12897. Generate code for PowerPC 750CL.
  12898. '-m821, -m850, -m860'
  12899. Generate code for PowerPC 821/850/860.
  12900. '-mppc64, -m620'
  12901. Generate code for PowerPC 620/625/630.
  12902. '-me500, -me500x2'
  12903. Generate code for Motorola e500 core complex.
  12904. '-me500mc'
  12905. Generate code for Freescale e500mc core complex.
  12906. '-me500mc64'
  12907. Generate code for Freescale e500mc64 core complex.
  12908. '-me5500'
  12909. Generate code for Freescale e5500 core complex.
  12910. '-me6500'
  12911. Generate code for Freescale e6500 core complex.
  12912. '-mspe'
  12913. Generate code for Motorola SPE instructions.
  12914. '-mtitan'
  12915. Generate code for AppliedMicro Titan core complex.
  12916. '-mppc64bridge'
  12917. Generate code for PowerPC 64, including bridge insns.
  12918. '-mbooke'
  12919. Generate code for 32-bit BookE.
  12920. '-ma2'
  12921. Generate code for A2 architecture.
  12922. '-me300'
  12923. Generate code for PowerPC e300 family.
  12924. '-maltivec'
  12925. Generate code for processors with AltiVec instructions.
  12926. '-mvle'
  12927. Generate code for Freescale PowerPC VLE instructions.
  12928. '-mvsx'
  12929. Generate code for processors with Vector-Scalar (VSX) instructions.
  12930. '-mhtm'
  12931. Generate code for processors with Hardware Transactional Memory
  12932. instructions.
  12933. '-mpower4, -mpwr4'
  12934. Generate code for Power4 architecture.
  12935. '-mpower5, -mpwr5, -mpwr5x'
  12936. Generate code for Power5 architecture.
  12937. '-mpower6, -mpwr6'
  12938. Generate code for Power6 architecture.
  12939. '-mpower7, -mpwr7'
  12940. Generate code for Power7 architecture.
  12941. '-mpower8, -mpwr8'
  12942. Generate code for Power8 architecture.
  12943. '-mpower9, -mpwr9'
  12944. Generate code for Power9 architecture.
  12945. '-mcell'
  12946. '-mcell'
  12947. Generate code for Cell Broadband Engine architecture.
  12948. '-mcom'
  12949. Generate code Power/PowerPC common instructions.
  12950. '-many'
  12951. Generate code for any architecture (PWR/PWRX/PPC).
  12952. '-mregnames'
  12953. Allow symbolic names for registers.
  12954. '-mno-regnames'
  12955. Do not allow symbolic names for registers.
  12956. '-mrelocatable'
  12957. Support for GCC's -mrelocatable option.
  12958. '-mrelocatable-lib'
  12959. Support for GCC's -mrelocatable-lib option.
  12960. '-memb'
  12961. Set PPC_EMB bit in ELF flags.
  12962. '-mlittle, -mlittle-endian, -le'
  12963. Generate code for a little endian machine.
  12964. '-mbig, -mbig-endian, -be'
  12965. Generate code for a big endian machine.
  12966. '-msolaris'
  12967. Generate code for Solaris.
  12968. '-mno-solaris'
  12969. Do not generate code for Solaris.
  12970. '-nops=COUNT'
  12971. If an alignment directive inserts more than COUNT nops, put a
  12972. branch at the beginning to skip execution of the nops.
  12973. 
  12974. File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent
  12975. 9.35.2 PowerPC Assembler Directives
  12976. -----------------------------------
  12977. A number of assembler directives are available for PowerPC. The
  12978. following table is far from complete.
  12979. '.machine "string"'
  12980. This directive allows you to change the machine for which code is
  12981. generated. '"string"' may be any of the -m cpu selection options
  12982. (without the -m) enclosed in double quotes, '"push"', or '"pop"'.
  12983. '.machine "push"' saves the currently selected cpu, which may be
  12984. restored with '.machine "pop"'.
  12985. 
  12986. File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent
  12987. 9.35.3 PowerPC Syntax
  12988. ---------------------
  12989. * Menu:
  12990. * PowerPC-Chars:: Special Characters
  12991. 
  12992. File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax
  12993. 9.35.3.1 Special Characters
  12994. ...........................
  12995. The presence of a '#' on a line indicates the start of a comment that
  12996. extends to the end of the current line.
  12997. If a '#' appears as the first character of a line then the whole line
  12998. is treated as a comment, but in this case the line could also be a
  12999. logical line number directive (*note Comments::) or a preprocessor
  13000. control command (*note Preprocessing::).
  13001. If the assembler has been configured for the ppc-*-solaris* target
  13002. then the '!' character also acts as a line comment character. This can
  13003. be disabled via the '-mno-solaris' command line option.
  13004. The ';' character can be used to separate statements on the same
  13005. line.
  13006. 
  13007. File: as.info, Node: RL78-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
  13008. 9.36 RL78 Dependent Features
  13009. ============================
  13010. * Menu:
  13011. * RL78-Opts:: RL78 Assembler Command Line Options
  13012. * RL78-Modifiers:: Symbolic Operand Modifiers
  13013. * RL78-Directives:: Assembler Directives
  13014. * RL78-Syntax:: Syntax
  13015. 
  13016. File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent
  13017. 9.36.1 RL78 Options
  13018. -------------------
  13019. 'relax'
  13020. Enable support for link-time relaxation.
  13021. 'norelax'
  13022. Disable support for link-time relaxation (default).
  13023. 'mg10'
  13024. Mark the generated binary as targeting the G10 variant of the RL78
  13025. architecture.
  13026. 'mg13'
  13027. Mark the generated binary as targeting the G13 variant of the RL78
  13028. architecture.
  13029. 'mg14'
  13030. 'mrl78'
  13031. Mark the generated binary as targeting the G14 variant of the RL78
  13032. architecture. This is the default.
  13033. 'm32bit-doubles'
  13034. Mark the generated binary as one that uses 32-bits to hold the
  13035. 'double' floating point type. This is the default.
  13036. 'm64bit-doubles'
  13037. Mark the generated binary as one that uses 64-bits to hold the
  13038. 'double' floating point type.
  13039. 
  13040. File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent
  13041. 9.36.2 Symbolic Operand Modifiers
  13042. ---------------------------------
  13043. The RL78 has three modifiers that adjust the relocations used by the
  13044. linker:
  13045. '%lo16()'
  13046. When loading a 20-bit (or wider) address into registers, this
  13047. modifier selects the 16 least significant bits.
  13048. movw ax,#%lo16(_sym)
  13049. '%hi16()'
  13050. When loading a 20-bit (or wider) address into registers, this
  13051. modifier selects the 16 most significant bits.
  13052. movw ax,#%hi16(_sym)
  13053. '%hi8()'
  13054. When loading a 20-bit (or wider) address into registers, this
  13055. modifier selects the 8 bits that would go into CS or ES (i.e. bits
  13056. 23..16).
  13057. mov es, #%hi8(_sym)
  13058. 
  13059. File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent
  13060. 9.36.3 Assembler Directives
  13061. ---------------------------
  13062. In addition to the common directives, the RL78 adds these:
  13063. '.double'
  13064. Output a constant in "double" format, which is either a 32-bit or a
  13065. 64-bit floating point value, depending upon the setting of the
  13066. '-m32bit-doubles'|'-m64bit-doubles' command line option.
  13067. '.bss'
  13068. Select the BSS section.
  13069. '.3byte'
  13070. Output a constant value in a three byte format.
  13071. '.int'
  13072. '.word'
  13073. Output a constant value in a four byte format.
  13074. 
  13075. File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent
  13076. 9.36.4 Syntax for the RL78
  13077. --------------------------
  13078. * Menu:
  13079. * RL78-Chars:: Special Characters
  13080. 
  13081. File: as.info, Node: RL78-Chars, Up: RL78-Syntax
  13082. 9.36.4.1 Special Characters
  13083. ...........................
  13084. The presence of a ';' appearing anywhere on a line indicates the start
  13085. of a comment that extends to the end of that line.
  13086. If a '#' appears as the first character of a line then the whole line
  13087. is treated as a comment, but in this case the line can also be a logical
  13088. line number directive (*note Comments::) or a preprocessor control
  13089. command (*note Preprocessing::).
  13090. The '|' character can be used to separate statements on the same
  13091. line.
  13092. 
  13093. File: as.info, Node: RISC-V-Dependent, Next: RX-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies
  13094. 9.37 RISC-V Dependent Features
  13095. ==============================
  13096. * Menu:
  13097. * RISC-V-Opts:: RISC-V Options
  13098. 
  13099. File: as.info, Node: RISC-V-Opts, Up: RISC-V-Dependent
  13100. 9.37.1 Options
  13101. --------------
  13102. The following table lists all availiable RISC-V specific options
  13103. '-fpic'
  13104. Generate position-independent code
  13105. '-fno-pic'
  13106. Don't generate position-independent code (default)
  13107. '-march=ISA'
  13108. Select the base isa, as specified by ISA. For example
  13109. -march=rv32ima.
  13110. '-mabi=ABI'
  13111. Selects the ABI, which is either "ilp32" or "lp64", optionally
  13112. followed by "f", "d", or "q" to indicate single-precision,
  13113. double-precision, or quad-precision floating-point calling
  13114. convention, or none to indicate the soft-float calling convention.
  13115. 
  13116. File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies
  13117. 9.38 RX Dependent Features
  13118. ==========================
  13119. * Menu:
  13120. * RX-Opts:: RX Assembler Command Line Options
  13121. * RX-Modifiers:: Symbolic Operand Modifiers
  13122. * RX-Directives:: Assembler Directives
  13123. * RX-Float:: Floating Point
  13124. * RX-Syntax:: Syntax
  13125. 
  13126. File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent
  13127. 9.38.1 RX Options
  13128. -----------------
  13129. The Renesas RX port of 'as' has a few target specfic command line
  13130. options:
  13131. '-m32bit-doubles'
  13132. This option controls the ABI and indicates to use a 32-bit float
  13133. ABI. It has no effect on the assembled instructions, but it does
  13134. influence the behaviour of the '.double' pseudo-op. This is the
  13135. default.
  13136. '-m64bit-doubles'
  13137. This option controls the ABI and indicates to use a 64-bit float
  13138. ABI. It has no effect on the assembled instructions, but it does
  13139. influence the behaviour of the '.double' pseudo-op.
  13140. '-mbig-endian'
  13141. This option controls the ABI and indicates to use a big-endian data
  13142. ABI. It has no effect on the assembled instructions, but it does
  13143. influence the behaviour of the '.short', '.hword', '.int', '.word',
  13144. '.long', '.quad' and '.octa' pseudo-ops.
  13145. '-mlittle-endian'
  13146. This option controls the ABI and indicates to use a little-endian
  13147. data ABI. It has no effect on the assembled instructions, but it
  13148. does influence the behaviour of the '.short', '.hword', '.int',
  13149. '.word', '.long', '.quad' and '.octa' pseudo-ops. This is the
  13150. default.
  13151. '-muse-conventional-section-names'
  13152. This option controls the default names given to the code (.text),
  13153. initialised data (.data) and uninitialised data sections (.bss).
  13154. '-muse-renesas-section-names'
  13155. This option controls the default names given to the code (.P),
  13156. initialised data (.D_1) and uninitialised data sections (.B_1).
  13157. This is the default.
  13158. '-msmall-data-limit'
  13159. This option tells the assembler that the small data limit feature
  13160. of the RX port of GCC is being used. This results in the assembler
  13161. generating an undefined reference to a symbol called '__gp' for use
  13162. by the relocations that are needed to support the small data limit
  13163. feature. This option is not enabled by default as it would
  13164. otherwise pollute the symbol table.
  13165. '-mpid'
  13166. This option tells the assembler that the position independent data
  13167. of the RX port of GCC is being used. This results in the assembler
  13168. generating an undefined reference to a symbol called '__pid_base',
  13169. and also setting the RX_PID flag bit in the e_flags field of the
  13170. ELF header of the object file.
  13171. '-mint-register=NUM'
  13172. This option tells the assembler how many registers have been
  13173. reserved for use by interrupt handlers. This is needed in order to
  13174. compute the correct values for the '%gpreg' and '%pidreg' meta
  13175. registers.
  13176. '-mgcc-abi'
  13177. This option tells the assembler that the old GCC ABI is being used
  13178. by the assembled code. With this version of the ABI function
  13179. arguments that are passed on the stack are aligned to a 32-bit
  13180. boundary.
  13181. '-mrx-abi'
  13182. This option tells the assembler that the official RX ABI is being
  13183. used by the assembled code. With this version of the ABI function
  13184. arguments that are passed on the stack are aligned to their natural
  13185. alignments. This option is the default.
  13186. '-mcpu=NAME'
  13187. This option tells the assembler the target CPU type. Currently the
  13188. 'rx100', 'rx200', 'rx600', 'rx610' and 'rxv2' are recognised as
  13189. valid cpu names. Attempting to assemble an instruction not
  13190. supported by the indicated cpu type will result in an error message
  13191. being generated.
  13192. '-mno-allow-string-insns'
  13193. This option tells the assembler to mark the object file that it is
  13194. building as one that does not use the string instructions 'SMOVF',
  13195. 'SCMPU', 'SMOVB', 'SMOVU', 'SUNTIL' 'SWHILE' or the 'RMPA'
  13196. instruction. In addition the mark tells the linker to complain if
  13197. an attempt is made to link the binary with another one that does
  13198. use any of these instructions.
  13199. Note - the inverse of this option, '-mallow-string-insns', is not
  13200. needed. The assembler automatically detects the use of the the
  13201. instructions in the source code and labels the resulting object
  13202. file appropriately. If no string instructions are detected then
  13203. the object file is labelled as being one that can be linked with
  13204. either string-using or string-banned object files.
  13205. 
  13206. File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent
  13207. 9.38.2 Symbolic Operand Modifiers
  13208. ---------------------------------
  13209. The assembler supports one modifier when using symbol addresses in RX
  13210. instruction operands. The general syntax is the following:
  13211. %gp(symbol)
  13212. The modifier returns the offset from the __GP symbol to the specified
  13213. symbol as a 16-bit value. The intent is that this offset should be used
  13214. in a register+offset move instruction when generating references to
  13215. small data. Ie, like this:
  13216. mov.W %gp(_foo)[%gpreg], r1
  13217. The assembler also supports two meta register names which can be used
  13218. to refer to registers whose values may not be known to the programmer.
  13219. These meta register names are:
  13220. '%gpreg'
  13221. The small data address register.
  13222. '%pidreg'
  13223. The PID base address register.
  13224. Both registers normally have the value r13, but this can change if
  13225. some registers have been reserved for use by interrupt handlers or if
  13226. both the small data limit and position independent data features are
  13227. being used at the same time.
  13228. 
  13229. File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent
  13230. 9.38.3 Assembler Directives
  13231. ---------------------------
  13232. The RX version of 'as' has the following specific assembler directives:
  13233. '.3byte'
  13234. Inserts a 3-byte value into the output file at the current
  13235. location.
  13236. '.fetchalign'
  13237. If the next opcode following this directive spans a fetch line
  13238. boundary (8 byte boundary), the opcode is aligned to that boundary.
  13239. If the next opcode does not span a fetch line, this directive has
  13240. no effect. Note that one or more labels may be between this
  13241. directive and the opcode; those labels are aligned as well. Any
  13242. inserted bytes due to alignment will form a NOP opcode.
  13243. 
  13244. File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent
  13245. 9.38.4 Floating Point
  13246. ---------------------
  13247. The floating point formats generated by directives are these.
  13248. '.float'
  13249. 'Single' precision (32-bit) floating point constants.
  13250. '.double'
  13251. If the '-m64bit-doubles' command line option has been specified
  13252. then then 'double' directive generates 'double' precision (64-bit)
  13253. floating point constants, otherwise it generates 'single' precision
  13254. (32-bit) floating point constants. To force the generation of
  13255. 64-bit floating point constants used the 'dc.d' directive instead.
  13256. 
  13257. File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent
  13258. 9.38.5 Syntax for the RX
  13259. ------------------------
  13260. * Menu:
  13261. * RX-Chars:: Special Characters
  13262. 
  13263. File: as.info, Node: RX-Chars, Up: RX-Syntax
  13264. 9.38.5.1 Special Characters
  13265. ...........................
  13266. The presence of a ';' appearing anywhere on a line indicates the start
  13267. of a comment that extends to the end of that line.
  13268. If a '#' appears as the first character of a line then the whole line
  13269. is treated as a comment, but in this case the line can also be a logical
  13270. line number directive (*note Comments::) or a preprocessor control
  13271. command (*note Preprocessing::).
  13272. The '!' character can be used to separate statements on the same
  13273. line.
  13274. 
  13275. File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies
  13276. 9.39 IBM S/390 Dependent Features
  13277. =================================
  13278. The s390 version of 'as' supports two architectures modes and eleven
  13279. chip levels. The architecture modes are the Enterprise System
  13280. Architecture (ESA) and the newer z/Architecture mode. The chip levels
  13281. are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
  13282. (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or
  13283. arch11), and z14 (or arch12).
  13284. * Menu:
  13285. * s390 Options:: Command-line Options.
  13286. * s390 Characters:: Special Characters.
  13287. * s390 Syntax:: Assembler Instruction syntax.
  13288. * s390 Directives:: Assembler Directives.
  13289. * s390 Floating Point:: Floating Point.
  13290. 
  13291. File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent
  13292. 9.39.1 Options
  13293. --------------
  13294. The following table lists all available s390 specific options:
  13295. '-m31 | -m64'
  13296. Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
  13297. These options are only available with the ELF object file format,
  13298. and require that the necessary BFD support has been included (on a
  13299. 31-bit platform you must add -enable-64-bit-bfd on the call to the
  13300. configure script to enable 64-bit usage and use s390x as target
  13301. platform).
  13302. '-mesa | -mzarch'
  13303. Select the architecture mode, either the Enterprise System
  13304. Architecture (esa) mode or the z/Architecture mode (zarch).
  13305. The 64-bit instructions are only available with the z/Architecture
  13306. mode. The combination of '-m64' and '-mesa' results in a warning
  13307. message.
  13308. '-march=CPU'
  13309. This option specifies the target processor. The following
  13310. processor names are recognized: 'g5' (or 'arch3'), 'g6', 'z900' (or
  13311. 'arch5'), 'z990' (or 'arch6'), 'z9-109', 'z9-ec' (or 'arch7'),
  13312. 'z10' (or 'arch8'), 'z196' (or 'arch9'), 'zEC12' (or 'arch10') and
  13313. 'z13' (or 'arch11').
  13314. Assembling an instruction that is not supported on the target
  13315. processor results in an error message.
  13316. The processor names starting with 'arch' refer to the edition
  13317. number in the Principle of Operations manual. They can be used as
  13318. alternate processor names and have been added for compatibility
  13319. with the IBM XL compiler.
  13320. 'arch3', 'g5' and 'g6' cannot be used with the '-mzarch' option
  13321. since the z/Architecture mode is not supported on these processor
  13322. levels.
  13323. There is no 'arch4' option supported. 'arch4' matches
  13324. '-march=arch5 -mesa'.
  13325. '-mregnames'
  13326. Allow symbolic names for registers.
  13327. '-mno-regnames'
  13328. Do not allow symbolic names for registers.
  13329. '-mwarn-areg-zero'
  13330. Warn whenever the operand for a base or index register has been
  13331. specified but evaluates to zero. This can indicate the misuse of
  13332. general purpose register 0 as an address register.
  13333. 
  13334. File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent
  13335. 9.39.2 Special Characters
  13336. -------------------------
  13337. '#' is the line comment character.
  13338. If a '#' appears as the first character of a line then the whole line
  13339. is treated as a comment, but in this case the line could also be a
  13340. logical line number directive (*note Comments::) or a preprocessor
  13341. control command (*note Preprocessing::).
  13342. The ';' character can be used instead of a newline to separate
  13343. statements.
  13344. 
  13345. File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent
  13346. 9.39.3 Instruction syntax
  13347. -------------------------
  13348. The assembler syntax closely follows the syntax outlined in Enterprise
  13349. Systems Architecture/390 Principles of Operation (SA22-7201) and the
  13350. z/Architecture Principles of Operation (SA22-7832).
  13351. Each instruction has two major parts, the instruction mnemonic and
  13352. the instruction operands. The instruction format varies.
  13353. * Menu:
  13354. * s390 Register:: Register Naming
  13355. * s390 Mnemonics:: Instruction Mnemonics
  13356. * s390 Operands:: Instruction Operands
  13357. * s390 Formats:: Instruction Formats
  13358. * s390 Aliases:: Instruction Aliases
  13359. * s390 Operand Modifier:: Instruction Operand Modifier
  13360. * s390 Instruction Marker:: Instruction Marker
  13361. * s390 Literal Pool Entries:: Literal Pool Entries
  13362. 
  13363. File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax
  13364. 9.39.3.1 Register naming
  13365. ........................
  13366. The 'as' recognizes a number of predefined symbols for the various
  13367. processor registers. A register specification in one of the instruction
  13368. formats is an unsigned integer between 0 and 15. The specific
  13369. instruction and the position of the register in the instruction format
  13370. denotes the type of the register. The register symbols are prefixed
  13371. with '%':
  13372. %rN the 16 general purpose registers, 0 <= N <= 15
  13373. %fN the 16 floating point registers, 0 <= N <= 15
  13374. %aN the 16 access registers, 0 <= N <= 15
  13375. %cN the 16 control registers, 0 <= N <= 15
  13376. %lit an alias for the general purpose register %r13
  13377. %sp an alias for the general purpose register %r15
  13378. 
  13379. File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax
  13380. 9.39.3.2 Instruction Mnemonics
  13381. ..............................
  13382. All instructions documented in the Principles of Operation are supported
  13383. with the mnemonic and order of operands as described. The instruction
  13384. mnemonic identifies the instruction format (*note s390 Formats::) and
  13385. the specific operation code for the instruction. For example, the 'lr'
  13386. mnemonic denotes the instruction format 'RR' with the operation code
  13387. '0x18'.
  13388. The definition of the various mnemonics follows a scheme, where the
  13389. first character usually hint at the type of the instruction:
  13390. a add instruction, for example 'al' for add logical 32-bit
  13391. b branch instruction, for example 'bc' for branch on condition
  13392. c compare or convert instruction, for example 'cr' for compare
  13393. register 32-bit
  13394. d divide instruction, for example 'dlr' devide logical register
  13395. 64-bit to 32-bit
  13396. i insert instruction, for example 'ic' insert character
  13397. l load instruction, for example 'ltr' load and test register
  13398. mv move instruction, for example 'mvc' move character
  13399. m multiply instruction, for example 'mh' multiply halfword
  13400. n and instruction, for example 'ni' and immediate
  13401. o or instruction, for example 'oc' or character
  13402. sla, sll shift left single instruction
  13403. sra, srl shift right single instruction
  13404. st store instruction, for example 'stm' store multiple
  13405. s subtract instruction, for example 'slr' subtract
  13406. logical 32-bit
  13407. t test or translate instruction, of example 'tm' test under mask
  13408. x exclusive or instruction, for example 'xc' exclusive or
  13409. character
  13410. Certain characters at the end of the mnemonic may describe a property
  13411. of the instruction:
  13412. c the instruction uses a 8-bit character operand
  13413. f the instruction extends a 32-bit operand to 64 bit
  13414. g the operands are treated as 64-bit values
  13415. h the operand uses a 16-bit halfword operand
  13416. i the instruction uses an immediate operand
  13417. l the instruction uses unsigned, logical operands
  13418. m the instruction uses a mask or operates on multiple values
  13419. r if r is the last character, the instruction operates on registers
  13420. y the instruction uses 20-bit displacements
  13421. There are many exceptions to the scheme outlined in the above lists,
  13422. in particular for the priviledged instructions. For non-priviledged
  13423. instruction it works quite well, for example the instruction 'clgfr' c:
  13424. compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to
  13425. 64-bit extension, r: register operands. The instruction compares an
  13426. 64-bit value in a register with the zero extended 32-bit value from a
  13427. second register. For a complete list of all mnemonics see appendix B in
  13428. the Principles of Operation.
  13429. 
  13430. File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax
  13431. 9.39.3.3 Instruction Operands
  13432. .............................
  13433. Instruction operands can be grouped into three classes, operands located
  13434. in registers, immediate operands, and operands in storage.
  13435. A register operand can be located in general, floating-point, access,
  13436. or control register. The register is identified by a four-bit field.
  13437. The field containing the register operand is called the R field.
  13438. Immediate operands are contained within the instruction and can have
  13439. 8, 16 or 32 bits. The field containing the immediate operand is called
  13440. the I field. Dependent on the instruction the I field is either signed
  13441. or unsigned.
  13442. A storage operand consists of an address and a length. The address
  13443. of a storage operands can be specified in any of these ways:
  13444. * The content of a single general R
  13445. * The sum of the content of a general register called the base
  13446. register B plus the content of a displacement field D
  13447. * The sum of the contents of two general registers called the index
  13448. register X and the base register B plus the content of a
  13449. displacement field
  13450. * The sum of the current instruction address and a 32-bit signed
  13451. immediate field multiplied by two.
  13452. The length of a storage operand can be:
  13453. * Implied by the instruction
  13454. * Specified by a bitmask
  13455. * Specified by a four-bit or eight-bit length field L
  13456. * Specified by the content of a general register
  13457. The notation for storage operand addresses formed from multiple
  13458. fields is as follows:
  13459. 'Dn(Bn)'
  13460. the address for operand number n is formed from the content of
  13461. general register Bn called the base register and the displacement
  13462. field Dn.
  13463. 'Dn(Xn,Bn)'
  13464. the address for operand number n is formed from the content of
  13465. general register Xn called the index register, general register Bn
  13466. called the base register and the displacement field Dn.
  13467. 'Dn(Ln,Bn)'
  13468. the address for operand number n is formed from the content of
  13469. general regiser Bn called the base register and the displacement
  13470. field Dn. The length of the operand n is specified by the field
  13471. Ln.
  13472. The base registers Bn and the index registers Xn of a storage operand
  13473. can be skipped. If Bn and Xn are skipped, a zero will be stored to the
  13474. operand field. The notation changes as follows:
  13475. full notation short notation
  13476. ----------------------------------------------
  13477. Dn(0,Bn) Dn(Bn)
  13478. Dn(0,0) Dn
  13479. Dn(0) Dn
  13480. Dn(Ln,0) Dn(Ln)
  13481. 
  13482. File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax
  13483. 9.39.3.4 Instruction Formats
  13484. ............................
  13485. The Principles of Operation manuals lists 26 instruction formats where
  13486. some of the formats have multiple variants. For the '.insn' pseudo
  13487. directive the assembler recognizes some of the formats. Typically, the
  13488. most general variant of the instruction format is used by the '.insn'
  13489. directive.
  13490. The following table lists the abbreviations used in the table of
  13491. instruction formats:
  13492. OpCode / OpCd Part of the op code.
  13493. Bx Base register number for operand x.
  13494. Dx Displacement for operand x.
  13495. DLx Displacement lower 12 bits for operand x.
  13496. DHx Displacement higher 8-bits for operand x.
  13497. Rx Register number for operand x.
  13498. Xx Index register number for operand x.
  13499. Ix Signed immediate for operand x.
  13500. Ux Unsigned immediate for operand x.
  13501. An instruction is two, four, or six bytes in length and must be
  13502. aligned on a 2 byte boundary. The first two bits of the instruction
  13503. specify the length of the instruction, 00 indicates a two byte
  13504. instruction, 01 and 10 indicates a four byte instruction, and 11
  13505. indicates a six byte instruction.
  13506. The following table lists the s390 instruction formats that are
  13507. available with the '.insn' pseudo directive:
  13508. 'E format'
  13509. +-------------+
  13510. | OpCode |
  13511. +-------------+
  13512. 0 15
  13513. 'RI format: <insn> R1,I2'
  13514. +--------+----+----+------------------+
  13515. | OpCode | R1 |OpCd| I2 |
  13516. +--------+----+----+------------------+
  13517. 0 8 12 16 31
  13518. 'RIE format: <insn> R1,R3,I2'
  13519. +--------+----+----+------------------+--------+--------+
  13520. | OpCode | R1 | R3 | I2 |////////| OpCode |
  13521. +--------+----+----+------------------+--------+--------+
  13522. 0 8 12 16 32 40 47
  13523. 'RIL format: <insn> R1,I2'
  13524. +--------+----+----+------------------------------------+
  13525. | OpCode | R1 |OpCd| I2 |
  13526. +--------+----+----+------------------------------------+
  13527. 0 8 12 16 47
  13528. 'RILU format: <insn> R1,U2'
  13529. +--------+----+----+------------------------------------+
  13530. | OpCode | R1 |OpCd| U2 |
  13531. +--------+----+----+------------------------------------+
  13532. 0 8 12 16 47
  13533. 'RIS format: <insn> R1,I2,M3,D4(B4)'
  13534. +--------+----+----+----+-------------+--------+--------+
  13535. | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
  13536. +--------+----+----+----+-------------+--------+--------+
  13537. 0 8 12 16 20 32 36 47
  13538. 'RR format: <insn> R1,R2'
  13539. +--------+----+----+
  13540. | OpCode | R1 | R2 |
  13541. +--------+----+----+
  13542. 0 8 12 15
  13543. 'RRE format: <insn> R1,R2'
  13544. +------------------+--------+----+----+
  13545. | OpCode |////////| R1 | R2 |
  13546. +------------------+--------+----+----+
  13547. 0 16 24 28 31
  13548. 'RRF format: <insn> R1,R2,R3,M4'
  13549. +------------------+----+----+----+----+
  13550. | OpCode | R3 | M4 | R1 | R2 |
  13551. +------------------+----+----+----+----+
  13552. 0 16 20 24 28 31
  13553. 'RRS format: <insn> R1,R2,M3,D4(B4)'
  13554. +--------+----+----+----+-------------+----+----+--------+
  13555. | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
  13556. +--------+----+----+----+-------------+----+----+--------+
  13557. 0 8 12 16 20 32 36 40 47
  13558. 'RS format: <insn> R1,R3,D2(B2)'
  13559. +--------+----+----+----+-------------+
  13560. | OpCode | R1 | R3 | B2 | D2 |
  13561. +--------+----+----+----+-------------+
  13562. 0 8 12 16 20 31
  13563. 'RSE format: <insn> R1,R3,D2(B2)'
  13564. +--------+----+----+----+-------------+--------+--------+
  13565. | OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
  13566. +--------+----+----+----+-------------+--------+--------+
  13567. 0 8 12 16 20 32 40 47
  13568. 'RSI format: <insn> R1,R3,I2'
  13569. +--------+----+----+------------------------------------+
  13570. | OpCode | R1 | R3 | I2 |
  13571. +--------+----+----+------------------------------------+
  13572. 0 8 12 16 47
  13573. 'RSY format: <insn> R1,R3,D2(B2)'
  13574. +--------+----+----+----+-------------+--------+--------+
  13575. | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
  13576. +--------+----+----+----+-------------+--------+--------+
  13577. 0 8 12 16 20 32 40 47
  13578. 'RX format: <insn> R1,D2(X2,B2)'
  13579. +--------+----+----+----+-------------+
  13580. | OpCode | R1 | X2 | B2 | D2 |
  13581. +--------+----+----+----+-------------+
  13582. 0 8 12 16 20 31
  13583. 'RXE format: <insn> R1,D2(X2,B2)'
  13584. +--------+----+----+----+-------------+--------+--------+
  13585. | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
  13586. +--------+----+----+----+-------------+--------+--------+
  13587. 0 8 12 16 20 32 40 47
  13588. 'RXF format: <insn> R1,R3,D2(X2,B2)'
  13589. +--------+----+----+----+-------------+----+---+--------+
  13590. | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
  13591. +--------+----+----+----+-------------+----+---+--------+
  13592. 0 8 12 16 20 32 36 40 47
  13593. 'RXY format: <insn> R1,D2(X2,B2)'
  13594. +--------+----+----+----+-------------+--------+--------+
  13595. | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
  13596. +--------+----+----+----+-------------+--------+--------+
  13597. 0 8 12 16 20 32 36 40 47
  13598. 'S format: <insn> D2(B2)'
  13599. +------------------+----+-------------+
  13600. | OpCode | B2 | D2 |
  13601. +------------------+----+-------------+
  13602. 0 16 20 31
  13603. 'SI format: <insn> D1(B1),I2'
  13604. +--------+---------+----+-------------+
  13605. | OpCode | I2 | B1 | D1 |
  13606. +--------+---------+----+-------------+
  13607. 0 8 16 20 31
  13608. 'SIY format: <insn> D1(B1),U2'
  13609. +--------+---------+----+-------------+--------+--------+
  13610. | OpCode | I2 | B1 | DL1 | DH1 | OpCode |
  13611. +--------+---------+----+-------------+--------+--------+
  13612. 0 8 16 20 32 36 40 47
  13613. 'SIL format: <insn> D1(B1),I2'
  13614. +------------------+----+-------------+-----------------+
  13615. | OpCode | B1 | D1 | I2 |
  13616. +------------------+----+-------------+-----------------+
  13617. 0 16 20 32 47
  13618. 'SS format: <insn> D1(R1,B1),D2(B3),R3'
  13619. +--------+----+----+----+-------------+----+------------+
  13620. | OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
  13621. +--------+----+----+----+-------------+----+------------+
  13622. 0 8 12 16 20 32 36 47
  13623. 'SSE format: <insn> D1(B1),D2(B2)'
  13624. +------------------+----+-------------+----+------------+
  13625. | OpCode | B1 | D1 | B2 | D2 |
  13626. +------------------+----+-------------+----+------------+
  13627. 0 8 12 16 20 32 36 47
  13628. 'SSF format: <insn> D1(B1),D2(B2),R3'
  13629. +--------+----+----+----+-------------+----+------------+
  13630. | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
  13631. +--------+----+----+----+-------------+----+------------+
  13632. 0 8 12 16 20 32 36 47
  13633. For the complete list of all instruction format variants see the
  13634. Principles of Operation manuals.
  13635. 
  13636. File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax
  13637. 9.39.3.5 Instruction Aliases
  13638. ............................
  13639. A specific bit pattern can have multiple mnemonics, for example the bit
  13640. pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition,
  13641. there are a number of mnemonics recognized by 'as' that are not present
  13642. in the Principles of Operation. These are the short forms of the branch
  13643. instructions, where the condition code mask operand is encoded in the
  13644. mnemonic. This is relevant for the branch instructions, the compare and
  13645. branch instructions, and the compare and trap instructions.
  13646. For the branch instructions there are 20 condition code strings that
  13647. can be used as part of the mnemonic in place of a mask operand in the
  13648. instruction format:
  13649. instruction short form
  13650. ----------------------------------------------
  13651. bcr M1,R2 b<m>r R2
  13652. bc M1,D2(X2,B2) b<m> D2(X2,B2)
  13653. brc M1,I2 j<m> I2
  13654. brcl M1,I2 jg<m> I2
  13655. In the mnemonic for a branch instruction the condition code string
  13656. <m> can be any of the following:
  13657. o jump on overflow / if ones
  13658. h jump on A high
  13659. p jump on plus
  13660. nle jump on not low or equal
  13661. l jump on A low
  13662. m jump on minus
  13663. nhe jump on not high or equal
  13664. lh jump on low or high
  13665. ne jump on A not equal B
  13666. nz jump on not zero / if not zeros
  13667. e jump on A equal B
  13668. z jump on zero / if zeroes
  13669. nlh jump on not low or high
  13670. he jump on high or equal
  13671. nl jump on A not low
  13672. nm jump on not minus / if not mixed
  13673. le jump on low or equal
  13674. nh jump on A not high
  13675. np jump on not plus
  13676. no jump on not overflow / if not ones
  13677. For the compare and branch, and compare and trap instructions there
  13678. are 12 condition code strings that can be used as part of the mnemonic
  13679. in place of a mask operand in the instruction format:
  13680. instruction short form
  13681. ------------------------------------------------------------
  13682. crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4)
  13683. cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4)
  13684. crj R1,R2,M3,I4 crj<m> R1,R2,I4
  13685. cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4
  13686. cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4)
  13687. cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4)
  13688. cij R1,I2,M3,I4 cij<m> R1,I2,I4
  13689. cgij R1,I2,M3,I4 cgij<m> R1,I2,I4
  13690. crt R1,R2,M3 crt<m> R1,R2
  13691. cgrt R1,R2,M3 cgrt<m> R1,R2
  13692. cit R1,I2,M3 cit<m> R1,I2
  13693. cgit R1,I2,M3 cgit<m> R1,I2
  13694. clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4)
  13695. clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4)
  13696. clrj R1,R2,M3,I4 clrj<m> R1,R2,I4
  13697. clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4
  13698. clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4)
  13699. clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4)
  13700. clij R1,I2,M3,I4 clij<m> R1,I2,I4
  13701. clgij R1,I2,M3,I4 clgij<m> R1,I2,I4
  13702. clrt R1,R2,M3 clrt<m> R1,R2
  13703. clgrt R1,R2,M3 clgrt<m> R1,R2
  13704. clfit R1,I2,M3 clfit<m> R1,I2
  13705. clgit R1,I2,M3 clgit<m> R1,I2
  13706. In the mnemonic for a compare and branch and compare and trap
  13707. instruction the condition code string <m> can be any of the following:
  13708. h jump on A high
  13709. nle jump on not low or equal
  13710. l jump on A low
  13711. nhe jump on not high or equal
  13712. ne jump on A not equal B
  13713. lh jump on low or high
  13714. e jump on A equal B
  13715. nlh jump on not low or high
  13716. nl jump on A not low
  13717. he jump on high or equal
  13718. nh jump on A not high
  13719. le jump on low or equal
  13720. 
  13721. File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax
  13722. 9.39.3.6 Instruction Operand Modifier
  13723. .....................................
  13724. If a symbol modifier is attached to a symbol in an expression for an
  13725. instruction operand field, the symbol term is replaced with a reference
  13726. to an object in the global offset table (GOT) or the procedure linkage
  13727. table (PLT). The following expressions are allowed: 'symbol@modifier +
  13728. constant', 'symbol@modifier + label + constant', and 'symbol@modifier -
  13729. label + constant'. The term 'symbol' is the symbol that will be entered
  13730. into the GOT or PLT, 'label' is a local label, and 'constant' is an
  13731. arbitrary expression that the assembler can evaluate to a constant
  13732. value.
  13733. The term '(symbol + constant1)@modifier +/- label + constant2' is
  13734. also accepted but a warning message is printed and the term is converted
  13735. to 'symbol@modifier +/- label + constant1 + constant2'.
  13736. '@got'
  13737. '@got12'
  13738. The @got modifier can be used for displacement fields, 16-bit
  13739. immediate fields and 32-bit pc-relative immediate fields. The
  13740. @got12 modifier is synonym to @got. The symbol is added to the
  13741. GOT. For displacement fields and 16-bit immediate fields the symbol
  13742. term is replaced with the offset from the start of the GOT to the
  13743. GOT slot for the symbol. For a 32-bit pc-relative field the
  13744. pc-relative offset to the GOT slot from the current instruction
  13745. address is used.
  13746. '@gotent'
  13747. The @gotent modifier can be used for 32-bit pc-relative immediate
  13748. fields. The symbol is added to the GOT and the symbol term is
  13749. replaced with the pc-relative offset from the current instruction
  13750. to the GOT slot for the symbol.
  13751. '@gotoff'
  13752. The @gotoff modifier can be used for 16-bit immediate fields. The
  13753. symbol term is replaced with the offset from the start of the GOT
  13754. to the address of the symbol.
  13755. '@gotplt'
  13756. The @gotplt modifier can be used for displacement fields, 16-bit
  13757. immediate fields, and 32-bit pc-relative immediate fields. A
  13758. procedure linkage table entry is generated for the symbol and a
  13759. jump slot for the symbol is added to the GOT. For displacement
  13760. fields and 16-bit immediate fields the symbol term is replaced with
  13761. the offset from the start of the GOT to the jump slot for the
  13762. symbol. For a 32-bit pc-relative field the pc-relative offset to
  13763. the jump slot from the current instruction address is used.
  13764. '@plt'
  13765. The @plt modifier can be used for 16-bit and 32-bit pc-relative
  13766. immediate fields. A procedure linkage table entry is generated for
  13767. the symbol. The symbol term is replaced with the relative offset
  13768. from the current instruction to the PLT entry for the symbol.
  13769. '@pltoff'
  13770. The @pltoff modifier can be used for 16-bit immediate fields. The
  13771. symbol term is replaced with the offset from the start of the PLT
  13772. to the address of the symbol.
  13773. '@gotntpoff'
  13774. The @gotntpoff modifier can be used for displacement fields. The
  13775. symbol is added to the static TLS block and the negated offset to
  13776. the symbol in the static TLS block is added to the GOT. The symbol
  13777. term is replaced with the offset to the GOT slot from the start of
  13778. the GOT.
  13779. '@indntpoff'
  13780. The @indntpoff modifier can be used for 32-bit pc-relative
  13781. immediate fields. The symbol is added to the static TLS block and
  13782. the negated offset to the symbol in the static TLS block is added
  13783. to the GOT. The symbol term is replaced with the pc-relative offset
  13784. to the GOT slot from the current instruction address.
  13785. For more information about the thread local storage modifiers
  13786. 'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF
  13787. Handling For Thread-Local Storage'.
  13788. 
  13789. File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax
  13790. 9.39.3.7 Instruction Marker
  13791. ...........................
  13792. The thread local storage instruction markers are used by the linker to
  13793. perform code optimization.
  13794. ':tls_load'
  13795. The :tls_load marker is used to flag the load instruction in the
  13796. initial exec TLS model that retrieves the offset from the thread
  13797. pointer to a thread local storage variable from the GOT.
  13798. ':tls_gdcall'
  13799. The :tls_gdcall marker is used to flag the branch-and-save
  13800. instruction to the __tls_get_offset function in the global dynamic
  13801. TLS model.
  13802. ':tls_ldcall'
  13803. The :tls_ldcall marker is used to flag the branch-and-save
  13804. instruction to the __tls_get_offset function in the local dynamic
  13805. TLS model.
  13806. For more information about the thread local storage instruction
  13807. marker and the linker optimizations see the ELF extension documentation
  13808. 'ELF Handling For Thread-Local Storage'.
  13809. 
  13810. File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax
  13811. 9.39.3.8 Literal Pool Entries
  13812. .............................
  13813. A literal pool is a collection of values. To access the values a
  13814. pointer to the literal pool is loaded to a register, the literal pool
  13815. register. Usually, register %r13 is used as the literal pool register
  13816. (*note s390 Register::). Literal pool entries are created by adding the
  13817. suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
  13818. instruction operand. The expression is added to the literal pool and
  13819. the operand is replaced with the offset to the literal in the literal
  13820. pool.
  13821. ':lit1'
  13822. The literal pool entry is created as an 8-bit value. An operand
  13823. modifier must not be used for the original expression.
  13824. ':lit2'
  13825. The literal pool entry is created as a 16 bit value. The operand
  13826. modifier @got may be used in the original expression. The term
  13827. 'x@got:lit2' will put the got offset for the global symbol x to the
  13828. literal pool as 16 bit value.
  13829. ':lit4'
  13830. The literal pool entry is created as a 32-bit value. The operand
  13831. modifier @got and @plt may be used in the original expression. The
  13832. term 'x@got:lit4' will put the got offset for the global symbol x
  13833. to the literal pool as a 32-bit value. The term 'x@plt:lit4' will
  13834. put the plt offset for the global symbol x to the literal pool as a
  13835. 32-bit value.
  13836. ':lit8'
  13837. The literal pool entry is created as a 64-bit value. The operand
  13838. modifier @got and @plt may be used in the original expression. The
  13839. term 'x@got:lit8' will put the got offset for the global symbol x
  13840. to the literal pool as a 64-bit value. The term 'x@plt:lit8' will
  13841. put the plt offset for the global symbol x to the literal pool as a
  13842. 64-bit value.
  13843. The assembler directive '.ltorg' is used to emit all literal pool
  13844. entries to the current position.
  13845. 
  13846. File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent
  13847. 9.39.4 Assembler Directives
  13848. ---------------------------
  13849. 'as' for s390 supports all of the standard ELF assembler directives as
  13850. outlined in the main part of this document. Some directives have been
  13851. extended and there are some additional directives, which are only
  13852. available for the s390 'as'.
  13853. '.insn'
  13854. This directive permits the numeric representation of an
  13855. instructions and makes the assembler insert the operands according
  13856. to one of the instructions formats for '.insn' (*note s390
  13857. Formats::). For example, the instruction 'l %r1,24(%r15)' could be
  13858. written as '.insn rx,0x58000000,%r1,24(%r15)'.
  13859. '.short'
  13860. '.long'
  13861. '.quad'
  13862. This directive places one or more 16-bit (.short), 32-bit (.long),
  13863. or 64-bit (.quad) values into the current section. If an ELF or
  13864. TLS modifier is used only the following expressions are allowed:
  13865. 'symbol@modifier + constant', 'symbol@modifier + label + constant',
  13866. and 'symbol@modifier - label + constant'. The following modifiers
  13867. are available:
  13868. '@got'
  13869. '@got12'
  13870. The @got modifier can be used for .short, .long and .quad.
  13871. The @got12 modifier is synonym to @got. The symbol is added
  13872. to the GOT. The symbol term is replaced with offset from the
  13873. start of the GOT to the GOT slot for the symbol.
  13874. '@gotoff'
  13875. The @gotoff modifier can be used for .short, .long and .quad.
  13876. The symbol term is replaced with the offset from the start of
  13877. the GOT to the address of the symbol.
  13878. '@gotplt'
  13879. The @gotplt modifier can be used for .long and .quad. A
  13880. procedure linkage table entry is generated for the symbol and
  13881. a jump slot for the symbol is added to the GOT. The symbol
  13882. term is replaced with the offset from the start of the GOT to
  13883. the jump slot for the symbol.
  13884. '@plt'
  13885. The @plt modifier can be used for .long and .quad. A
  13886. procedure linkage table entry us generated for the symbol.
  13887. The symbol term is replaced with the address of the PLT entry
  13888. for the symbol.
  13889. '@pltoff'
  13890. The @pltoff modifier can be used for .short, .long and .quad.
  13891. The symbol term is replaced with the offset from the start of
  13892. the PLT to the address of the symbol.
  13893. '@tlsgd'
  13894. '@tlsldm'
  13895. The @tlsgd and @tlsldm modifier can be used for .long and
  13896. .quad. A tls_index structure for the symbol is added to the
  13897. GOT. The symbol term is replaced with the offset from the
  13898. start of the GOT to the tls_index structure.
  13899. '@gotntpoff'
  13900. '@indntpoff'
  13901. The @gotntpoff and @indntpoff modifier can be used for .long
  13902. and .quad. The symbol is added to the static TLS block and
  13903. the negated offset to the symbol in the static TLS block is
  13904. added to the GOT. For @gotntpoff the symbol term is replaced
  13905. with the offset from the start of the GOT to the GOT slot, for
  13906. @indntpoff the symbol term is replaced with the address of the
  13907. GOT slot.
  13908. '@dtpoff'
  13909. The @dtpoff modifier can be used for .long and .quad. The
  13910. symbol term is replaced with the offset of the symbol relative
  13911. to the start of the TLS block it is contained in.
  13912. '@ntpoff'
  13913. The @ntpoff modifier can be used for .long and .quad. The
  13914. symbol term is replaced with the offset of the symbol relative
  13915. to the TCB pointer.
  13916. For more information about the thread local storage modifiers see
  13917. the ELF extension documentation 'ELF Handling For Thread-Local
  13918. Storage'.
  13919. '.ltorg'
  13920. This directive causes the current contents of the literal pool to
  13921. be dumped to the current location (*note s390 Literal Pool
  13922. Entries::).
  13923. '.machine STRING[+EXTENSION]...'
  13924. This directive allows changing the machine for which code is
  13925. generated. 'string' may be any of the '-march=' selection options,
  13926. or 'push', or 'pop'. '.machine push' saves the currently selected
  13927. cpu, which may be restored with '.machine pop'. Be aware that the
  13928. cpu string has to be put into double quotes in case it contains
  13929. characters not appropriate for identifiers. So you have to write
  13930. '"z9-109"' instead of just 'z9-109'. Extensions can be specified
  13931. after the cpu name, separated by plus charaters. Valid extensions
  13932. are: 'htm', 'nohtm', 'vx', 'novx'. They extend the basic
  13933. instruction set with features from a higher cpu level, or remove
  13934. support for a feature from the given cpu level.
  13935. Example: 'z13+nohtm' allows all instructions of the z13 cpu except
  13936. instructions from the HTM facility.
  13937. '.machinemode string'
  13938. This directive allows to change the architecture mode for which
  13939. code is being generated. 'string' may be 'esa', 'zarch',
  13940. 'zarch_nohighgprs', 'push', or 'pop'. '.machinemode
  13941. zarch_nohighgprs' can be used to prevent the 'highgprs' flag from
  13942. being set in the ELF header of the output file. This is useful in
  13943. situations where the code is gated with a runtime check which makes
  13944. sure that the code is only executed on kernels providing the
  13945. 'highgprs' feature. '.machinemode push' saves the currently
  13946. selected mode, which may be restored with '.machinemode pop'.
  13947. 
  13948. File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent
  13949. 9.39.5 Floating Point
  13950. ---------------------
  13951. The assembler recognizes both the IEEE floating-point instruction and
  13952. the hexadecimal floating-point instructions. The floating-point
  13953. constructors '.float', '.single', and '.double' always emit the IEEE
  13954. format. To assemble hexadecimal floating-point constants the '.long'
  13955. and '.quad' directives must be used.
  13956. 
  13957. File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies
  13958. 9.40 SCORE Dependent Features
  13959. =============================
  13960. * Menu:
  13961. * SCORE-Opts:: Assembler options
  13962. * SCORE-Pseudo:: SCORE Assembler Directives
  13963. * SCORE-Syntax:: Syntax
  13964. 
  13965. File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent
  13966. 9.40.1 Options
  13967. --------------
  13968. The following table lists all available SCORE options.
  13969. '-G NUM'
  13970. This option sets the largest size of an object that can be
  13971. referenced implicitly with the 'gp' register. The default value is
  13972. 8.
  13973. '-EB'
  13974. Assemble code for a big-endian cpu
  13975. '-EL'
  13976. Assemble code for a little-endian cpu
  13977. '-FIXDD'
  13978. Assemble code for fix data dependency
  13979. '-NWARN'
  13980. Assemble code for no warning message for fix data dependency
  13981. '-SCORE5'
  13982. Assemble code for target is SCORE5
  13983. '-SCORE5U'
  13984. Assemble code for target is SCORE5U
  13985. '-SCORE7'
  13986. Assemble code for target is SCORE7, this is default setting
  13987. '-SCORE3'
  13988. Assemble code for target is SCORE3
  13989. '-march=score7'
  13990. Assemble code for target is SCORE7, this is default setting
  13991. '-march=score3'
  13992. Assemble code for target is SCORE3
  13993. '-USE_R1'
  13994. Assemble code for no warning message when using temp register r1
  13995. '-KPIC'
  13996. Generate code for PIC. This option tells the assembler to generate
  13997. score position-independent macro expansions. It also tells the
  13998. assembler to mark the output file as PIC.
  13999. '-O0'
  14000. Assembler will not perform any optimizations
  14001. '-V'
  14002. Sunplus release version
  14003. 
  14004. File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent
  14005. 9.40.2 SCORE Assembler Directives
  14006. ---------------------------------
  14007. A number of assembler directives are available for SCORE. The following
  14008. table is far from complete.
  14009. '.set nwarn'
  14010. Let the assembler not to generate warnings if the source machine
  14011. language instructions happen data dependency.
  14012. '.set fixdd'
  14013. Let the assembler to insert bubbles (32 bit nop instruction / 16
  14014. bit nop! Instruction) if the source machine language instructions
  14015. happen data dependency.
  14016. '.set nofixdd'
  14017. Let the assembler to generate warnings if the source machine
  14018. language instructions happen data dependency. (Default)
  14019. '.set r1'
  14020. Let the assembler not to generate warnings if the source program
  14021. uses r1. allow user to use r1
  14022. 'set nor1'
  14023. Let the assembler to generate warnings if the source program uses
  14024. r1. (Default)
  14025. '.sdata'
  14026. Tell the assembler to add subsequent data into the sdata section
  14027. '.rdata'
  14028. Tell the assembler to add subsequent data into the rdata section
  14029. '.frame "frame-register", "offset", "return-pc-register"'
  14030. Describe a stack frame. "frame-register" is the frame register,
  14031. "offset" is the distance from the frame register to the virtual
  14032. frame pointer, "return-pc-register" is the return program register.
  14033. You must use ".ent" before ".frame" and only one ".frame" can be
  14034. used per ".ent".
  14035. '.mask "bitmask", "frameoffset"'
  14036. Indicate which of the integer registers are saved in the current
  14037. function's stack frame, this is for the debugger to explain the
  14038. frame chain.
  14039. '.ent "proc-name"'
  14040. Set the beginning of the procedure "proc_name". Use this directive
  14041. when you want to generate information for the debugger.
  14042. '.end proc-name'
  14043. Set the end of a procedure. Use this directive to generate
  14044. information for the debugger.
  14045. '.bss'
  14046. Switch the destination of following statements into the bss
  14047. section, which is used for data that is uninitialized anywhere.
  14048. 
  14049. File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent
  14050. 9.40.3 SCORE Syntax
  14051. -------------------
  14052. * Menu:
  14053. * SCORE-Chars:: Special Characters
  14054. 
  14055. File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax
  14056. 9.40.3.1 Special Characters
  14057. ...........................
  14058. The presence of a '#' appearing anywhere on a line indicates the start
  14059. of a comment that extends to the end of that line.
  14060. If a '#' appears as the first character of a line then the whole line
  14061. is treated as a comment, but in this case the line can also be a logical
  14062. line number directive (*note Comments::) or a preprocessor control
  14063. command (*note Preprocessing::).
  14064. The ';' character can be used to separate statements on the same
  14065. line.
  14066. 
  14067. File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies
  14068. 9.41 Renesas / SuperH SH Dependent Features
  14069. ===========================================
  14070. * Menu:
  14071. * SH Options:: Options
  14072. * SH Syntax:: Syntax
  14073. * SH Floating Point:: Floating Point
  14074. * SH Directives:: SH Machine Directives
  14075. * SH Opcodes:: Opcodes
  14076. 
  14077. File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
  14078. 9.41.1 Options
  14079. --------------
  14080. 'as' has following command-line options for the Renesas (formerly
  14081. Hitachi) / SuperH SH family.
  14082. '--little'
  14083. Generate little endian code.
  14084. '--big'
  14085. Generate big endian code.
  14086. '--relax'
  14087. Alter jump instructions for long displacements.
  14088. '--small'
  14089. Align sections to 4 byte boundaries, not 16.
  14090. '--dsp'
  14091. Enable sh-dsp insns, and disable sh3e / sh4 insns.
  14092. '--renesas'
  14093. Disable optimization with section symbol for compatibility with
  14094. Renesas assembler.
  14095. '--allow-reg-prefix'
  14096. Allow '$' as a register name prefix.
  14097. '--fdpic'
  14098. Generate an FDPIC object file.
  14099. '--isa=sh4 | sh4a'
  14100. Specify the sh4 or sh4a instruction set.
  14101. '--isa=dsp'
  14102. Enable sh-dsp insns, and disable sh3e / sh4 insns.
  14103. '--isa=fp'
  14104. Enable sh2e, sh3e, sh4, and sh4a insn sets.
  14105. '--isa=all'
  14106. Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
  14107. '-h-tick-hex'
  14108. Support H'00 style hex constants in addition to 0x00 style.
  14109. 
  14110. File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
  14111. 9.41.2 Syntax
  14112. -------------
  14113. * Menu:
  14114. * SH-Chars:: Special Characters
  14115. * SH-Regs:: Register Names
  14116. * SH-Addressing:: Addressing Modes
  14117. 
  14118. File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
  14119. 9.41.2.1 Special Characters
  14120. ...........................
  14121. '!' is the line comment character.
  14122. You can use ';' instead of a newline to separate statements.
  14123. If a '#' appears as the first character of a line then the whole line
  14124. is treated as a comment, but in this case the line could also be a
  14125. logical line number directive (*note Comments::) or a preprocessor
  14126. control command (*note Preprocessing::).
  14127. Since '$' has no special meaning, you may use it in symbol names.
  14128. 
  14129. File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
  14130. 9.41.2.2 Register Names
  14131. .......................
  14132. You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5',
  14133. 'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to
  14134. refer to the SH registers.
  14135. The SH also has these control registers:
  14136. 'pr'
  14137. procedure register (holds return address)
  14138. 'pc'
  14139. program counter
  14140. 'mach'
  14141. 'macl'
  14142. high and low multiply accumulator registers
  14143. 'sr'
  14144. status register
  14145. 'gbr'
  14146. global base register
  14147. 'vbr'
  14148. vector base register (for interrupt vectors)
  14149. 
  14150. File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
  14151. 9.41.2.3 Addressing Modes
  14152. .........................
  14153. 'as' understands the following addressing modes for the SH. 'RN' in the
  14154. following refers to any of the numbered registers, but _not_ the control
  14155. registers.
  14156. 'RN'
  14157. Register direct
  14158. '@RN'
  14159. Register indirect
  14160. '@-RN'
  14161. Register indirect with pre-decrement
  14162. '@RN+'
  14163. Register indirect with post-increment
  14164. '@(DISP, RN)'
  14165. Register indirect with displacement
  14166. '@(R0, RN)'
  14167. Register indexed
  14168. '@(DISP, GBR)'
  14169. 'GBR' offset
  14170. '@(R0, GBR)'
  14171. GBR indexed
  14172. 'ADDR'
  14173. '@(DISP, PC)'
  14174. PC relative address (for branch or for addressing memory). The
  14175. 'as' implementation allows you to use the simpler form ADDR
  14176. anywhere a PC relative address is called for; the alternate form is
  14177. supported for compatibility with other assemblers.
  14178. '#IMM'
  14179. Immediate data
  14180. 
  14181. File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
  14182. 9.41.3 Floating Point
  14183. ---------------------
  14184. SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
  14185. SH groups can use '.float' directive to generate IEEE floating-point
  14186. numbers.
  14187. SH2E and SH3E support single-precision floating point calculations as
  14188. well as entirely PCAPI compatible emulation of double-precision floating
  14189. point calculations. SH2E and SH3E instructions are a subset of the
  14190. floating point calculations conforming to the IEEE754 standard.
  14191. In addition to single-precision and double-precision floating-point
  14192. operation capability, the on-chip FPU of SH4 has a 128-bit graphic
  14193. engine that enables 32-bit floating-point data to be processed 128 bits
  14194. at a time. It also supports 4 * 4 array operations and inner product
  14195. operations. Also, a superscalar architecture is employed that enables
  14196. simultaneous execution of two instructions (including FPU instructions),
  14197. providing performance of up to twice that of conventional architectures
  14198. at the same frequency.
  14199. 
  14200. File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
  14201. 9.41.4 SH Machine Directives
  14202. ----------------------------
  14203. 'uaword'
  14204. 'ualong'
  14205. 'uaquad'
  14206. 'as' will issue a warning when a misaligned '.word', '.long', or
  14207. '.quad' directive is used. You may use '.uaword', '.ualong', or
  14208. '.uaquad' to indicate that the value is intentionally misaligned.
  14209. 
  14210. File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
  14211. 9.41.5 Opcodes
  14212. --------------
  14213. For detailed information on the SH machine instruction set, see
  14214. 'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core
  14215. Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH).
  14216. 'as' implements all the standard SH opcodes. No additional
  14217. pseudo-instructions are needed on this family. Note, however, that
  14218. because 'as' supports a simpler form of PC-relative addressing, you may
  14219. simply write (for example)
  14220. mov.l bar,r0
  14221. where other assemblers might require an explicit displacement to 'bar'
  14222. from the program counter:
  14223. mov.l @(DISP, PC)
  14224. Here is a summary of SH opcodes:
  14225. Legend:
  14226. Rn a numbered register
  14227. Rm another numbered register
  14228. #imm immediate data
  14229. disp displacement
  14230. disp8 8-bit displacement
  14231. disp12 12-bit displacement
  14232. add #imm,Rn lds.l @Rn+,PR
  14233. add Rm,Rn mac.w @Rm+,@Rn+
  14234. addc Rm,Rn mov #imm,Rn
  14235. addv Rm,Rn mov Rm,Rn
  14236. and #imm,R0 mov.b Rm,@(R0,Rn)
  14237. and Rm,Rn mov.b Rm,@-Rn
  14238. and.b #imm,@(R0,GBR) mov.b Rm,@Rn
  14239. bf disp8 mov.b @(disp,Rm),R0
  14240. bra disp12 mov.b @(disp,GBR),R0
  14241. bsr disp12 mov.b @(R0,Rm),Rn
  14242. bt disp8 mov.b @Rm+,Rn
  14243. clrmac mov.b @Rm,Rn
  14244. clrt mov.b R0,@(disp,Rm)
  14245. cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
  14246. cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
  14247. cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
  14248. cmp/gt Rm,Rn mov.l Rm,@-Rn
  14249. cmp/hi Rm,Rn mov.l Rm,@Rn
  14250. cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
  14251. cmp/pl Rn mov.l @(disp,GBR),R0
  14252. cmp/pz Rn mov.l @(disp,PC),Rn
  14253. cmp/str Rm,Rn mov.l @(R0,Rm),Rn
  14254. div0s Rm,Rn mov.l @Rm+,Rn
  14255. div0u mov.l @Rm,Rn
  14256. div1 Rm,Rn mov.l R0,@(disp,GBR)
  14257. exts.b Rm,Rn mov.w Rm,@(R0,Rn)
  14258. exts.w Rm,Rn mov.w Rm,@-Rn
  14259. extu.b Rm,Rn mov.w Rm,@Rn
  14260. extu.w Rm,Rn mov.w @(disp,Rm),R0
  14261. jmp @Rn mov.w @(disp,GBR),R0
  14262. jsr @Rn mov.w @(disp,PC),Rn
  14263. ldc Rn,GBR mov.w @(R0,Rm),Rn
  14264. ldc Rn,SR mov.w @Rm+,Rn
  14265. ldc Rn,VBR mov.w @Rm,Rn
  14266. ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
  14267. ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
  14268. ldc.l @Rn+,VBR mova @(disp,PC),R0
  14269. lds Rn,MACH movt Rn
  14270. lds Rn,MACL muls Rm,Rn
  14271. lds Rn,PR mulu Rm,Rn
  14272. lds.l @Rn+,MACH neg Rm,Rn
  14273. lds.l @Rn+,MACL negc Rm,Rn
  14274. nop stc VBR,Rn
  14275. not Rm,Rn stc.l GBR,@-Rn
  14276. or #imm,R0 stc.l SR,@-Rn
  14277. or Rm,Rn stc.l VBR,@-Rn
  14278. or.b #imm,@(R0,GBR) sts MACH,Rn
  14279. rotcl Rn sts MACL,Rn
  14280. rotcr Rn sts PR,Rn
  14281. rotl Rn sts.l MACH,@-Rn
  14282. rotr Rn sts.l MACL,@-Rn
  14283. rte sts.l PR,@-Rn
  14284. rts sub Rm,Rn
  14285. sett subc Rm,Rn
  14286. shal Rn subv Rm,Rn
  14287. shar Rn swap.b Rm,Rn
  14288. shll Rn swap.w Rm,Rn
  14289. shll16 Rn tas.b @Rn
  14290. shll2 Rn trapa #imm
  14291. shll8 Rn tst #imm,R0
  14292. shlr Rn tst Rm,Rn
  14293. shlr16 Rn tst.b #imm,@(R0,GBR)
  14294. shlr2 Rn xor #imm,R0
  14295. shlr8 Rn xor Rm,Rn
  14296. sleep xor.b #imm,@(R0,GBR)
  14297. stc GBR,Rn xtrct Rm,Rn
  14298. stc SR,Rn
  14299. 
  14300. File: as.info, Node: SH64-Dependent, Next: Sparc-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
  14301. 9.42 SuperH SH64 Dependent Features
  14302. ===================================
  14303. * Menu:
  14304. * SH64 Options:: Options
  14305. * SH64 Syntax:: Syntax
  14306. * SH64 Directives:: SH64 Machine Directives
  14307. * SH64 Opcodes:: Opcodes
  14308. 
  14309. File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent
  14310. 9.42.1 Options
  14311. --------------
  14312. '-isa=sh4 | sh4a'
  14313. Specify the sh4 or sh4a instruction set.
  14314. '-isa=dsp'
  14315. Enable sh-dsp insns, and disable sh3e / sh4 insns.
  14316. '-isa=fp'
  14317. Enable sh2e, sh3e, sh4, and sh4a insn sets.
  14318. '-isa=all'
  14319. Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
  14320. '-isa=shmedia | -isa=shcompact'
  14321. Specify the default instruction set. 'SHmedia' specifies the
  14322. 32-bit opcodes, and 'SHcompact' specifies the 16-bit opcodes
  14323. compatible with previous SH families. The default depends on the
  14324. ABI selected; the default for the 64-bit ABI is SHmedia, and the
  14325. default for the 32-bit ABI is SHcompact. If neither the ABI nor
  14326. the ISA is specified, the default is 32-bit SHcompact.
  14327. Note that the '.mode' pseudo-op is not permitted if the ISA is not
  14328. specified on the command line.
  14329. '-abi=32 | -abi=64'
  14330. Specify the default ABI. If the ISA is specified and the ABI is
  14331. not, the default ABI depends on the ISA, with SHmedia defaulting to
  14332. 64-bit and SHcompact defaulting to 32-bit.
  14333. Note that the '.abi' pseudo-op is not permitted if the ABI is not
  14334. specified on the command line. When the ABI is specified on the
  14335. command line, any '.abi' pseudo-ops in the source must match it.
  14336. '-shcompact-const-crange'
  14337. Emit code-range descriptors for constants in SHcompact code
  14338. sections.
  14339. '-no-mix'
  14340. Disallow SHmedia code in the same section as constants and
  14341. SHcompact code.
  14342. '-no-expand'
  14343. Do not expand MOVI, PT, PTA or PTB instructions.
  14344. '-expand-pt32'
  14345. With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
  14346. '-h-tick-hex'
  14347. Support H'00 style hex constants in addition to 0x00 style.
  14348. 
  14349. File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent
  14350. 9.42.2 Syntax
  14351. -------------
  14352. * Menu:
  14353. * SH64-Chars:: Special Characters
  14354. * SH64-Regs:: Register Names
  14355. * SH64-Addressing:: Addressing Modes
  14356. 
  14357. File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax
  14358. 9.42.2.1 Special Characters
  14359. ...........................
  14360. '!' is the line comment character.
  14361. If a '#' appears as the first character of a line then the whole line
  14362. is treated as a comment, but in this case the line could also be a
  14363. logical line number directive (*note Comments::) or a preprocessor
  14364. control command (*note Preprocessing::).
  14365. You can use ';' instead of a newline to separate statements.
  14366. Since '$' has no special meaning, you may use it in symbol names.
  14367. 
  14368. File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax
  14369. 9.42.2.2 Register Names
  14370. .......................
  14371. You can use the predefined symbols 'r0' through 'r63' to refer to the
  14372. SH64 general registers, 'cr0' through 'cr63' for control registers,
  14373. 'tr0' through 'tr7' for target address registers, 'fr0' through 'fr63'
  14374. for single-precision floating point registers, 'dr0' through 'dr62'
  14375. (even numbered registers only) for double-precision floating point
  14376. registers, 'fv0' through 'fv60' (multiples of four only) for
  14377. single-precision floating point vectors, 'fp0' through 'fp62' (even
  14378. numbered registers only) for single-precision floating point pairs,
  14379. 'mtrx0' through 'mtrx48' (multiples of 16 only) for 4x4 matrices of
  14380. single-precision floating point registers, 'pc' for the program counter,
  14381. and 'fpscr' for the floating point status and control register.
  14382. You can also refer to the control registers by the mnemonics 'sr',
  14383. 'ssr', 'pssr', 'intevt', 'expevt', 'pexpevt', 'tra', 'spc', 'pspc',
  14384. 'resvec', 'vbr', 'tea', 'dcr', 'kcr0', 'kcr1', 'ctc', and 'usr'.
  14385. 
  14386. File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax
  14387. 9.42.2.3 Addressing Modes
  14388. .........................
  14389. SH64 operands consist of either a register or immediate value. The
  14390. immediate value can be a constant or label reference (or portion of a
  14391. label reference), as in this example:
  14392. movi 4,r2
  14393. pt function, tr4
  14394. movi (function >> 16) & 65535,r0
  14395. shori function & 65535, r0
  14396. ld.l r0,4,r0
  14397. Instruction label references can reference labels in either SHmedia
  14398. or SHcompact. To differentiate between the two, labels in SHmedia
  14399. sections will always have the least significant bit set (i.e. they will
  14400. be odd), which SHcompact labels will have the least significant bit
  14401. reset (i.e. they will be even). If you need to reference the actual
  14402. address of a label, you can use the 'datalabel' modifier, as in this
  14403. example:
  14404. .long function
  14405. .long datalabel function
  14406. In that example, the first longword may or may not have the least
  14407. significant bit set depending on whether the label is an SHmedia label
  14408. or an SHcompact label. The second longword will be the actual address
  14409. of the label, regardless of what type of label it is.
  14410. 
  14411. File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent
  14412. 9.42.3 SH64 Machine Directives
  14413. ------------------------------
  14414. In addition to the SH directives, the SH64 provides the following
  14415. directives:
  14416. '.mode [shmedia|shcompact]'
  14417. '.isa [shmedia|shcompact]'
  14418. Specify the ISA for the following instructions (the two directives
  14419. are equivalent). Note that programs such as 'objdump' rely on
  14420. symbolic labels to determine when such mode switches occur (by
  14421. checking the least significant bit of the label's address), so such
  14422. mode/isa changes should always be followed by a label (in practice,
  14423. this is true anyway). Note that you cannot use these directives if
  14424. you didn't specify an ISA on the command line.
  14425. '.abi [32|64]'
  14426. Specify the ABI for the following instructions. Note that you
  14427. cannot use this directive unless you specified an ABI on the
  14428. command line, and the ABIs specified must match.
  14429. 
  14430. File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent
  14431. 9.42.4 Opcodes
  14432. --------------
  14433. For detailed information on the SH64 machine instruction set, see
  14434. 'SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
  14435. 'as' implements all the standard SH64 opcodes. In addition, the
  14436. following pseudo-opcodes may be expanded into one or more alternate
  14437. opcodes:
  14438. 'movi'
  14439. If the value doesn't fit into a standard 'movi' opcode, 'as' will
  14440. replace the 'movi' with a sequence of 'movi' and 'shori' opcodes.
  14441. 'pt'
  14442. This expands to a sequence of 'movi' and 'shori' opcode, followed
  14443. by a 'ptrel' opcode, or to a 'pta' or 'ptb' opcode, depending on
  14444. the label referenced.
  14445. 
  14446. File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies
  14447. 9.43 SPARC Dependent Features
  14448. =============================
  14449. * Menu:
  14450. * Sparc-Opts:: Options
  14451. * Sparc-Aligned-Data:: Option to enforce aligned data
  14452. * Sparc-Syntax:: Syntax
  14453. * Sparc-Float:: Floating Point
  14454. * Sparc-Directives:: Sparc Machine Directives
  14455. 
  14456. File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
  14457. 9.43.1 Options
  14458. --------------
  14459. The SPARC chip family includes several successive versions, using the
  14460. same core instruction set, but including a few additional instructions
  14461. at each version. There are exceptions to this however. For details on
  14462. what instructions each variant supports, please see the chip's
  14463. architecture reference manual.
  14464. By default, 'as' assumes the core instruction set (SPARC v6), but
  14465. "bumps" the architecture level as needed: it switches to successively
  14466. higher architectures as it encounters instructions that only exist in
  14467. the higher levels.
  14468. If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past
  14469. sparclite by default, an option must be passed to enable the v9
  14470. instructions.
  14471. GAS treats sparclite as being compatible with v8, unless an
  14472. architecture is explicitly requested. SPARC v9 is always incompatible
  14473. with sparclite.
  14474. '-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite'
  14475. '-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm'
  14476. '-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m'
  14477. '-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima'
  14478. '-Asparcvis3 | -Asparcvis3r | -Asparc5'
  14479. Use one of the '-A' options to select one of the SPARC
  14480. architectures explicitly. If you select an architecture
  14481. explicitly, 'as' reports a fatal error if it encounters an
  14482. instruction or feature requiring an incompatible or higher level.
  14483. '-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and
  14484. '-Av8plusv' select a 32 bit environment.
  14485. '-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', '-Av9e', '-Av9v' and
  14486. '-Av9m' select a 64 bit environment and are not available unless
  14487. GAS is explicitly configured with 64 bit environment support.
  14488. '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with
  14489. UltraSPARC VIS 1.0 extensions.
  14490. '-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions,
  14491. as well as the instructions enabled by '-Av8plusa' and '-Av9a'.
  14492. '-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions,
  14493. as well as the instructions enabled by '-Av8plusb' and '-Av9b'.
  14494. '-Av8plusd' and '-Av9d' enable the floating point fused
  14495. multiply-add, VIS 3.0, and HPC extension instructions, as well as
  14496. the instructions enabled by '-Av8plusc' and '-Av9c'.
  14497. '-Av8pluse' and '-Av9e' enable the cryptographic instructions, as
  14498. well as the instructions enabled by '-Av8plusd' and '-Av9d'.
  14499. '-Av8plusv' and '-Av9v' enable floating point unfused multiply-add,
  14500. and integer multiply-add, as well as the instructions enabled by
  14501. '-Av8pluse' and '-Av9e'.
  14502. '-Av8plusm' and '-Av9m' enable the VIS 4.0, subtract extended,
  14503. xmpmul, xmontmul and xmontsqr instructions, as well as the
  14504. instructions enabled by '-Av8plusv' and '-Av9v'.
  14505. '-Asparc' specifies a v9 environment. It is equivalent to '-Av9'
  14506. if the word size is 64-bit, and '-Av8plus' otherwise.
  14507. '-Asparcvis' specifies a v9a environment. It is equivalent to
  14508. '-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise.
  14509. '-Asparcvis2' specifies a v9b environment. It is equivalent to
  14510. '-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise.
  14511. '-Asparcfmaf' specifies a v9b environment with the floating point
  14512. fused multiply-add instructions enabled.
  14513. '-Asparcima' specifies a v9b environment with the integer
  14514. multiply-add instructions enabled.
  14515. '-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC ,
  14516. and floating point fused multiply-add instructions enabled.
  14517. '-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC,
  14518. and floating point unfused multiply-add instructions enabled.
  14519. '-Asparc5' is equivalent to '-Av9m'.
  14520. '-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc'
  14521. '-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a'
  14522. '-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m'
  14523. '-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2'
  14524. '-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3'
  14525. '-xarch=sparcvis3r | -xarch=sparc5'
  14526. For compatibility with the SunOS v9 assembler. These options are
  14527. equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
  14528. -Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e,
  14529. -Av9v, -Av9m, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf,
  14530. -Asparcima, -Asparcvis3, and -Asparcvis3r, respectively.
  14531. '-bump'
  14532. Warn whenever it is necessary to switch to another level. If an
  14533. architecture level is explicitly requested, GAS will not issue
  14534. warnings until that level is reached, and will then bump the level
  14535. as required (except between incompatible levels).
  14536. '-32 | -64'
  14537. Select the word size, either 32 bits or 64 bits. These options are
  14538. only available with the ELF object file format, and require that
  14539. the necessary BFD support has been included.
  14540. '--dcti-couples-detect'
  14541. Warn if a DCTI (delayed control transfer instruction) couple is
  14542. found when generating code for a variant of the SPARC architecture
  14543. in which the execution of the couple is unpredictable, or very
  14544. slow. This is disabled by default.
  14545. 
  14546. File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent
  14547. 9.43.2 Enforcing aligned data
  14548. -----------------------------
  14549. SPARC GAS normally permits data to be misaligned. For example, it
  14550. permits the '.long' pseudo-op to be used on a byte boundary. However,
  14551. the native SunOS assemblers issue an error when they see misaligned
  14552. data.
  14553. You can use the '--enforce-aligned-data' option to make SPARC GAS
  14554. also issue an error about misaligned data, just as the SunOS assemblers
  14555. do.
  14556. The '--enforce-aligned-data' option is not the default because gcc
  14557. issues misaligned data pseudo-ops when it initializes certain packed
  14558. data structures (structures defined using the 'packed' attribute). You
  14559. may have to assemble with GAS in order to initialize packed data
  14560. structures in your own code.
  14561. 
  14562. File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
  14563. 9.43.3 Sparc Syntax
  14564. -------------------
  14565. The assembler syntax closely follows The Sparc Architecture Manual,
  14566. versions 8 and 9, as well as most extensions defined by Sun for their
  14567. UltraSPARC and Niagara line of processors.
  14568. * Menu:
  14569. * Sparc-Chars:: Special Characters
  14570. * Sparc-Regs:: Register Names
  14571. * Sparc-Constants:: Constant Names
  14572. * Sparc-Relocs:: Relocations
  14573. * Sparc-Size-Translations:: Size Translations
  14574. 
  14575. File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax
  14576. 9.43.3.1 Special Characters
  14577. ...........................
  14578. A '!' character appearing anywhere on a line indicates the start of a
  14579. comment that extends to the end of that line.
  14580. If a '#' appears as the first character of a line then the whole line
  14581. is treated as a comment, but in this case the line could also be a
  14582. logical line number directive (*note Comments::) or a preprocessor
  14583. control command (*note Preprocessing::).
  14584. ';' can be used instead of a newline to separate statements.
  14585. 
  14586. File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax
  14587. 9.43.3.2 Register Names
  14588. .......................
  14589. The Sparc integer register file is broken down into global, outgoing,
  14590. local, and incoming.
  14591. * The 8 global registers are referred to as '%gN'.
  14592. * The 8 outgoing registers are referred to as '%oN'.
  14593. * The 8 local registers are referred to as '%lN'.
  14594. * The 8 incoming registers are referred to as '%iN'.
  14595. * The frame pointer register '%i6' can be referenced using the alias
  14596. '%fp'.
  14597. * The stack pointer register '%o6' can be referenced using the alias
  14598. '%sp'.
  14599. Floating point registers are simply referred to as '%fN'. When
  14600. assembling for pre-V9, only 32 floating point registers are available.
  14601. For V9 and later there are 64, but there are restrictions when
  14602. referencing the upper 32 registers. They can only be accessed as double
  14603. or quad, and thus only even or quad numbered accesses are allowed. For
  14604. example, '%f34' is a legal floating point register, but '%f35' is not.
  14605. Floating point registers accessed as double can also be referred
  14606. using the '%dN' notation, where N is even. Similarly, floating point
  14607. registers accessed as quad can be referred using the '%qN' notation,
  14608. where N is a multiple of 4. For example, '%f4' can be denoted as both
  14609. '%d4' and '%q4'. On the other hand, '%f2' can be denoted as '%d2' but
  14610. not as '%q2'.
  14611. Certain V9 instructions allow access to ancillary state registers.
  14612. Most simply they can be referred to as '%asrN' where N can be from 16 to
  14613. 31. However, there are some aliases defined to reference ASR registers
  14614. defined for various UltraSPARC processors:
  14615. * The tick compare register is referred to as '%tick_cmpr'.
  14616. * The system tick register is referred to as '%stick'. An alias,
  14617. '%sys_tick', exists but is deprecated and should not be used by new
  14618. software.
  14619. * The system tick compare register is referred to as '%stick_cmpr'.
  14620. An alias, '%sys_tick_cmpr', exists but is deprecated and should not
  14621. be used by new software.
  14622. * The software interrupt register is referred to as '%softint'.
  14623. * The set software interrupt register is referred to as
  14624. '%set_softint'. The mnemonic '%softint_set' is provided as an
  14625. alias.
  14626. * The clear software interrupt register is referred to as
  14627. '%clear_softint'. The mnemonic '%softint_clear' is provided as an
  14628. alias.
  14629. * The performance instrumentation counters register is referred to as
  14630. '%pic'.
  14631. * The performance control register is referred to as '%pcr'.
  14632. * The graphics status register is referred to as '%gsr'.
  14633. * The V9 dispatch control register is referred to as '%dcr'.
  14634. Various V9 branch and conditional move instructions allow
  14635. specification of which set of integer condition codes to test. These
  14636. are referred to as '%xcc' and '%icc'.
  14637. Additionally, GAS supports the so-called "natural" condition codes;
  14638. these are referred to as '%ncc' and reference to '%icc' if the word size
  14639. is 32, '%xcc' if the word size is 64.
  14640. In V9, there are 4 sets of floating point condition codes which are
  14641. referred to as '%fccN'.
  14642. Several special privileged and non-privileged registers exist:
  14643. * The V9 address space identifier register is referred to as '%asi'.
  14644. * The V9 restorable windows register is referred to as '%canrestore'.
  14645. * The V9 savable windows register is referred to as '%cansave'.
  14646. * The V9 clean windows register is referred to as '%cleanwin'.
  14647. * The V9 current window pointer register is referred to as '%cwp'.
  14648. * The floating-point queue register is referred to as '%fq'.
  14649. * The V8 co-processor queue register is referred to as '%cq'.
  14650. * The floating point status register is referred to as '%fsr'.
  14651. * The other windows register is referred to as '%otherwin'.
  14652. * The V9 program counter register is referred to as '%pc'.
  14653. * The V9 next program counter register is referred to as '%npc'.
  14654. * The V9 processor interrupt level register is referred to as '%pil'.
  14655. * The V9 processor state register is referred to as '%pstate'.
  14656. * The trap base address register is referred to as '%tba'.
  14657. * The V9 tick register is referred to as '%tick'.
  14658. * The V9 trap level is referred to as '%tl'.
  14659. * The V9 trap program counter is referred to as '%tpc'.
  14660. * The V9 trap next program counter is referred to as '%tnpc'.
  14661. * The V9 trap state is referred to as '%tstate'.
  14662. * The V9 trap type is referred to as '%tt'.
  14663. * The V9 condition codes is referred to as '%ccr'.
  14664. * The V9 floating-point registers state is referred to as '%fprs'.
  14665. * The V9 version register is referred to as '%ver'.
  14666. * The V9 window state register is referred to as '%wstate'.
  14667. * The Y register is referred to as '%y'.
  14668. * The V8 window invalid mask register is referred to as '%wim'.
  14669. * The V8 processor state register is referred to as '%psr'.
  14670. * The V9 global register level register is referred to as '%gl'.
  14671. Several special register names exist for hypervisor mode code:
  14672. * The hyperprivileged processor state register is referred to as
  14673. '%hpstate'.
  14674. * The hyperprivileged trap state register is referred to as
  14675. '%htstate'.
  14676. * The hyperprivileged interrupt pending register is referred to as
  14677. '%hintp'.
  14678. * The hyperprivileged trap base address register is referred to as
  14679. '%htba'.
  14680. * The hyperprivileged implementation version register is referred to
  14681. as '%hver'.
  14682. * The hyperprivileged system tick offset register is referred to as
  14683. '%hstick_offset'. Note that there is no '%hstick' register, the
  14684. normal '%stick' is used.
  14685. * The hyperprivileged system tick enable register is referred to as
  14686. '%hstick_enable'.
  14687. * The hyperprivileged system tick compare register is referred to as
  14688. '%hstick_cmpr'.
  14689. 
  14690. File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax
  14691. 9.43.3.3 Constants
  14692. ..................
  14693. Several Sparc instructions take an immediate operand field for which
  14694. mnemonic names exist. Two such examples are 'membar' and 'prefetch'.
  14695. Another example are the set of V9 memory access instruction that allow
  14696. specification of an address space identifier.
  14697. The 'membar' instruction specifies a memory barrier that is the
  14698. defined by the operand which is a bitmask. The supported mask mnemonics
  14699. are:
  14700. * '#Sync' requests that all operations (including nonmemory reference
  14701. operations) appearing prior to the 'membar' must have been
  14702. performed and the effects of any exceptions become visible before
  14703. any instructions after the 'membar' may be initiated. This
  14704. corresponds to 'membar' cmask field bit 2.
  14705. * '#MemIssue' requests that all memory reference operations appearing
  14706. prior to the 'membar' must have been performed before any memory
  14707. operation after the 'membar' may be initiated. This corresponds to
  14708. 'membar' cmask field bit 1.
  14709. * '#Lookaside' requests that a store appearing prior to the 'membar'
  14710. must complete before any load following the 'membar' referencing
  14711. the same address can be initiated. This corresponds to 'membar'
  14712. cmask field bit 0.
  14713. * '#StoreStore' defines that the effects of all stores appearing
  14714. prior to the 'membar' instruction must be visible to all processors
  14715. before the effect of any stores following the 'membar'. Equivalent
  14716. to the deprecated 'stbar' instruction. This corresponds to
  14717. 'membar' mmask field bit 3.
  14718. * '#LoadStore' defines all loads appearing prior to the 'membar'
  14719. instruction must have been performed before the effect of any
  14720. stores following the 'membar' is visible to any other processor.
  14721. This corresponds to 'membar' mmask field bit 2.
  14722. * '#StoreLoad' defines that the effects of all stores appearing prior
  14723. to the 'membar' instruction must be visible to all processors
  14724. before loads following the 'membar' may be performed. This
  14725. corresponds to 'membar' mmask field bit 1.
  14726. * '#LoadLoad' defines that all loads appearing prior to the 'membar'
  14727. instruction must have been performed before any loads following the
  14728. 'membar' may be performed. This corresponds to 'membar' mmask
  14729. field bit 0.
  14730. These values can be ored together, for example:
  14731. membar #Sync
  14732. membar #StoreLoad | #LoadLoad
  14733. membar #StoreLoad | #StoreStore
  14734. The 'prefetch' and 'prefetcha' instructions take a prefetch function
  14735. code. The following prefetch function code constant mnemonics are
  14736. available:
  14737. * '#n_reads' requests a prefetch for several reads, and corresponds
  14738. to a prefetch function code of 0.
  14739. '#one_read' requests a prefetch for one read, and corresponds to a
  14740. prefetch function code of 1.
  14741. '#n_writes' requests a prefetch for several writes (and possibly
  14742. reads), and corresponds to a prefetch function code of 2.
  14743. '#one_write' requests a prefetch for one write, and corresponds to
  14744. a prefetch function code of 3.
  14745. '#page' requests a prefetch page, and corresponds to a prefetch
  14746. function code of 4.
  14747. '#invalidate' requests a prefetch invalidate, and corresponds to a
  14748. prefetch function code of 16.
  14749. '#unified' requests a prefetch to the nearest unified cache, and
  14750. corresponds to a prefetch function code of 17.
  14751. '#n_reads_strong' requests a strong prefetch for several reads, and
  14752. corresponds to a prefetch function code of 20.
  14753. '#one_read_strong' requests a strong prefetch for one read, and
  14754. corresponds to a prefetch function code of 21.
  14755. '#n_writes_strong' requests a strong prefetch for several writes,
  14756. and corresponds to a prefetch function code of 22.
  14757. '#one_write_strong' requests a strong prefetch for one write, and
  14758. corresponds to a prefetch function code of 23.
  14759. Onle one prefetch code may be specified. Here are some examples:
  14760. prefetch [%l0 + %l2], #one_read
  14761. prefetch [%g2 + 8], #n_writes
  14762. prefetcha [%g1] 0x8, #unified
  14763. prefetcha [%o0 + 0x10] %asi, #n_reads
  14764. The actual behavior of a given prefetch function code is processor
  14765. specific. If a processor does not implement a given prefetch
  14766. function code, it will treat the prefetch instruction as a nop.
  14767. For instructions that accept an immediate address space identifier,
  14768. 'as' provides many mnemonics corresponding to V9 defined as well as
  14769. UltraSPARC and Niagara extended values. For example, '#ASI_P' and
  14770. '#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific
  14771. manuals for details.
  14772. 
  14773. File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax
  14774. 9.43.3.4 Relocations
  14775. ....................
  14776. ELF relocations are available as defined in the 32-bit and 64-bit Sparc
  14777. ELF specifications.
  14778. 'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained
  14779. using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and
  14780. 'R_SPARC_LOX10' is obtained using '%lox'. For example:
  14781. sethi %hi(symbol), %g1
  14782. or %g1, %lo(symbol), %g1
  14783. sethi %hix(symbol), %g1
  14784. xor %g1, %lox(symbol), %g1
  14785. These "high" mnemonics extract bits 31:10 of their operand, and the
  14786. "low" mnemonics extract bits 9:0 of their operand.
  14787. V9 code model relocations can be requested as follows:
  14788. * 'R_SPARC_HH22' is requested using '%hh'. It can also be generated
  14789. using '%uhi'.
  14790. * 'R_SPARC_HM10' is requested using '%hm'. It can also be generated
  14791. using '%ulo'.
  14792. * 'R_SPARC_LM22' is requested using '%lm'.
  14793. * 'R_SPARC_H44' is requested using '%h44'.
  14794. * 'R_SPARC_M44' is requested using '%m44'.
  14795. * 'R_SPARC_L44' is requested using '%l44' or '%l34'.
  14796. * 'R_SPARC_H34' is requested using '%h34'.
  14797. The '%l34' generates a 'R_SPARC_L44' relocation because it calculates
  14798. the necessary value, and therefore no explicit 'R_SPARC_L34' relocation
  14799. needed to be created for this purpose.
  14800. The '%h34' and '%l34' relocations are used for the abs34 code model.
  14801. Here is an example abs34 address generation sequence:
  14802. sethi %h34(symbol), %g1
  14803. sllx %g1, 2, %g1
  14804. or %g1, %l34(symbol), %g1
  14805. The PC relative relocation 'R_SPARC_PC22' can be obtained by
  14806. enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10'
  14807. relocation can be obtained using '%pc10'. These are mostly used when
  14808. assembling PIC code. For example, the standard PIC sequence on Sparc to
  14809. get the base of the global offset table, PC relative, into a register,
  14810. can be performed as:
  14811. sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
  14812. add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
  14813. Several relocations exist to allow the link editor to potentially
  14814. optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation
  14815. can obtained by enclosing an operand inside of '%gdop_hix22'. The
  14816. 'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an
  14817. operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be
  14818. obtained by enclosing an operand inside of '%gdop'. For example,
  14819. assuming the GOT base is in register '%l7':
  14820. sethi %gdop_hix22(symbol), %l1
  14821. xor %l1, %gdop_lox10(symbol), %l1
  14822. ld [%l7 + %l1], %l2, %gdop(symbol)
  14823. There are many relocations that can be requested for access to thread
  14824. local storage variables. All of the Sparc TLS mnemonics are supported:
  14825. * 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'.
  14826. * 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'.
  14827. * 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'.
  14828. * 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'.
  14829. * 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'.
  14830. * 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'.
  14831. * 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'.
  14832. * 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'.
  14833. * 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'.
  14834. * 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'.
  14835. * 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'.
  14836. * 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'.
  14837. * 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'.
  14838. * 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'.
  14839. * 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'.
  14840. * 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'.
  14841. * 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'.
  14842. * 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'.
  14843. Here are some example TLS model sequences.
  14844. First, General Dynamic:
  14845. sethi %tgd_hi22(symbol), %l1
  14846. add %l1, %tgd_lo10(symbol), %l1
  14847. add %l7, %l1, %o0, %tgd_add(symbol)
  14848. call __tls_get_addr, %tgd_call(symbol)
  14849. nop
  14850. Local Dynamic:
  14851. sethi %tldm_hi22(symbol), %l1
  14852. add %l1, %tldm_lo10(symbol), %l1
  14853. add %l7, %l1, %o0, %tldm_add(symbol)
  14854. call __tls_get_addr, %tldm_call(symbol)
  14855. nop
  14856. sethi %tldo_hix22(symbol), %l1
  14857. xor %l1, %tldo_lox10(symbol), %l1
  14858. add %o0, %l1, %l1, %tldo_add(symbol)
  14859. Initial Exec:
  14860. sethi %tie_hi22(symbol), %l1
  14861. add %l1, %tie_lo10(symbol), %l1
  14862. ld [%l7 + %l1], %o0, %tie_ld(symbol)
  14863. add %g7, %o0, %o0, %tie_add(symbol)
  14864. sethi %tie_hi22(symbol), %l1
  14865. add %l1, %tie_lo10(symbol), %l1
  14866. ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
  14867. add %g7, %o0, %o0, %tie_add(symbol)
  14868. And finally, Local Exec:
  14869. sethi %tle_hix22(symbol), %l1
  14870. add %l1, %tle_lox10(symbol), %l1
  14871. add %g7, %l1, %l1
  14872. When assembling for 64-bit, and a secondary constant addend is
  14873. specified in an address expression that would normally generate an
  14874. 'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10'
  14875. instead.
  14876. 
  14877. File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax
  14878. 9.43.3.5 Size Translations
  14879. ..........................
  14880. Often it is desirable to write code in an operand size agnostic manner.
  14881. 'as' provides support for this via operand size opcode translations.
  14882. Translations are supported for loads, stores, shifts, compare-and-swap
  14883. atomics, and the 'clr' synthetic instruction.
  14884. If generating 32-bit code, 'as' will generate the 32-bit opcode.
  14885. Whereas if 64-bit code is being generated, the 64-bit opcode will be
  14886. emitted. For example 'ldn' will be transformed into 'ld' for 32-bit
  14887. code and 'ldx' for 64-bit code.
  14888. Here is an example meant to demonstrate all the supported opcode
  14889. translations:
  14890. ldn [%o0], %o1
  14891. ldna [%o0] %asi, %o2
  14892. stn %o1, [%o0]
  14893. stna %o2, [%o0] %asi
  14894. slln %o3, 3, %o3
  14895. srln %o4, 8, %o4
  14896. sran %o5, 12, %o5
  14897. casn [%o0], %o1, %o2
  14898. casna [%o0] %asi, %o1, %o2
  14899. clrn %g1
  14900. In 32-bit mode 'as' will emit:
  14901. ld [%o0], %o1
  14902. lda [%o0] %asi, %o2
  14903. st %o1, [%o0]
  14904. sta %o2, [%o0] %asi
  14905. sll %o3, 3, %o3
  14906. srl %o4, 8, %o4
  14907. sra %o5, 12, %o5
  14908. cas [%o0], %o1, %o2
  14909. casa [%o0] %asi, %o1, %o2
  14910. clr %g1
  14911. And in 64-bit mode 'as' will emit:
  14912. ldx [%o0], %o1
  14913. ldxa [%o0] %asi, %o2
  14914. stx %o1, [%o0]
  14915. stxa %o2, [%o0] %asi
  14916. sllx %o3, 3, %o3
  14917. srlx %o4, 8, %o4
  14918. srax %o5, 12, %o5
  14919. casx [%o0], %o1, %o2
  14920. casxa [%o0] %asi, %o1, %o2
  14921. clrx %g1
  14922. Finally, the '.nword' translating directive is supported as well. It
  14923. is documented in the section on Sparc machine directives.
  14924. 
  14925. File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent
  14926. 9.43.4 Floating Point
  14927. ---------------------
  14928. The Sparc uses IEEE floating-point numbers.
  14929. 
  14930. File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
  14931. 9.43.5 Sparc Machine Directives
  14932. -------------------------------
  14933. The Sparc version of 'as' supports the following additional machine
  14934. directives:
  14935. '.align'
  14936. This must be followed by the desired alignment in bytes.
  14937. '.common'
  14938. This must be followed by a symbol name, a positive number, and
  14939. '"bss"'. This behaves somewhat like '.comm', but the syntax is
  14940. different.
  14941. '.half'
  14942. This is functionally identical to '.short'.
  14943. '.nword'
  14944. On the Sparc, the '.nword' directive produces native word sized
  14945. value, ie. if assembling with -32 it is equivalent to '.word', if
  14946. assembling with -64 it is equivalent to '.xword'.
  14947. '.proc'
  14948. This directive is ignored. Any text following it on the same line
  14949. is also ignored.
  14950. '.register'
  14951. This directive declares use of a global application or system
  14952. register. It must be followed by a register name %g2, %g3, %g6 or
  14953. %g7, comma and the symbol name for that register. If symbol name
  14954. is '#scratch', it is a scratch register, if it is '#ignore', it
  14955. just suppresses any errors about using undeclared global register,
  14956. but does not emit any information about it into the object file.
  14957. This can be useful e.g. if you save the register before use and
  14958. restore it after.
  14959. '.reserve'
  14960. This must be followed by a symbol name, a positive number, and
  14961. '"bss"'. This behaves somewhat like '.lcomm', but the syntax is
  14962. different.
  14963. '.seg'
  14964. This must be followed by '"text"', '"data"', or '"data1"'. It
  14965. behaves like '.text', '.data', or '.data 1'.
  14966. '.skip'
  14967. This is functionally identical to the '.space' directive.
  14968. '.word'
  14969. On the Sparc, the '.word' directive produces 32 bit values, instead
  14970. of the 16 bit values it produces on many other machines.
  14971. '.xword'
  14972. On the Sparc V9 processor, the '.xword' directive produces 64 bit
  14973. values.
  14974. 
  14975. File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
  14976. 9.44 TIC54X Dependent Features
  14977. ==============================
  14978. * Menu:
  14979. * TIC54X-Opts:: Command-line Options
  14980. * TIC54X-Block:: Blocking
  14981. * TIC54X-Env:: Environment Settings
  14982. * TIC54X-Constants:: Constants Syntax
  14983. * TIC54X-Subsyms:: String Substitution
  14984. * TIC54X-Locals:: Local Label Syntax
  14985. * TIC54X-Builtins:: Builtin Assembler Math Functions
  14986. * TIC54X-Ext:: Extended Addressing Support
  14987. * TIC54X-Directives:: Directives
  14988. * TIC54X-Macros:: Macro Features
  14989. * TIC54X-MMRegs:: Memory-mapped Registers
  14990. * TIC54X-Syntax:: Syntax
  14991. 
  14992. File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent
  14993. 9.44.1 Options
  14994. --------------
  14995. The TMS320C54X version of 'as' has a few machine-dependent options.
  14996. You can use the '-mfar-mode' option to enable extended addressing
  14997. mode. All addresses will be assumed to be > 16 bits, and the
  14998. appropriate relocation types will be used. This option is equivalent to
  14999. using the '.far_mode' directive in the assembly code. If you do not use
  15000. the '-mfar-mode' option, all references will be assumed to be 16 bits.
  15001. This option may be abbreviated to '-mf'.
  15002. You can use the '-mcpu' option to specify a particular CPU. This
  15003. option is equivalent to using the '.version' directive in the assembly
  15004. code. For recognized CPU codes, see *Note '.version':
  15005. TIC54X-Directives. The default CPU version is '542'.
  15006. You can use the '-merrors-to-file' option to redirect error output to
  15007. a file (this provided for those deficient environments which don't
  15008. provide adequate output redirection). This option may be abbreviated to
  15009. '-me'.
  15010. 
  15011. File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent
  15012. 9.44.2 Blocking
  15013. ---------------
  15014. A blocked section or memory block is guaranteed not to cross the
  15015. blocking boundary (usually a page, or 128 words) if it is smaller than
  15016. the blocking size, or to start on a page boundary if it is larger than
  15017. the blocking size.
  15018. 
  15019. File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent
  15020. 9.44.3 Environment Settings
  15021. ---------------------------
  15022. 'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added
  15023. to the list of directories normally searched for source and include
  15024. files. 'C54XDSP_DIR' will override 'A_DIR'.
  15025. 
  15026. File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent
  15027. 9.44.4 Constants Syntax
  15028. -----------------------
  15029. The TIC54X version of 'as' allows the following additional constant
  15030. formats, using a suffix to indicate the radix:
  15031. Binary 000000B, 011000b
  15032. Octal 10Q, 224q
  15033. Hexadecimal 45h, 0FH
  15034. 
  15035. File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent
  15036. 9.44.5 String Substitution
  15037. --------------------------
  15038. A subset of allowable symbols (which we'll call subsyms) may be assigned
  15039. arbitrary string values. This is roughly equivalent to C preprocessor
  15040. #define macros. When 'as' encounters one of these symbols, the symbol
  15041. is replaced in the input stream by its string value. Subsym names
  15042. *must* begin with a letter.
  15043. Subsyms may be defined using the '.asg' and '.eval' directives (*Note
  15044. '.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives.
  15045. Expansion is recursive until a previously encountered symbol is seen,
  15046. at which point substitution stops.
  15047. In this example, x is replaced with SYM2; SYM2 is replaced with SYM1,
  15048. and SYM1 is replaced with x. At this point, x has already been
  15049. encountered and the substitution stops.
  15050. .asg "x",SYM1
  15051. .asg "SYM1",SYM2
  15052. .asg "SYM2",x
  15053. add x,a ; final code assembled is "add x, a"
  15054. Macro parameters are converted to subsyms; a side effect of this is
  15055. the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms
  15056. defined within a macro will have global scope, unless the '.var'
  15057. directive is used to identify the subsym as a local macro variable *note
  15058. '.var': TIC54X-Directives.
  15059. Substitution may be forced in situations where replacement might be
  15060. ambiguous by placing colons on either side of the subsym. The following
  15061. code:
  15062. .eval "10",x
  15063. LAB:X: add #x, a
  15064. When assembled becomes:
  15065. LAB10 add #10, a
  15066. Smaller parts of the string assigned to a subsym may be accessed with
  15067. the following syntax:
  15068. ':SYMBOL(CHAR_INDEX):'
  15069. Evaluates to a single-character string, the character at
  15070. CHAR_INDEX.
  15071. ':SYMBOL(START,LENGTH):'
  15072. Evaluates to a substring of SYMBOL beginning at START with length
  15073. LENGTH.
  15074. 
  15075. File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent
  15076. 9.44.6 Local Labels
  15077. -------------------
  15078. Local labels may be defined in two ways:
  15079. * $N, where N is a decimal number between 0 and 9
  15080. * LABEL?, where LABEL is any legal symbol name.
  15081. Local labels thus defined may be redefined or automatically
  15082. generated. The scope of a local label is based on when it may be
  15083. undefined or reset. This happens when one of the following situations
  15084. is encountered:
  15085. * .newblock directive *note '.newblock': TIC54X-Directives.
  15086. * The current section is changed (.sect, .text, or .data)
  15087. * Entering or leaving an included file
  15088. * The macro scope where the label was defined is exited
  15089. 
  15090. File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent
  15091. 9.44.7 Math Builtins
  15092. --------------------
  15093. The following built-in functions may be used to generate a
  15094. floating-point value. All return a floating-point value except '$cvi',
  15095. '$int', and '$sgn', which return an integer value.
  15096. '$acos(EXPR)'
  15097. Returns the floating point arccosine of EXPR.
  15098. '$asin(EXPR)'
  15099. Returns the floating point arcsine of EXPR.
  15100. '$atan(EXPR)'
  15101. Returns the floating point arctangent of EXPR.
  15102. '$atan2(EXPR1,EXPR2)'
  15103. Returns the floating point arctangent of EXPR1 / EXPR2.
  15104. '$ceil(EXPR)'
  15105. Returns the smallest integer not less than EXPR as floating point.
  15106. '$cosh(EXPR)'
  15107. Returns the floating point hyperbolic cosine of EXPR.
  15108. '$cos(EXPR)'
  15109. Returns the floating point cosine of EXPR.
  15110. '$cvf(EXPR)'
  15111. Returns the integer value EXPR converted to floating-point.
  15112. '$cvi(EXPR)'
  15113. Returns the floating point value EXPR converted to integer.
  15114. '$exp(EXPR)'
  15115. Returns the floating point value e ^ EXPR.
  15116. '$fabs(EXPR)'
  15117. Returns the floating point absolute value of EXPR.
  15118. '$floor(EXPR)'
  15119. Returns the largest integer that is not greater than EXPR as
  15120. floating point.
  15121. '$fmod(EXPR1,EXPR2)'
  15122. Returns the floating point remainder of EXPR1 / EXPR2.
  15123. '$int(EXPR)'
  15124. Returns 1 if EXPR evaluates to an integer, zero otherwise.
  15125. '$ldexp(EXPR1,EXPR2)'
  15126. Returns the floating point value EXPR1 * 2 ^ EXPR2.
  15127. '$log10(EXPR)'
  15128. Returns the base 10 logarithm of EXPR.
  15129. '$log(EXPR)'
  15130. Returns the natural logarithm of EXPR.
  15131. '$max(EXPR1,EXPR2)'
  15132. Returns the floating point maximum of EXPR1 and EXPR2.
  15133. '$min(EXPR1,EXPR2)'
  15134. Returns the floating point minimum of EXPR1 and EXPR2.
  15135. '$pow(EXPR1,EXPR2)'
  15136. Returns the floating point value EXPR1 ^ EXPR2.
  15137. '$round(EXPR)'
  15138. Returns the nearest integer to EXPR as a floating point number.
  15139. '$sgn(EXPR)'
  15140. Returns -1, 0, or 1 based on the sign of EXPR.
  15141. '$sin(EXPR)'
  15142. Returns the floating point sine of EXPR.
  15143. '$sinh(EXPR)'
  15144. Returns the floating point hyperbolic sine of EXPR.
  15145. '$sqrt(EXPR)'
  15146. Returns the floating point square root of EXPR.
  15147. '$tan(EXPR)'
  15148. Returns the floating point tangent of EXPR.
  15149. '$tanh(EXPR)'
  15150. Returns the floating point hyperbolic tangent of EXPR.
  15151. '$trunc(EXPR)'
  15152. Returns the integer value of EXPR truncated towards zero as
  15153. floating point.
  15154. 
  15155. File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent
  15156. 9.44.8 Extended Addressing
  15157. --------------------------
  15158. The 'LDX' pseudo-op is provided for loading the extended addressing bits
  15159. of a label or address. For example, if an address '_label' resides in
  15160. extended program memory, the value of '_label' may be loaded as follows:
  15161. ldx #_label,16,a ; loads extended bits of _label
  15162. or #_label,a ; loads lower 16 bits of _label
  15163. bacc a ; full address is in accumulator A
  15164. 
  15165. File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent
  15166. 9.44.9 Directives
  15167. -----------------
  15168. '.align [SIZE]'
  15169. '.even'
  15170. Align the section program counter on the next boundary, based on
  15171. SIZE. SIZE may be any power of 2. '.even' is equivalent to
  15172. '.align' with a SIZE of 2.
  15173. '1'
  15174. Align SPC to word boundary
  15175. '2'
  15176. Align SPC to longword boundary (same as .even)
  15177. '128'
  15178. Align SPC to page boundary
  15179. '.asg STRING, NAME'
  15180. Assign NAME the string STRING. String replacement is performed on
  15181. STRING before assignment.
  15182. '.eval STRING, NAME'
  15183. Evaluate the contents of string STRING and assign the result as a
  15184. string to the subsym NAME. String replacement is performed on
  15185. STRING before assignment.
  15186. '.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
  15187. Reserve space for SYMBOL in the .bss section. SIZE is in words.
  15188. If present, BLOCKING_FLAG indicates the allocated space should be
  15189. aligned on a page boundary if it would otherwise cross a page
  15190. boundary. If present, ALIGNMENT_FLAG causes the assembler to
  15191. allocate SIZE on a long word boundary.
  15192. '.byte VALUE [,...,VALUE_N]'
  15193. '.ubyte VALUE [,...,VALUE_N]'
  15194. '.char VALUE [,...,VALUE_N]'
  15195. '.uchar VALUE [,...,VALUE_N]'
  15196. Place one or more bytes into consecutive words of the current
  15197. section. The upper 8 bits of each word is zero-filled. If a label
  15198. is used, it points to the word allocated for the first byte
  15199. encountered.
  15200. '.clink ["SECTION_NAME"]'
  15201. Set STYP_CLINK flag for this section, which indicates to the linker
  15202. that if no symbols from this section are referenced, the section
  15203. should not be included in the link. If SECTION_NAME is omitted,
  15204. the current section is used.
  15205. '.c_mode'
  15206. TBD.
  15207. '.copy "FILENAME" | FILENAME'
  15208. '.include "FILENAME" | FILENAME'
  15209. Read source statements from FILENAME. The normal include search
  15210. path is used. Normally .copy will cause statements from the
  15211. included file to be printed in the assembly listing and .include
  15212. will not, but this distinction is not currently implemented.
  15213. '.data'
  15214. Begin assembling code into the .data section.
  15215. '.double VALUE [,...,VALUE_N]'
  15216. '.ldouble VALUE [,...,VALUE_N]'
  15217. '.float VALUE [,...,VALUE_N]'
  15218. '.xfloat VALUE [,...,VALUE_N]'
  15219. Place an IEEE single-precision floating-point representation of one
  15220. or more floating-point values into the current section. All but
  15221. '.xfloat' align the result on a longword boundary. Values are
  15222. stored most-significant word first.
  15223. '.drlist'
  15224. '.drnolist'
  15225. Control printing of directives to the listing file. Ignored.
  15226. '.emsg STRING'
  15227. '.mmsg STRING'
  15228. '.wmsg STRING'
  15229. Emit a user-defined error, message, or warning, respectively.
  15230. '.far_mode'
  15231. Use extended addressing when assembling statements. This should
  15232. appear only once per file, and is equivalent to the -mfar-mode
  15233. option *note '-mfar-mode': TIC54X-Opts.
  15234. '.fclist'
  15235. '.fcnolist'
  15236. Control printing of false conditional blocks to the listing file.
  15237. '.field VALUE [,SIZE]'
  15238. Initialize a bitfield of SIZE bits in the current section. If
  15239. VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16
  15240. bits. If VALUE does not fit into SIZE bits, the value will be
  15241. truncated. Successive '.field' directives will pack starting at
  15242. the current word, filling the most significant bits first, and
  15243. aligning to the start of the next word if the field size does not
  15244. fit into the space remaining in the current word. A '.align'
  15245. directive with an operand of 1 will force the next '.field'
  15246. directive to begin packing into a new word. If a label is used, it
  15247. points to the word that contains the specified field.
  15248. '.global SYMBOL [,...,SYMBOL_N]'
  15249. '.def SYMBOL [,...,SYMBOL_N]'
  15250. '.ref SYMBOL [,...,SYMBOL_N]'
  15251. '.def' nominally identifies a symbol defined in the current file
  15252. and available to other files. '.ref' identifies a symbol used in
  15253. the current file but defined elsewhere. Both map to the standard
  15254. '.global' directive.
  15255. '.half VALUE [,...,VALUE_N]'
  15256. '.uhalf VALUE [,...,VALUE_N]'
  15257. '.short VALUE [,...,VALUE_N]'
  15258. '.ushort VALUE [,...,VALUE_N]'
  15259. '.int VALUE [,...,VALUE_N]'
  15260. '.uint VALUE [,...,VALUE_N]'
  15261. '.word VALUE [,...,VALUE_N]'
  15262. '.uword VALUE [,...,VALUE_N]'
  15263. Place one or more values into consecutive words of the current
  15264. section. If a label is used, it points to the word allocated for
  15265. the first value encountered.
  15266. '.label SYMBOL'
  15267. Define a special SYMBOL to refer to the load time address of the
  15268. current section program counter.
  15269. '.length'
  15270. '.width'
  15271. Set the page length and width of the output listing file. Ignored.
  15272. '.list'
  15273. '.nolist'
  15274. Control whether the source listing is printed. Ignored.
  15275. '.long VALUE [,...,VALUE_N]'
  15276. '.ulong VALUE [,...,VALUE_N]'
  15277. '.xlong VALUE [,...,VALUE_N]'
  15278. Place one or more 32-bit values into consecutive words in the
  15279. current section. The most significant word is stored first.
  15280. '.long' and '.ulong' align the result on a longword boundary;
  15281. 'xlong' does not.
  15282. '.loop [COUNT]'
  15283. '.break [CONDITION]'
  15284. '.endloop'
  15285. Repeatedly assemble a block of code. '.loop' begins the block, and
  15286. '.endloop' marks its termination. COUNT defaults to 1024, and
  15287. indicates the number of times the block should be repeated.
  15288. '.break' terminates the loop so that assembly begins after the
  15289. '.endloop' directive. The optional CONDITION will cause the loop
  15290. to terminate only if it evaluates to zero.
  15291. 'MACRO_NAME .macro [PARAM1][,...PARAM_N]'
  15292. '[.mexit]'
  15293. '.endm'
  15294. See the section on macros for more explanation (*Note
  15295. TIC54X-Macros::.
  15296. '.mlib "FILENAME" | FILENAME'
  15297. Load the macro library FILENAME. FILENAME must be an archived
  15298. library (BFD ar-compatible) of text files, expected to contain only
  15299. macro definitions. The standard include search path is used.
  15300. '.mlist'
  15301. '.mnolist'
  15302. Control whether to include macro and loop block expansions in the
  15303. listing output. Ignored.
  15304. '.mmregs'
  15305. Define global symbolic names for the 'c54x registers. Supposedly
  15306. equivalent to executing '.set' directives for each register with
  15307. its memory-mapped value, but in reality is provided only for
  15308. compatibility and does nothing.
  15309. '.newblock'
  15310. This directive resets any TIC54X local labels currently defined.
  15311. Normal 'as' local labels are unaffected.
  15312. '.option OPTION_LIST'
  15313. Set listing options. Ignored.
  15314. '.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
  15315. Designate SECTION_NAME for blocking. Blocking guarantees that a
  15316. section will start on a page boundary (128 words) if it would
  15317. otherwise cross a page boundary. Only initialized sections may be
  15318. designated with this directive. See also *Note TIC54X-Block::.
  15319. '.sect "SECTION_NAME"'
  15320. Define a named initialized section and make it the current section.
  15321. 'SYMBOL .set "VALUE"'
  15322. 'SYMBOL .equ "VALUE"'
  15323. Equate a constant VALUE to a SYMBOL, which is placed in the symbol
  15324. table. SYMBOL may not be previously defined.
  15325. '.space SIZE_IN_BITS'
  15326. '.bes SIZE_IN_BITS'
  15327. Reserve the given number of bits in the current section and
  15328. zero-fill them. If a label is used with '.space', it points to the
  15329. *first* word reserved. With '.bes', the label points to the *last*
  15330. word reserved.
  15331. '.sslist'
  15332. '.ssnolist'
  15333. Controls the inclusion of subsym replacement in the listing output.
  15334. Ignored.
  15335. '.string "STRING" [,...,"STRING_N"]'
  15336. '.pstring "STRING" [,...,"STRING_N"]'
  15337. Place 8-bit characters from STRING into the current section.
  15338. '.string' zero-fills the upper 8 bits of each word, while
  15339. '.pstring' puts two characters into each word, filling the
  15340. most-significant bits first. Unused space is zero-filled. If a
  15341. label is used, it points to the first word initialized.
  15342. '[STAG] .struct [OFFSET]'
  15343. '[NAME_1] element [COUNT_1]'
  15344. '[NAME_2] element [COUNT_2]'
  15345. '[TNAME] .tag STAGX [TCOUNT]'
  15346. '...'
  15347. '[NAME_N] element [COUNT_N]'
  15348. '[SSIZE] .endstruct'
  15349. 'LABEL .tag [STAG]'
  15350. Assign symbolic offsets to the elements of a structure. STAG
  15351. defines a symbol to use to reference the structure. OFFSET
  15352. indicates a starting value to use for the first element
  15353. encountered; otherwise it defaults to zero. Each element can have
  15354. a named offset, NAME, which is a symbol assigned the value of the
  15355. element's offset into the structure. If STAG is missing, these
  15356. become global symbols. COUNT adjusts the offset that many times,
  15357. as if 'element' were an array. 'element' may be one of '.byte',
  15358. '.word', '.long', '.float', or any equivalent of those, and the
  15359. structure offset is adjusted accordingly. '.field' and '.string'
  15360. are also allowed; the size of '.field' is one bit, and '.string' is
  15361. considered to be one word in size. Only element descriptors,
  15362. structure/union tags, '.align' and conditional assembly directives
  15363. are allowed within '.struct'/'.endstruct'. '.align' aligns member
  15364. offsets to word boundaries only. SSIZE, if provided, will always
  15365. be assigned the size of the structure.
  15366. The '.tag' directive, in addition to being used to define a
  15367. structure/union element within a structure, may be used to apply a
  15368. structure to a symbol. Once applied to LABEL, the individual
  15369. structure elements may be applied to LABEL to produce the desired
  15370. offsets using LABEL as the structure base.
  15371. '.tab'
  15372. Set the tab size in the output listing. Ignored.
  15373. '[UTAG] .union'
  15374. '[NAME_1] element [COUNT_1]'
  15375. '[NAME_2] element [COUNT_2]'
  15376. '[TNAME] .tag UTAGX[,TCOUNT]'
  15377. '...'
  15378. '[NAME_N] element [COUNT_N]'
  15379. '[USIZE] .endstruct'
  15380. 'LABEL .tag [UTAG]'
  15381. Similar to '.struct', but the offset after each element is reset to
  15382. zero, and the USIZE is set to the maximum of all defined elements.
  15383. Starting offset for the union is always zero.
  15384. '[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
  15385. Reserve space for variables in a named, uninitialized section
  15386. (similar to .bss). '.usect' allows definitions sections
  15387. independent of .bss. SYMBOL points to the first location reserved
  15388. by this allocation. The symbol may be used as a variable name.
  15389. SIZE is the allocated size in words. BLOCKING_FLAG indicates
  15390. whether to block this section on a page boundary (128 words) (*note
  15391. TIC54X-Block::). ALIGNMENT FLAG indicates whether the section
  15392. should be longword-aligned.
  15393. '.var SYM[,..., SYM_N]'
  15394. Define a subsym to be a local variable within a macro. See *Note
  15395. TIC54X-Macros::.
  15396. '.version VERSION'
  15397. Set which processor to build instructions for. Though the
  15398. following values are accepted, the op is ignored.
  15399. '541'
  15400. '542'
  15401. '543'
  15402. '545'
  15403. '545LP'
  15404. '546LP'
  15405. '548'
  15406. '549'
  15407. 
  15408. File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent
  15409. 9.44.10 Macros
  15410. --------------
  15411. Macros do not require explicit dereferencing of arguments (i.e., \ARG).
  15412. During macro expansion, the macro parameters are converted to
  15413. subsyms. If the number of arguments passed the macro invocation exceeds
  15414. the number of parameters defined, the last parameter is assigned the
  15415. string equivalent of all remaining arguments. If fewer arguments are
  15416. given than parameters, the missing parameters are assigned empty
  15417. strings. To include a comma in an argument, you must enclose the
  15418. argument in quotes.
  15419. The following built-in subsym functions allow examination of the
  15420. string value of subsyms (or ordinary strings). The arguments are
  15421. strings unless otherwise indicated (subsyms passed as args will be
  15422. replaced by the strings they represent).
  15423. '$symlen(STR)'
  15424. Returns the length of STR.
  15425. '$symcmp(STR1,STR2)'
  15426. Returns 0 if STR1 == STR2, non-zero otherwise.
  15427. '$firstch(STR,CH)'
  15428. Returns index of the first occurrence of character constant CH in
  15429. STR.
  15430. '$lastch(STR,CH)'
  15431. Returns index of the last occurrence of character constant CH in
  15432. STR.
  15433. '$isdefed(SYMBOL)'
  15434. Returns zero if the symbol SYMBOL is not in the symbol table,
  15435. non-zero otherwise.
  15436. '$ismember(SYMBOL,LIST)'
  15437. Assign the first member of comma-separated string LIST to SYMBOL;
  15438. LIST is reassigned the remainder of the list. Returns zero if LIST
  15439. is a null string. Both arguments must be subsyms.
  15440. '$iscons(EXPR)'
  15441. Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4
  15442. if a character, 5 if decimal, and zero if not an integer.
  15443. '$isname(NAME)'
  15444. Returns 1 if NAME is a valid symbol name, zero otherwise.
  15445. '$isreg(REG)'
  15446. Returns 1 if REG is a valid predefined register name (AR0-AR7
  15447. only).
  15448. '$structsz(STAG)'
  15449. Returns the size of the structure or union represented by STAG.
  15450. '$structacc(STAG)'
  15451. Returns the reference point of the structure or union represented
  15452. by STAG. Always returns zero.
  15453. 
  15454. File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent
  15455. 9.44.11 Memory-mapped Registers
  15456. -------------------------------
  15457. The following symbols are recognized as memory-mapped registers:
  15458. 
  15459. File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent
  15460. 9.44.12 TIC54X Syntax
  15461. ---------------------
  15462. * Menu:
  15463. * TIC54X-Chars:: Special Characters
  15464. 
  15465. File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax
  15466. 9.44.12.1 Special Characters
  15467. ............................
  15468. The presence of a ';' appearing anywhere on a line indicates the start
  15469. of a comment that extends to the end of that line.
  15470. If a '#' appears as the first character of a line then the whole line
  15471. is treated as a comment, but in this case the line can also be a logical
  15472. line number directive (*note Comments::) or a preprocessor control
  15473. command (*note Preprocessing::).
  15474. The presence of an asterisk ('*') at the start of a line also
  15475. indicates a comment that extends to the end of that line.
  15476. The TIC54X assembler does not currently support a line separator
  15477. character.
  15478. 
  15479. File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies
  15480. 9.45 TIC6X Dependent Features
  15481. =============================
  15482. * Menu:
  15483. * TIC6X Options:: Options
  15484. * TIC6X Syntax:: Syntax
  15485. * TIC6X Directives:: Directives
  15486. 
  15487. File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent
  15488. 9.45.1 TIC6X Options
  15489. --------------------
  15490. '-march=ARCH'
  15491. Enable (only) instructions from architecture ARCH. By default, all
  15492. instructions are permitted.
  15493. The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+',
  15494. 'c67x', 'c67x+', 'c674x'.
  15495. '-mdsbt'
  15496. '-mno-dsbt'
  15497. The '-mdsbt' option causes the assembler to generate the
  15498. 'Tag_ABI_DSBT' attribute with a value of 1, indicating that the
  15499. code is using DSBT addressing. The '-mno-dsbt' option, the
  15500. default, causes the tag to have a value of 0, indicating that the
  15501. code does not use DSBT addressing. The linker will emit a warning
  15502. if objects of different type (DSBT and non-DSBT) are linked
  15503. together.
  15504. '-mpid=no'
  15505. '-mpid=near'
  15506. '-mpid=far'
  15507. The '-mpid=' option causes the assembler to generate the
  15508. 'Tag_ABI_PID' attribute with a value indicating the form of data
  15509. addressing used by the code. '-mpid=no', the default, indicates
  15510. position-dependent data addressing, '-mpid=near' indicates
  15511. position-independent addressing with GOT accesses using near DP
  15512. addressing, and '-mpid=far' indicates position-independent
  15513. addressing with GOT accesses using far DP addressing. The linker
  15514. will emit a warning if objects built with different settings of
  15515. this option are linked together.
  15516. '-mpic'
  15517. '-mno-pic'
  15518. The '-mpic' option causes the assembler to generate the
  15519. 'Tag_ABI_PIC' attribute with a value of 1, indicating that the code
  15520. is using position-independent code addressing, The '-mno-pic'
  15521. option, the default, causes the tag to have a value of 0,
  15522. indicating position-dependent code addressing. The linker will
  15523. emit a warning if objects of different type (position-dependent and
  15524. position-independent) are linked together.
  15525. '-mbig-endian'
  15526. '-mlittle-endian'
  15527. Generate code for the specified endianness. The default is
  15528. little-endian.
  15529. 
  15530. File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent
  15531. 9.45.2 TIC6X Syntax
  15532. -------------------
  15533. The presence of a ';' on a line indicates the start of a comment that
  15534. extends to the end of the current line. If a '#' or '*' appears as the
  15535. first character of a line, the whole line is treated as a comment. Note
  15536. that if a line starts with a '#' character then it can also be a logical
  15537. line number directive (*note Comments::) or a preprocessor control
  15538. command (*note Preprocessing::).
  15539. The '@' character can be used instead of a newline to separate
  15540. statements.
  15541. Instruction, register and functional unit names are case-insensitive.
  15542. 'as' requires fully-specified functional unit names, such as '.S1',
  15543. '.L1X' or '.D1T2', on all instructions using a functional unit.
  15544. For some instructions, there may be syntactic ambiguity between
  15545. register or functional unit names and the names of labels or other
  15546. symbols. To avoid this, enclose the ambiguous symbol name in
  15547. parentheses; register and functional unit names may not be enclosed in
  15548. parentheses.
  15549. 
  15550. File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent
  15551. 9.45.3 TIC6X Directives
  15552. -----------------------
  15553. Directives controlling the set of instructions accepted by the assembler
  15554. have effect for instructions between the directive and any subsequent
  15555. directive overriding it.
  15556. '.arch ARCH'
  15557. This has the same effect as '-march=ARCH'.
  15558. '.cantunwind'
  15559. Prevents unwinding through the current function. No personality
  15560. routine or exception table data is required or permitted.
  15561. If this is not specified then frame unwinding information will be
  15562. constructed from CFI directives. *note CFI directives::.
  15563. '.c6xabi_attribute TAG, VALUE'
  15564. Set the C6000 EABI build attribute TAG to VALUE.
  15565. The TAG is either an attribute number or one of 'Tag_ISA',
  15566. 'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed',
  15567. 'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID',
  15568. 'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment',
  15569. 'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and
  15570. 'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"',
  15571. or 'number, "string"' depending on the tag.
  15572. '.ehtype SYMBOL'
  15573. Output an exception type table reference to SYMBOL.
  15574. '.endp'
  15575. Marks the end of and exception table or function. If preceeded by
  15576. a '.handlerdata' directive then this also switched back to the
  15577. previous text section.
  15578. '.handlerdata'
  15579. Marks the end of the current function, and the start of the
  15580. exception table entry for that function. Anything between this
  15581. directive and the '.endp' directive will be added to the exception
  15582. table entry.
  15583. Must be preceded by a CFI block containing a '.cfi_lsda' directive.
  15584. '.nocmp'
  15585. Disallow use of C64x+ compact instructions in the current text
  15586. section.
  15587. '.personalityindex INDEX'
  15588. Sets the personality routine for the current function to the ABI
  15589. specified compact routine number INDEX
  15590. '.personality NAME'
  15591. Sets the personality routine for the current function to NAME.
  15592. '.scomm SYMBOL, SIZE, ALIGN'
  15593. Like '.comm', creating a common symbol SYMBOL with size SIZE and
  15594. alignment ALIGN, but unlike when using '.comm', this symbol will be
  15595. placed into the small BSS section by the linker.
  15596. 
  15597. File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies
  15598. 9.46 TILE-Gx Dependent Features
  15599. ===============================
  15600. * Menu:
  15601. * TILE-Gx Options:: TILE-Gx Options
  15602. * TILE-Gx Syntax:: TILE-Gx Syntax
  15603. * TILE-Gx Directives:: TILE-Gx Directives
  15604. 
  15605. File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent
  15606. 9.46.1 Options
  15607. --------------
  15608. The following table lists all available TILE-Gx specific options:
  15609. '-m32 | -m64'
  15610. Select the word size, either 32 bits or 64 bits.
  15611. '-EB | -EL'
  15612. Select the endianness, either big-endian (-EB) or little-endian
  15613. (-EL).
  15614. 
  15615. File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent
  15616. 9.46.2 Syntax
  15617. -------------
  15618. Block comments are delimited by '/*' and '*/'. End of line comments may
  15619. be introduced by '#'.
  15620. Instructions consist of a leading opcode or macro name followed by
  15621. whitespace and an optional comma-separated list of operands:
  15622. OPCODE [OPERAND, ...]
  15623. Instructions must be separated by a newline or semicolon.
  15624. There are two ways to write code: either write naked instructions,
  15625. which the assembler is free to combine into VLIW bundles, or specify the
  15626. VLIW bundles explicitly.
  15627. Bundles are specified using curly braces:
  15628. { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
  15629. A bundle can span multiple lines. If you want to put multiple
  15630. instructions on a line, whether in a bundle or not, you need to separate
  15631. them with semicolons as in this example.
  15632. A bundle may contain one or more instructions, up to the limit
  15633. specified by the ISA (currently three). If fewer instructions are
  15634. specified than the hardware supports in a bundle, the assembler inserts
  15635. 'fnop' instructions automatically.
  15636. The assembler will prefer to preserve the ordering of instructions
  15637. within the bundle, putting the first instruction in a lower-numbered
  15638. pipeline than the next one, etc. This fact, combined with the optional
  15639. use of explicit 'fnop' or 'nop' instructions, allows precise control
  15640. over which pipeline executes each instruction.
  15641. If the instructions cannot be bundled in the listed order, the
  15642. assembler will automatically try to find a valid pipeline assignment.
  15643. If there is no way to bundle the instructions together, the assembler
  15644. reports an error.
  15645. The assembler does not yet auto-bundle (automatically combine
  15646. multiple instructions into one bundle), but it reserves the right to do
  15647. so in the future. If you want to force an instruction to run by itself,
  15648. put it in a bundle explicitly with curly braces and use 'nop'
  15649. instructions (not 'fnop') to fill the remaining pipeline slots in that
  15650. bundle.
  15651. * Menu:
  15652. * TILE-Gx Opcodes:: Opcode Naming Conventions.
  15653. * TILE-Gx Registers:: Register Naming.
  15654. * TILE-Gx Modifiers:: Symbolic Operand Modifiers.
  15655. 
  15656. File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax
  15657. 9.46.2.1 Opcode Names
  15658. .....................
  15659. For a complete list of opcodes and descriptions of their semantics, see
  15660. 'TILE-Gx Instruction Set Architecture', available upon request at
  15661. www.tilera.com.
  15662. 
  15663. File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax
  15664. 9.46.2.2 Register Names
  15665. .......................
  15666. General-purpose registers are represented by predefined symbols of the
  15667. form 'rN', where N represents a number between '0' and '63'. However,
  15668. the following registers have canonical names that must be used instead:
  15669. 'r54'
  15670. sp
  15671. 'r55'
  15672. lr
  15673. 'r56'
  15674. sn
  15675. 'r57'
  15676. idn0
  15677. 'r58'
  15678. idn1
  15679. 'r59'
  15680. udn0
  15681. 'r60'
  15682. udn1
  15683. 'r61'
  15684. udn2
  15685. 'r62'
  15686. udn3
  15687. 'r63'
  15688. zero
  15689. The assembler will emit a warning if a numeric name is used instead
  15690. of the non-numeric name. The '.no_require_canonical_reg_names'
  15691. assembler pseudo-op turns off this warning.
  15692. '.require_canonical_reg_names' turns it back on.
  15693. 
  15694. File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax
  15695. 9.46.2.3 Symbolic Operand Modifiers
  15696. ...................................
  15697. The assembler supports several modifiers when using symbol addresses in
  15698. TILE-Gx instruction operands. The general syntax is the following:
  15699. modifier(symbol)
  15700. The following modifiers are supported:
  15701. 'hw0'
  15702. This modifier is used to load bits 0-15 of the symbol's address.
  15703. 'hw1'
  15704. This modifier is used to load bits 16-31 of the symbol's address.
  15705. 'hw2'
  15706. This modifier is used to load bits 32-47 of the symbol's address.
  15707. 'hw3'
  15708. This modifier is used to load bits 48-63 of the symbol's address.
  15709. 'hw0_last'
  15710. This modifier yields the same value as 'hw0', but it also checks
  15711. that the value does not overflow.
  15712. 'hw1_last'
  15713. This modifier yields the same value as 'hw1', but it also checks
  15714. that the value does not overflow.
  15715. 'hw2_last'
  15716. This modifier yields the same value as 'hw2', but it also checks
  15717. that the value does not overflow.
  15718. A 48-bit symbolic value is constructed by using the following
  15719. idiom:
  15720. moveli r0, hw2_last(sym)
  15721. shl16insli r0, r0, hw1(sym)
  15722. shl16insli r0, r0, hw0(sym)
  15723. 'hw0_got'
  15724. This modifier is used to load bits 0-15 of the symbol's offset in
  15725. the GOT entry corresponding to the symbol.
  15726. 'hw0_last_got'
  15727. This modifier yields the same value as 'hw0_got', but it also
  15728. checks that the value does not overflow.
  15729. 'hw1_last_got'
  15730. This modifier is used to load bits 16-31 of the symbol's offset in
  15731. the GOT entry corresponding to the symbol, and it also checks that
  15732. the value does not overflow.
  15733. 'plt'
  15734. This modifier is used for function symbols. It causes a _procedure
  15735. linkage table_, an array of code stubs, to be created at the time
  15736. the shared object is created or linked against, together with a
  15737. global offset table entry. The value is a pc-relative offset to
  15738. the corresponding stub code in the procedure linkage table. This
  15739. arrangement causes the run-time symbol resolver to be called to
  15740. look up and set the value of the symbol the first time the function
  15741. is called (at latest; depending environment variables). It is only
  15742. safe to leave the symbol unresolved this way if all references are
  15743. function calls.
  15744. 'hw0_plt'
  15745. This modifier is used to load bits 0-15 of the pc-relative address
  15746. of a plt entry.
  15747. 'hw1_plt'
  15748. This modifier is used to load bits 16-31 of the pc-relative address
  15749. of a plt entry.
  15750. 'hw1_last_plt'
  15751. This modifier yields the same value as 'hw1_plt', but it also
  15752. checks that the value does not overflow.
  15753. 'hw2_last_plt'
  15754. This modifier is used to load bits 32-47 of the pc-relative address
  15755. of a plt entry, and it also checks that the value does not
  15756. overflow.
  15757. 'hw0_tls_gd'
  15758. This modifier is used to load bits 0-15 of the offset of the GOT
  15759. entry of the symbol's TLS descriptor, to be used for
  15760. general-dynamic TLS accesses.
  15761. 'hw0_last_tls_gd'
  15762. This modifier yields the same value as 'hw0_tls_gd', but it also
  15763. checks that the value does not overflow.
  15764. 'hw1_last_tls_gd'
  15765. This modifier is used to load bits 16-31 of the offset of the GOT
  15766. entry of the symbol's TLS descriptor, to be used for
  15767. general-dynamic TLS accesses. It also checks that the value does
  15768. not overflow.
  15769. 'hw0_tls_ie'
  15770. This modifier is used to load bits 0-15 of the offset of the GOT
  15771. entry containing the offset of the symbol's address from the TCB,
  15772. to be used for initial-exec TLS accesses.
  15773. 'hw0_last_tls_ie'
  15774. This modifier yields the same value as 'hw0_tls_ie', but it also
  15775. checks that the value does not overflow.
  15776. 'hw1_last_tls_ie'
  15777. This modifier is used to load bits 16-31 of the offset of the GOT
  15778. entry containing the offset of the symbol's address from the TCB,
  15779. to be used for initial-exec TLS accesses. It also checks that the
  15780. value does not overflow.
  15781. 'hw0_tls_le'
  15782. This modifier is used to load bits 0-15 of the offset of the
  15783. symbol's address from the TCB, to be used for local-exec TLS
  15784. accesses.
  15785. 'hw0_last_tls_le'
  15786. This modifier yields the same value as 'hw0_tls_le', but it also
  15787. checks that the value does not overflow.
  15788. 'hw1_last_tls_le'
  15789. This modifier is used to load bits 16-31 of the offset of the
  15790. symbol's address from the TCB, to be used for local-exec TLS
  15791. accesses. It also checks that the value does not overflow.
  15792. 'tls_gd_call'
  15793. This modifier is used to tag an instrution as the "call" part of a
  15794. calling sequence for a TLS GD reference of its operand.
  15795. 'tls_gd_add'
  15796. This modifier is used to tag an instruction as the "add" part of a
  15797. calling sequence for a TLS GD reference of its operand.
  15798. 'tls_ie_load'
  15799. This modifier is used to tag an instruction as the "load" part of a
  15800. calling sequence for a TLS IE reference of its operand.
  15801. 
  15802. File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent
  15803. 9.46.3 TILE-Gx Directives
  15804. -------------------------
  15805. '.align EXPRESSION [, EXPRESSION]'
  15806. This is the generic .ALIGN directive. The first argument is the
  15807. requested alignment in bytes.
  15808. '.allow_suspicious_bundles'
  15809. Turns on error checking for combinations of instructions in a
  15810. bundle that probably indicate a programming error. This is on by
  15811. default.
  15812. '.no_allow_suspicious_bundles'
  15813. Turns off error checking for combinations of instructions in a
  15814. bundle that probably indicate a programming error.
  15815. '.require_canonical_reg_names'
  15816. Require that canonical register names be used, and emit a warning
  15817. if the numeric names are used. This is on by default.
  15818. '.no_require_canonical_reg_names'
  15819. Permit the use of numeric names for registers that have canonical
  15820. names.
  15821. 
  15822. File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies
  15823. 9.47 TILEPro Dependent Features
  15824. ===============================
  15825. * Menu:
  15826. * TILEPro Options:: TILEPro Options
  15827. * TILEPro Syntax:: TILEPro Syntax
  15828. * TILEPro Directives:: TILEPro Directives
  15829. 
  15830. File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent
  15831. 9.47.1 Options
  15832. --------------
  15833. 'as' has no machine-dependent command-line options for TILEPro.
  15834. 
  15835. File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent
  15836. 9.47.2 Syntax
  15837. -------------
  15838. Block comments are delimited by '/*' and '*/'. End of line comments may
  15839. be introduced by '#'.
  15840. Instructions consist of a leading opcode or macro name followed by
  15841. whitespace and an optional comma-separated list of operands:
  15842. OPCODE [OPERAND, ...]
  15843. Instructions must be separated by a newline or semicolon.
  15844. There are two ways to write code: either write naked instructions,
  15845. which the assembler is free to combine into VLIW bundles, or specify the
  15846. VLIW bundles explicitly.
  15847. Bundles are specified using curly braces:
  15848. { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
  15849. A bundle can span multiple lines. If you want to put multiple
  15850. instructions on a line, whether in a bundle or not, you need to separate
  15851. them with semicolons as in this example.
  15852. A bundle may contain one or more instructions, up to the limit
  15853. specified by the ISA (currently three). If fewer instructions are
  15854. specified than the hardware supports in a bundle, the assembler inserts
  15855. 'fnop' instructions automatically.
  15856. The assembler will prefer to preserve the ordering of instructions
  15857. within the bundle, putting the first instruction in a lower-numbered
  15858. pipeline than the next one, etc. This fact, combined with the optional
  15859. use of explicit 'fnop' or 'nop' instructions, allows precise control
  15860. over which pipeline executes each instruction.
  15861. If the instructions cannot be bundled in the listed order, the
  15862. assembler will automatically try to find a valid pipeline assignment.
  15863. If there is no way to bundle the instructions together, the assembler
  15864. reports an error.
  15865. The assembler does not yet auto-bundle (automatically combine
  15866. multiple instructions into one bundle), but it reserves the right to do
  15867. so in the future. If you want to force an instruction to run by itself,
  15868. put it in a bundle explicitly with curly braces and use 'nop'
  15869. instructions (not 'fnop') to fill the remaining pipeline slots in that
  15870. bundle.
  15871. * Menu:
  15872. * TILEPro Opcodes:: Opcode Naming Conventions.
  15873. * TILEPro Registers:: Register Naming.
  15874. * TILEPro Modifiers:: Symbolic Operand Modifiers.
  15875. 
  15876. File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax
  15877. 9.47.2.1 Opcode Names
  15878. .....................
  15879. For a complete list of opcodes and descriptions of their semantics, see
  15880. 'TILE Processor User Architecture Manual', available upon request at
  15881. www.tilera.com.
  15882. 
  15883. File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax
  15884. 9.47.2.2 Register Names
  15885. .......................
  15886. General-purpose registers are represented by predefined symbols of the
  15887. form 'rN', where N represents a number between '0' and '63'. However,
  15888. the following registers have canonical names that must be used instead:
  15889. 'r54'
  15890. sp
  15891. 'r55'
  15892. lr
  15893. 'r56'
  15894. sn
  15895. 'r57'
  15896. idn0
  15897. 'r58'
  15898. idn1
  15899. 'r59'
  15900. udn0
  15901. 'r60'
  15902. udn1
  15903. 'r61'
  15904. udn2
  15905. 'r62'
  15906. udn3
  15907. 'r63'
  15908. zero
  15909. The assembler will emit a warning if a numeric name is used instead
  15910. of the canonical name. The '.no_require_canonical_reg_names' assembler
  15911. pseudo-op turns off this warning. '.require_canonical_reg_names' turns
  15912. it back on.
  15913. 
  15914. File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax
  15915. 9.47.2.3 Symbolic Operand Modifiers
  15916. ...................................
  15917. The assembler supports several modifiers when using symbol addresses in
  15918. TILEPro instruction operands. The general syntax is the following:
  15919. modifier(symbol)
  15920. The following modifiers are supported:
  15921. 'lo16'
  15922. This modifier is used to load the low 16 bits of the symbol's
  15923. address, sign-extended to a 32-bit value (sign-extension allows it
  15924. to be range-checked against signed 16 bit immediate operands
  15925. without complaint).
  15926. 'hi16'
  15927. This modifier is used to load the high 16 bits of the symbol's
  15928. address, also sign-extended to a 32-bit value.
  15929. 'ha16'
  15930. 'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is
  15931. negative it adds one to the 'hi16(N)' value. This way 'lo16' and
  15932. 'ha16' can be added to create any 32-bit value using 'auli'. For
  15933. example, here is how you move an arbitrary 32-bit address into r3:
  15934. moveli r3, lo16(sym)
  15935. auli r3, r3, ha16(sym)
  15936. 'got'
  15937. This modifier is used to load the offset of the GOT entry
  15938. corresponding to the symbol.
  15939. 'got_lo16'
  15940. This modifier is used to load the sign-extended low 16 bits of the
  15941. offset of the GOT entry corresponding to the symbol.
  15942. 'got_hi16'
  15943. This modifier is used to load the sign-extended high 16 bits of the
  15944. offset of the GOT entry corresponding to the symbol.
  15945. 'got_ha16'
  15946. This modifier is like 'got_hi16', but it adds one if 'got_lo16' of
  15947. the input value is negative.
  15948. 'plt'
  15949. This modifier is used for function symbols. It causes a _procedure
  15950. linkage table_, an array of code stubs, to be created at the time
  15951. the shared object is created or linked against, together with a
  15952. global offset table entry. The value is a pc-relative offset to
  15953. the corresponding stub code in the procedure linkage table. This
  15954. arrangement causes the run-time symbol resolver to be called to
  15955. look up and set the value of the symbol the first time the function
  15956. is called (at latest; depending environment variables). It is only
  15957. safe to leave the symbol unresolved this way if all references are
  15958. function calls.
  15959. 'tls_gd'
  15960. This modifier is used to load the offset of the GOT entry of the
  15961. symbol's TLS descriptor, to be used for general-dynamic TLS
  15962. accesses.
  15963. 'tls_gd_lo16'
  15964. This modifier is used to load the sign-extended low 16 bits of the
  15965. offset of the GOT entry of the symbol's TLS descriptor, to be used
  15966. for general dynamic TLS accesses.
  15967. 'tls_gd_hi16'
  15968. This modifier is used to load the sign-extended high 16 bits of the
  15969. offset of the GOT entry of the symbol's TLS descriptor, to be used
  15970. for general dynamic TLS accesses.
  15971. 'tls_gd_ha16'
  15972. This modifier is like 'tls_gd_hi16', but it adds one to the value
  15973. if 'tls_gd_lo16' of the input value is negative.
  15974. 'tls_ie'
  15975. This modifier is used to load the offset of the GOT entry
  15976. containing the offset of the symbol's address from the TCB, to be
  15977. used for initial-exec TLS accesses.
  15978. 'tls_ie_lo16'
  15979. This modifier is used to load the low 16 bits of the offset of the
  15980. GOT entry containing the offset of the symbol's address from the
  15981. TCB, to be used for initial-exec TLS accesses.
  15982. 'tls_ie_hi16'
  15983. This modifier is used to load the high 16 bits of the offset of the
  15984. GOT entry containing the offset of the symbol's address from the
  15985. TCB, to be used for initial-exec TLS accesses.
  15986. 'tls_ie_ha16'
  15987. This modifier is like 'tls_ie_hi16', but it adds one to the value
  15988. if 'tls_ie_lo16' of the input value is negative.
  15989. 'tls_le'
  15990. This modifier is used to load the offset of the symbol's address
  15991. from the TCB, to be used for local-exec TLS accesses.
  15992. 'tls_le_lo16'
  15993. This modifier is used to load the low 16 bits of the offset of the
  15994. symbol's address from the TCB, to be used for local-exec TLS
  15995. accesses.
  15996. 'tls_le_hi16'
  15997. This modifier is used to load the high 16 bits of the offset of the
  15998. symbol's address from the TCB, to be used for local-exec TLS
  15999. accesses.
  16000. 'tls_le_ha16'
  16001. This modifier is like 'tls_le_hi16', but it adds one to the value
  16002. if 'tls_le_lo16' of the input value is negative.
  16003. 'tls_gd_call'
  16004. This modifier is used to tag an instrution as the "call" part of a
  16005. calling sequence for a TLS GD reference of its operand.
  16006. 'tls_gd_add'
  16007. This modifier is used to tag an instruction as the "add" part of a
  16008. calling sequence for a TLS GD reference of its operand.
  16009. 'tls_ie_load'
  16010. This modifier is used to tag an instruction as the "load" part of a
  16011. calling sequence for a TLS IE reference of its operand.
  16012. 
  16013. File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent
  16014. 9.47.3 TILEPro Directives
  16015. -------------------------
  16016. '.align EXPRESSION [, EXPRESSION]'
  16017. This is the generic .ALIGN directive. The first argument is the
  16018. requested alignment in bytes.
  16019. '.allow_suspicious_bundles'
  16020. Turns on error checking for combinations of instructions in a
  16021. bundle that probably indicate a programming error. This is on by
  16022. default.
  16023. '.no_allow_suspicious_bundles'
  16024. Turns off error checking for combinations of instructions in a
  16025. bundle that probably indicate a programming error.
  16026. '.require_canonical_reg_names'
  16027. Require that canonical register names be used, and emit a warning
  16028. if the numeric names are used. This is on by default.
  16029. '.no_require_canonical_reg_names'
  16030. Permit the use of numeric names for registers that have canonical
  16031. names.
  16032. 
  16033. File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies
  16034. 9.48 v850 Dependent Features
  16035. ============================
  16036. * Menu:
  16037. * V850 Options:: Options
  16038. * V850 Syntax:: Syntax
  16039. * V850 Floating Point:: Floating Point
  16040. * V850 Directives:: V850 Machine Directives
  16041. * V850 Opcodes:: Opcodes
  16042. 
  16043. File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
  16044. 9.48.1 Options
  16045. --------------
  16046. 'as' supports the following additional command-line options for the V850
  16047. processor family:
  16048. '-wsigned_overflow'
  16049. Causes warnings to be produced when signed immediate values
  16050. overflow the space available for then within their opcodes. By
  16051. default this option is disabled as it is possible to receive
  16052. spurious warnings due to using exact bit patterns as immediate
  16053. constants.
  16054. '-wunsigned_overflow'
  16055. Causes warnings to be produced when unsigned immediate values
  16056. overflow the space available for then within their opcodes. By
  16057. default this option is disabled as it is possible to receive
  16058. spurious warnings due to using exact bit patterns as immediate
  16059. constants.
  16060. '-mv850'
  16061. Specifies that the assembled code should be marked as being
  16062. targeted at the V850 processor. This allows the linker to detect
  16063. attempts to link such code with code assembled for other
  16064. processors.
  16065. '-mv850e'
  16066. Specifies that the assembled code should be marked as being
  16067. targeted at the V850E processor. This allows the linker to detect
  16068. attempts to link such code with code assembled for other
  16069. processors.
  16070. '-mv850e1'
  16071. Specifies that the assembled code should be marked as being
  16072. targeted at the V850E1 processor. This allows the linker to detect
  16073. attempts to link such code with code assembled for other
  16074. processors.
  16075. '-mv850any'
  16076. Specifies that the assembled code should be marked as being
  16077. targeted at the V850 processor but support instructions that are
  16078. specific to the extended variants of the process. This allows the
  16079. production of binaries that contain target specific code, but which
  16080. are also intended to be used in a generic fashion. For example
  16081. libgcc.a contains generic routines used by the code produced by GCC
  16082. for all versions of the v850 architecture, together with support
  16083. routines only used by the V850E architecture.
  16084. '-mv850e2'
  16085. Specifies that the assembled code should be marked as being
  16086. targeted at the V850E2 processor. This allows the linker to detect
  16087. attempts to link such code with code assembled for other
  16088. processors.
  16089. '-mv850e2v3'
  16090. Specifies that the assembled code should be marked as being
  16091. targeted at the V850E2V3 processor. This allows the linker to
  16092. detect attempts to link such code with code assembled for other
  16093. processors.
  16094. '-mv850e2v4'
  16095. This is an alias for '-mv850e3v5'.
  16096. '-mv850e3v5'
  16097. Specifies that the assembled code should be marked as being
  16098. targeted at the V850E3V5 processor. This allows the linker to
  16099. detect attempts to link such code with code assembled for other
  16100. processors.
  16101. '-mrelax'
  16102. Enables relaxation. This allows the .longcall and .longjump pseudo
  16103. ops to be used in the assembler source code. These ops label
  16104. sections of code which are either a long function call or a long
  16105. branch. The assembler will then flag these sections of code and
  16106. the linker will attempt to relax them.
  16107. '-mgcc-abi'
  16108. Marks the generated object file as supporting the old GCC ABI.
  16109. '-mrh850-abi'
  16110. Marks the generated object file as supporting the RH850 ABI. This
  16111. is the default.
  16112. '-m8byte-align'
  16113. Marks the generated object file as supporting a maximum 64-bits of
  16114. alignment for variables defined in the source code.
  16115. '-m4byte-align'
  16116. Marks the generated object file as supporting a maximum 32-bits of
  16117. alignment for variables defined in the source code. This is the
  16118. default.
  16119. '-msoft-float'
  16120. Marks the generated object file as not using any floating point
  16121. instructions - and hence can be linked with other V850 binaries
  16122. that do or do not use floating point. This is the default for
  16123. binaries for architectures earlier than the 'e2v3'.
  16124. '-mhard-float'
  16125. Marks the generated object file as one that uses floating point
  16126. instructions - and hence can only be linked with other V850
  16127. binaries that use the same kind of floating point instructions, or
  16128. with binaries that do not use floating point at all. This is the
  16129. default for binaries the 'e2v3' and later architectures.
  16130. 
  16131. File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
  16132. 9.48.2 Syntax
  16133. -------------
  16134. * Menu:
  16135. * V850-Chars:: Special Characters
  16136. * V850-Regs:: Register Names
  16137. 
  16138. File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
  16139. 9.48.2.1 Special Characters
  16140. ...........................
  16141. '#' is the line comment character. If a '#' appears as the first
  16142. character of a line, the whole line is treated as a comment, but in this
  16143. case the line can also be a logical line number directive (*note
  16144. Comments::) or a preprocessor control command (*note Preprocessing::).
  16145. Two dashes ('--') can also be used to start a line comment.
  16146. The ';' character can be used to separate statements on the same
  16147. line.
  16148. 
  16149. File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
  16150. 9.48.2.2 Register Names
  16151. .......................
  16152. 'as' supports the following names for registers:
  16153. 'general register 0'
  16154. r0, zero
  16155. 'general register 1'
  16156. r1
  16157. 'general register 2'
  16158. r2, hp
  16159. 'general register 3'
  16160. r3, sp
  16161. 'general register 4'
  16162. r4, gp
  16163. 'general register 5'
  16164. r5, tp
  16165. 'general register 6'
  16166. r6
  16167. 'general register 7'
  16168. r7
  16169. 'general register 8'
  16170. r8
  16171. 'general register 9'
  16172. r9
  16173. 'general register 10'
  16174. r10
  16175. 'general register 11'
  16176. r11
  16177. 'general register 12'
  16178. r12
  16179. 'general register 13'
  16180. r13
  16181. 'general register 14'
  16182. r14
  16183. 'general register 15'
  16184. r15
  16185. 'general register 16'
  16186. r16
  16187. 'general register 17'
  16188. r17
  16189. 'general register 18'
  16190. r18
  16191. 'general register 19'
  16192. r19
  16193. 'general register 20'
  16194. r20
  16195. 'general register 21'
  16196. r21
  16197. 'general register 22'
  16198. r22
  16199. 'general register 23'
  16200. r23
  16201. 'general register 24'
  16202. r24
  16203. 'general register 25'
  16204. r25
  16205. 'general register 26'
  16206. r26
  16207. 'general register 27'
  16208. r27
  16209. 'general register 28'
  16210. r28
  16211. 'general register 29'
  16212. r29
  16213. 'general register 30'
  16214. r30, ep
  16215. 'general register 31'
  16216. r31, lp
  16217. 'system register 0'
  16218. eipc
  16219. 'system register 1'
  16220. eipsw
  16221. 'system register 2'
  16222. fepc
  16223. 'system register 3'
  16224. fepsw
  16225. 'system register 4'
  16226. ecr
  16227. 'system register 5'
  16228. psw
  16229. 'system register 16'
  16230. ctpc
  16231. 'system register 17'
  16232. ctpsw
  16233. 'system register 18'
  16234. dbpc
  16235. 'system register 19'
  16236. dbpsw
  16237. 'system register 20'
  16238. ctbp
  16239. 
  16240. File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
  16241. 9.48.3 Floating Point
  16242. ---------------------
  16243. The V850 family uses IEEE floating-point numbers.
  16244. 
  16245. File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
  16246. 9.48.4 V850 Machine Directives
  16247. ------------------------------
  16248. '.offset <EXPRESSION>'
  16249. Moves the offset into the current section to the specified amount.
  16250. '.section "name", <type>'
  16251. This is an extension to the standard .section directive. It sets
  16252. the current section to be <type> and creates an alias for this
  16253. section called "name".
  16254. '.v850'
  16255. Specifies that the assembled code should be marked as being
  16256. targeted at the V850 processor. This allows the linker to detect
  16257. attempts to link such code with code assembled for other
  16258. processors.
  16259. '.v850e'
  16260. Specifies that the assembled code should be marked as being
  16261. targeted at the V850E processor. This allows the linker to detect
  16262. attempts to link such code with code assembled for other
  16263. processors.
  16264. '.v850e1'
  16265. Specifies that the assembled code should be marked as being
  16266. targeted at the V850E1 processor. This allows the linker to detect
  16267. attempts to link such code with code assembled for other
  16268. processors.
  16269. '.v850e2'
  16270. Specifies that the assembled code should be marked as being
  16271. targeted at the V850E2 processor. This allows the linker to detect
  16272. attempts to link such code with code assembled for other
  16273. processors.
  16274. '.v850e2v3'
  16275. Specifies that the assembled code should be marked as being
  16276. targeted at the V850E2V3 processor. This allows the linker to
  16277. detect attempts to link such code with code assembled for other
  16278. processors.
  16279. '.v850e2v4'
  16280. Specifies that the assembled code should be marked as being
  16281. targeted at the V850E3V5 processor. This allows the linker to
  16282. detect attempts to link such code with code assembled for other
  16283. processors.
  16284. '.v850e3v5'
  16285. Specifies that the assembled code should be marked as being
  16286. targeted at the V850E3V5 processor. This allows the linker to
  16287. detect attempts to link such code with code assembled for other
  16288. processors.
  16289. 
  16290. File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
  16291. 9.48.5 Opcodes
  16292. --------------
  16293. 'as' implements all the standard V850 opcodes.
  16294. 'as' also implements the following pseudo ops:
  16295. 'hi0()'
  16296. Computes the higher 16 bits of the given expression and stores it
  16297. into the immediate operand field of the given instruction. For
  16298. example:
  16299. 'mulhi hi0(here - there), r5, r6'
  16300. computes the difference between the address of labels 'here' and
  16301. 'there', takes the upper 16 bits of this difference, shifts it down
  16302. 16 bits and then multiplies it by the lower 16 bits in register 5,
  16303. putting the result into register 6.
  16304. 'lo()'
  16305. Computes the lower 16 bits of the given expression and stores it
  16306. into the immediate operand field of the given instruction. For
  16307. example:
  16308. 'addi lo(here - there), r5, r6'
  16309. computes the difference between the address of labels 'here' and
  16310. 'there', takes the lower 16 bits of this difference and adds it to
  16311. register 5, putting the result into register 6.
  16312. 'hi()'
  16313. Computes the higher 16 bits of the given expression and then adds
  16314. the value of the most significant bit of the lower 16 bits of the
  16315. expression and stores the result into the immediate operand field
  16316. of the given instruction. For example the following code can be
  16317. used to compute the address of the label 'here' and store it into
  16318. register 6:
  16319. 'movhi hi(here), r0, r6' 'movea lo(here), r6, r6'
  16320. The reason for this special behaviour is that movea performs a sign
  16321. extension on its immediate operand. So for example if the address
  16322. of 'here' was 0xFFFFFFFF then without the special behaviour of the
  16323. hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
  16324. then the movea instruction would takes its immediate operand,
  16325. 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into
  16326. r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With
  16327. the hi() pseudo op adding in the top bit of the lo() pseudo op, the
  16328. movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000),
  16329. so that the movea instruction stores 0xFFFFFFFF into r6 - the right
  16330. value.
  16331. 'hilo()'
  16332. Computes the 32 bit value of the given expression and stores it
  16333. into the immediate operand field of the given instruction (which
  16334. must be a mov instruction). For example:
  16335. 'mov hilo(here), r6'
  16336. computes the absolute address of label 'here' and puts the result
  16337. into register 6.
  16338. 'sdaoff()'
  16339. Computes the offset of the named variable from the start of the
  16340. Small Data Area (whoes address is held in register 4, the GP
  16341. register) and stores the result as a 16 bit signed value in the
  16342. immediate operand field of the given instruction. For example:
  16343. 'ld.w sdaoff(_a_variable)[gp],r6'
  16344. loads the contents of the location pointed to by the label
  16345. '_a_variable' into register 6, provided that the label is located
  16346. somewhere within +/- 32K of the address held in the GP register.
  16347. [Note the linker assumes that the GP register contains a fixed
  16348. address set to the address of the label called '__gp'. This can
  16349. either be set up automatically by the linker, or specifically set
  16350. by using the '--defsym __gp=<value>' command line option].
  16351. 'tdaoff()'
  16352. Computes the offset of the named variable from the start of the
  16353. Tiny Data Area (whoes address is held in register 30, the EP
  16354. register) and stores the result as a 4,5, 7 or 8 bit unsigned value
  16355. in the immediate operand field of the given instruction. For
  16356. example:
  16357. 'sld.w tdaoff(_a_variable)[ep],r6'
  16358. loads the contents of the location pointed to by the label
  16359. '_a_variable' into register 6, provided that the label is located
  16360. somewhere within +256 bytes of the address held in the EP register.
  16361. [Note the linker assumes that the EP register contains a fixed
  16362. address set to the address of the label called '__ep'. This can
  16363. either be set up automatically by the linker, or specifically set
  16364. by using the '--defsym __ep=<value>' command line option].
  16365. 'zdaoff()'
  16366. Computes the offset of the named variable from address 0 and stores
  16367. the result as a 16 bit signed value in the immediate operand field
  16368. of the given instruction. For example:
  16369. 'movea zdaoff(_a_variable),zero,r6'
  16370. puts the address of the label '_a_variable' into register 6,
  16371. assuming that the label is somewhere within the first 32K of
  16372. memory. (Strictly speaking it also possible to access the last 32K
  16373. of memory as well, as the offsets are signed).
  16374. 'ctoff()'
  16375. Computes the offset of the named variable from the start of the
  16376. Call Table Area (whoes address is helg in system register 20, the
  16377. CTBP register) and stores the result a 6 or 16 bit unsigned value
  16378. in the immediate field of then given instruction or piece of data.
  16379. For example:
  16380. 'callt ctoff(table_func1)'
  16381. will put the call the function whoes address is held in the call
  16382. table at the location labeled 'table_func1'.
  16383. '.longcall name'
  16384. Indicates that the following sequence of instructions is a long
  16385. call to function 'name'. The linker will attempt to shorten this
  16386. call sequence if 'name' is within a 22bit offset of the call. Only
  16387. valid if the '-mrelax' command line switch has been enabled.
  16388. '.longjump name'
  16389. Indicates that the following sequence of instructions is a long
  16390. jump to label 'name'. The linker will attempt to shorten this code
  16391. sequence if 'name' is within a 22bit offset of the jump. Only
  16392. valid if the '-mrelax' command line switch has been enabled.
  16393. For information on the V850 instruction set, see 'V850 Family
  16394. 32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
  16395. Ltd.
  16396. 
  16397. File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
  16398. 9.49 VAX Dependent Features
  16399. ===========================
  16400. * Menu:
  16401. * VAX-Opts:: VAX Command-Line Options
  16402. * VAX-float:: VAX Floating Point
  16403. * VAX-directives:: Vax Machine Directives
  16404. * VAX-opcodes:: VAX Opcodes
  16405. * VAX-branch:: VAX Branch Improvement
  16406. * VAX-operands:: VAX Operands
  16407. * VAX-no:: Not Supported on VAX
  16408. * VAX-Syntax:: VAX Syntax
  16409. 
  16410. File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
  16411. 9.49.1 VAX Command-Line Options
  16412. -------------------------------
  16413. The Vax version of 'as' accepts any of the following options, gives a
  16414. warning message that the option was ignored and proceeds. These options
  16415. are for compatibility with scripts designed for other people's
  16416. assemblers.
  16417. '-D (Debug)'
  16418. '-S (Symbol Table)'
  16419. '-T (Token Trace)'
  16420. These are obsolete options used to debug old assemblers.
  16421. '-d (Displacement size for JUMPs)'
  16422. This option expects a number following the '-d'. Like options that
  16423. expect filenames, the number may immediately follow the '-d' (old
  16424. standard) or constitute the whole of the command line argument that
  16425. follows '-d' (GNU standard).
  16426. '-V (Virtualize Interpass Temporary File)'
  16427. Some other assemblers use a temporary file. This option commanded
  16428. them to keep the information in active memory rather than in a disk
  16429. file. 'as' always does this, so this option is redundant.
  16430. '-J (JUMPify Longer Branches)'
  16431. Many 32-bit computers permit a variety of branch instructions to do
  16432. the same job. Some of these instructions are short (and fast) but
  16433. have a limited range; others are long (and slow) but can branch
  16434. anywhere in virtual memory. Often there are 3 flavors of branch:
  16435. short, medium and long. Some other assemblers would emit short and
  16436. medium branches, unless told by this option to emit short and long
  16437. branches.
  16438. '-t (Temporary File Directory)'
  16439. Some other assemblers may use a temporary file, and this option
  16440. takes a filename being the directory to site the temporary file.
  16441. Since 'as' does not use a temporary disk file, this option makes no
  16442. difference. '-t' needs exactly one filename.
  16443. The Vax version of the assembler accepts additional options when
  16444. compiled for VMS:
  16445. '-h N'
  16446. External symbol or section (used for global variables) names are
  16447. not case sensitive on VAX/VMS and always mapped to upper case.
  16448. This is contrary to the C language definition which explicitly
  16449. distinguishes upper and lower case. To implement a standard
  16450. conforming C compiler, names must be changed (mapped) to preserve
  16451. the case information. The default mapping is to convert all lower
  16452. case characters to uppercase and adding an underscore followed by a
  16453. 6 digit hex value, representing a 24 digit binary value. The one
  16454. digits in the binary value represent which characters are uppercase
  16455. in the original symbol name.
  16456. The '-h N' option determines how we map names. This takes several
  16457. values. No '-h' switch at all allows case hacking as described
  16458. above. A value of zero ('-h0') implies names should be upper case,
  16459. and inhibits the case hack. A value of 2 ('-h2') implies names
  16460. should be all lower case, with no case hack. A value of 3 ('-h3')
  16461. implies that case should be preserved. The value 1 is unused. The
  16462. '-H' option directs 'as' to display every mapped symbol during
  16463. assembly.
  16464. Symbols whose names include a dollar sign '$' are exceptions to the
  16465. general name mapping. These symbols are normally only used to
  16466. reference VMS library names. Such symbols are always mapped to
  16467. upper case.
  16468. '-+'
  16469. The '-+' option causes 'as' to truncate any symbol name larger than
  16470. 31 characters. The '-+' option also prevents some code following
  16471. the '_main' symbol normally added to make the object file
  16472. compatible with Vax-11 "C".
  16473. '-1'
  16474. This option is ignored for backward compatibility with 'as' version
  16475. 1.x.
  16476. '-H'
  16477. The '-H' option causes 'as' to print every symbol which was changed
  16478. by case mapping.
  16479. 
  16480. File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
  16481. 9.49.2 VAX Floating Point
  16482. -------------------------
  16483. Conversion of flonums to floating point is correct, and compatible with
  16484. previous assemblers. Rounding is towards zero if the remainder is
  16485. exactly half the least significant bit.
  16486. 'D', 'F', 'G' and 'H' floating point formats are understood.
  16487. Immediate floating literals (_e.g._ 'S`$6.9') are rendered
  16488. correctly. Again, rounding is towards zero in the boundary case.
  16489. The '.float' directive produces 'f' format numbers. The '.double'
  16490. directive produces 'd' format numbers.
  16491. 
  16492. File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
  16493. 9.49.3 Vax Machine Directives
  16494. -----------------------------
  16495. The Vax version of the assembler supports four directives for generating
  16496. Vax floating point constants. They are described in the table below.
  16497. '.dfloat'
  16498. This expects zero or more flonums, separated by commas, and
  16499. assembles Vax 'd' format 64-bit floating point constants.
  16500. '.ffloat'
  16501. This expects zero or more flonums, separated by commas, and
  16502. assembles Vax 'f' format 32-bit floating point constants.
  16503. '.gfloat'
  16504. This expects zero or more flonums, separated by commas, and
  16505. assembles Vax 'g' format 64-bit floating point constants.
  16506. '.hfloat'
  16507. This expects zero or more flonums, separated by commas, and
  16508. assembles Vax 'h' format 128-bit floating point constants.
  16509. 
  16510. File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
  16511. 9.49.4 VAX Opcodes
  16512. ------------------
  16513. All DEC mnemonics are supported. Beware that 'case...' instructions
  16514. have exactly 3 operands. The dispatch table that follows the 'case...'
  16515. instruction should be made with '.word' statements. This is compatible
  16516. with all unix assemblers we know of.
  16517. 
  16518. File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
  16519. 9.49.5 VAX Branch Improvement
  16520. -----------------------------
  16521. Certain pseudo opcodes are permitted. They are for branch instructions.
  16522. They expand to the shortest branch instruction that reaches the target.
  16523. Generally these mnemonics are made by substituting 'j' for 'b' at the
  16524. start of a DEC mnemonic. This feature is included both for
  16525. compatibility and to help compilers. If you do not need this feature,
  16526. avoid these opcodes. Here are the mnemonics, and the code they can
  16527. expand into.
  16528. 'jbsb'
  16529. 'Jsb' is already an instruction mnemonic, so we chose 'jbsb'.
  16530. (byte displacement)
  16531. 'bsbb ...'
  16532. (word displacement)
  16533. 'bsbw ...'
  16534. (long displacement)
  16535. 'jsb ...'
  16536. 'jbr'
  16537. 'jr'
  16538. Unconditional branch.
  16539. (byte displacement)
  16540. 'brb ...'
  16541. (word displacement)
  16542. 'brw ...'
  16543. (long displacement)
  16544. 'jmp ...'
  16545. 'jCOND'
  16546. COND may be any one of the conditional branches 'neq', 'nequ',
  16547. 'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs',
  16548. 'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests
  16549. 'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs',
  16550. 'lbc'. NOTCOND is the opposite condition to COND.
  16551. (byte displacement)
  16552. 'bCOND ...'
  16553. (word displacement)
  16554. 'bNOTCOND foo ; brw ... ; foo:'
  16555. (long displacement)
  16556. 'bNOTCOND foo ; jmp ... ; foo:'
  16557. 'jacbX'
  16558. X may be one of 'b d f g h l w'.
  16559. (word displacement)
  16560. 'OPCODE ...'
  16561. (long displacement)
  16562. OPCODE ..., foo ;
  16563. brb bar ;
  16564. foo: jmp ... ;
  16565. bar:
  16566. 'jaobYYY'
  16567. YYY may be one of 'lss leq'.
  16568. 'jsobZZZ'
  16569. ZZZ may be one of 'geq gtr'.
  16570. (byte displacement)
  16571. 'OPCODE ...'
  16572. (word displacement)
  16573. OPCODE ..., foo ;
  16574. brb bar ;
  16575. foo: brw DESTINATION ;
  16576. bar:
  16577. (long displacement)
  16578. OPCODE ..., foo ;
  16579. brb bar ;
  16580. foo: jmp DESTINATION ;
  16581. bar:
  16582. 'aobleq'
  16583. 'aoblss'
  16584. 'sobgeq'
  16585. 'sobgtr'
  16586. (byte displacement)
  16587. 'OPCODE ...'
  16588. (word displacement)
  16589. OPCODE ..., foo ;
  16590. brb bar ;
  16591. foo: brw DESTINATION ;
  16592. bar:
  16593. (long displacement)
  16594. OPCODE ..., foo ;
  16595. brb bar ;
  16596. foo: jmp DESTINATION ;
  16597. bar:
  16598. 
  16599. File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
  16600. 9.49.6 VAX Operands
  16601. -------------------
  16602. The immediate character is '$' for Unix compatibility, not '#' as DEC
  16603. writes it.
  16604. The indirect character is '*' for Unix compatibility, not '@' as DEC
  16605. writes it.
  16606. The displacement sizing character is '`' (an accent grave) for Unix
  16607. compatibility, not '^' as DEC writes it. The letter preceding '`' may
  16608. have either case. 'G' is not understood, but all other letters ('b i l
  16609. s w') are understood.
  16610. Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper
  16611. and lower case letters are equivalent.
  16612. For instance
  16613. tstb *w`$4(r5)
  16614. Any expression is permitted in an operand. Operands are comma
  16615. separated.
  16616. 
  16617. File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent
  16618. 9.49.7 Not Supported on VAX
  16619. ---------------------------
  16620. Vax bit fields can not be assembled with 'as'. Someone can add the
  16621. required code if they really need it.
  16622. 
  16623. File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent
  16624. 9.49.8 VAX Syntax
  16625. -----------------
  16626. * Menu:
  16627. * VAX-Chars:: Special Characters
  16628. 
  16629. File: as.info, Node: VAX-Chars, Up: VAX-Syntax
  16630. 9.49.8.1 Special Characters
  16631. ...........................
  16632. The presence of a '#' appearing anywhere on a line indicates the start
  16633. of a comment that extends to the end of that line.
  16634. If a '#' appears as the first character of a line then the whole line
  16635. is treated as a comment, but in this case the line can also be a logical
  16636. line number directive (*note Comments::) or a preprocessor control
  16637. command (*note Preprocessing::).
  16638. The ';' character can be used to separate statements on the same
  16639. line.
  16640. 
  16641. File: as.info, Node: Visium-Dependent, Next: XGATE-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies
  16642. 9.50 Visium Dependent Features
  16643. ==============================
  16644. * Menu:
  16645. * Visium Options:: Options
  16646. * Visium Syntax:: Syntax
  16647. * Visium Opcodes:: Opcodes
  16648. 
  16649. File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent
  16650. 9.50.1 Options
  16651. --------------
  16652. The Visium assembler implements one machine-specific option:
  16653. '-mtune=ARCH'
  16654. This option specifies the target architecture. If an attempt is
  16655. made to assemble an instruction that will not execute on the target
  16656. architecture, the assembler will issue an error message.
  16657. The following names are recognized: 'mcm24' 'mcm' 'gr5' 'gr6'
  16658. 
  16659. File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent
  16660. 9.50.2 Syntax
  16661. -------------
  16662. * Menu:
  16663. * Visium Characters:: Special Characters
  16664. * Visium Registers:: Register Names
  16665. 
  16666. File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax
  16667. 9.50.2.1 Special Characters
  16668. ...........................
  16669. Line comments are introduced either by the '!' character or by the ';'
  16670. character appearing anywhere on a line.
  16671. A hash character ('#') as the first character on a line also marks
  16672. the start of a line comment, but in this case it could also be a logical
  16673. line number directive (*note Comments::) or a preprocessor control
  16674. command (*note Preprocessing::).
  16675. The Visium assembler does not currently support a line separator
  16676. character.
  16677. 
  16678. File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax
  16679. 9.50.2.2 Register Names
  16680. .......................
  16681. Registers can be specified either by using their canonical mnemonic
  16682. names or by using their alias if they have one, for example 'sp'.
  16683. 
  16684. File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent
  16685. 9.50.3 Opcodes
  16686. --------------
  16687. All the standard opcodes of the architecture are implemented, along with
  16688. the following three pseudo-instructions: 'cmp', 'cmpc', 'move'.
  16689. In addition, the following two illegal opcodes are implemented and
  16690. used by the simulation:
  16691. stop 5-bit immediate, SourceA
  16692. trace 5-bit immediate, SourceA
  16693. 
  16694. File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies
  16695. 9.51 XGATE Dependent Features
  16696. =============================
  16697. * Menu:
  16698. * XGATE-Opts:: XGATE Options
  16699. * XGATE-Syntax:: Syntax
  16700. * XGATE-Directives:: Assembler Directives
  16701. * XGATE-Float:: Floating Point
  16702. * XGATE-opcodes:: Opcodes
  16703. 
  16704. File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent
  16705. 9.51.1 XGATE Options
  16706. --------------------
  16707. The Freescale XGATE version of 'as' has a few machine dependent options.
  16708. '-mshort'
  16709. This option controls the ABI and indicates to use a 16-bit integer
  16710. ABI. It has no effect on the assembled instructions. This is the
  16711. default.
  16712. '-mlong'
  16713. This option controls the ABI and indicates to use a 32-bit integer
  16714. ABI.
  16715. '-mshort-double'
  16716. This option controls the ABI and indicates to use a 32-bit float
  16717. ABI. This is the default.
  16718. '-mlong-double'
  16719. This option controls the ABI and indicates to use a 64-bit float
  16720. ABI.
  16721. '--print-insn-syntax'
  16722. You can use the '--print-insn-syntax' option to obtain the syntax
  16723. description of the instruction when an error is detected.
  16724. '--print-opcodes'
  16725. The '--print-opcodes' option prints the list of all the
  16726. instructions with their syntax. Once the list is printed 'as'
  16727. exits.
  16728. 
  16729. File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent
  16730. 9.51.2 Syntax
  16731. -------------
  16732. In XGATE RISC syntax, the instruction name comes first and it may be
  16733. followed by up to three operands. Operands are separated by commas
  16734. (','). 'as' will complain if too many operands are specified for a
  16735. given instruction. The same will happen if you specified too few
  16736. operands.
  16737. nop
  16738. ldl #23
  16739. CMP R1, R2
  16740. The presence of a ';' character or a '!' character anywhere on a line
  16741. indicates the start of a comment that extends to the end of that line.
  16742. A '*' or a '#' character at the start of a line also introduces a
  16743. line comment, but these characters do not work elsewhere on the line.
  16744. If the first character of the line is a '#' then as well as starting a
  16745. comment, the line could also be logical line number directive (*note
  16746. Comments::) or a preprocessor control command (*note Preprocessing::).
  16747. The XGATE assembler does not currently support a line separator
  16748. character.
  16749. The following addressing modes are understood for XGATE:
  16750. "Inherent"
  16751. ''
  16752. "Immediate 3 Bit Wide"
  16753. '#NUMBER'
  16754. "Immediate 4 Bit Wide"
  16755. '#NUMBER'
  16756. "Immediate 8 Bit Wide"
  16757. '#NUMBER'
  16758. "Monadic Addressing"
  16759. 'REG'
  16760. "Dyadic Addressing"
  16761. 'REG, REG'
  16762. "Triadic Addressing"
  16763. 'REG, REG, REG'
  16764. "Relative Addressing 9 Bit Wide"
  16765. '*SYMBOL'
  16766. "Relative Addressing 10 Bit Wide"
  16767. '*SYMBOL'
  16768. "Index Register plus Immediate Offset"
  16769. 'REG, (REG, #NUMBER)'
  16770. "Index Register plus Register Offset"
  16771. 'REG, REG, REG'
  16772. "Index Register plus Register Offset with Post-increment"
  16773. 'REG, REG, REG+'
  16774. "Index Register plus Register Offset with Pre-decrement"
  16775. 'REG, REG, -REG'
  16776. The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6'
  16777. or 'R7'.
  16778. Convience macro opcodes to deal with 16-bit values have been added.
  16779. "Immediate 16 Bit Wide"
  16780. '#NUMBER', or '*SYMBOL'
  16781. For example:
  16782. ldw R1, #1024
  16783. ldw R3, timer
  16784. ldw R1, (R1, #0)
  16785. COM R1
  16786. stw R2, (R1, #0)
  16787. 
  16788. File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent
  16789. 9.51.3 Assembler Directives
  16790. ---------------------------
  16791. The XGATE version of 'as' have the following specific assembler
  16792. directives:
  16793. 
  16794. File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent
  16795. 9.51.4 Floating Point
  16796. ---------------------
  16797. Packed decimal (P) format floating literals are not supported(yet).
  16798. The floating point formats generated by directives are these.
  16799. '.float'
  16800. 'Single' precision floating point constants.
  16801. '.double'
  16802. 'Double' precision floating point constants.
  16803. '.extend'
  16804. '.ldouble'
  16805. 'Extended' precision ('long double') floating point constants.
  16806. 
  16807. File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent
  16808. 9.51.5 Opcodes
  16809. --------------
  16810. 
  16811. File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies
  16812. 9.52 XStormy16 Dependent Features
  16813. =================================
  16814. * Menu:
  16815. * XStormy16 Syntax:: Syntax
  16816. * XStormy16 Directives:: Machine Directives
  16817. * XStormy16 Opcodes:: Pseudo-Opcodes
  16818. 
  16819. File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent
  16820. 9.52.1 Syntax
  16821. -------------
  16822. * Menu:
  16823. * XStormy16-Chars:: Special Characters
  16824. 
  16825. File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax
  16826. 9.52.1.1 Special Characters
  16827. ...........................
  16828. '#' is the line comment character. If a '#' appears as the first
  16829. character of a line, the whole line is treated as a comment, but in this
  16830. case the line can also be a logical line number directive (*note
  16831. Comments::) or a preprocessor control command (*note Preprocessing::).
  16832. A semicolon (';') can be used to start a comment that extends from
  16833. wherever the character appears on the line up to the end of the line.
  16834. The '|' character can be used to separate statements on the same
  16835. line.
  16836. 
  16837. File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent
  16838. 9.52.2 XStormy16 Machine Directives
  16839. -----------------------------------
  16840. '.16bit_pointers'
  16841. Like the '--16bit-pointers' command line option this directive
  16842. indicates that the assembly code makes use of 16-bit pointers.
  16843. '.32bit_pointers'
  16844. Like the '--32bit-pointers' command line option this directive
  16845. indicates that the assembly code makes use of 32-bit pointers.
  16846. '.no_pointers'
  16847. Like the '--no-pointers' command line option this directive
  16848. indicates that the assembly code does not makes use pointers.
  16849. 
  16850. File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent
  16851. 9.52.3 XStormy16 Pseudo-Opcodes
  16852. -------------------------------
  16853. 'as' implements all the standard XStormy16 opcodes.
  16854. 'as' also implements the following pseudo ops:
  16855. '@lo()'
  16856. Computes the lower 16 bits of the given expression and stores it
  16857. into the immediate operand field of the given instruction. For
  16858. example:
  16859. 'add r6, @lo(here - there)'
  16860. computes the difference between the address of labels 'here' and
  16861. 'there', takes the lower 16 bits of this difference and adds it to
  16862. register 6.
  16863. '@hi()'
  16864. Computes the higher 16 bits of the given expression and stores it
  16865. into the immediate operand field of the given instruction. For
  16866. example:
  16867. 'addc r7, @hi(here - there)'
  16868. computes the difference between the address of labels 'here' and
  16869. 'there', takes the upper 16 bits of this difference, shifts it down
  16870. 16 bits and then adds it, along with the carry bit, to the value in
  16871. register 7.
  16872. 
  16873. File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies
  16874. 9.53 Xtensa Dependent Features
  16875. ==============================
  16876. This chapter covers features of the GNU assembler that are specific to
  16877. the Xtensa architecture. For details about the Xtensa instruction set,
  16878. please consult the 'Xtensa Instruction Set Architecture (ISA) Reference
  16879. Manual'.
  16880. * Menu:
  16881. * Xtensa Options:: Command-line Options.
  16882. * Xtensa Syntax:: Assembler Syntax for Xtensa Processors.
  16883. * Xtensa Optimizations:: Assembler Optimizations.
  16884. * Xtensa Relaxation:: Other Automatic Transformations.
  16885. * Xtensa Directives:: Directives for Xtensa Processors.
  16886. 
  16887. File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent
  16888. 9.53.1 Command Line Options
  16889. ---------------------------
  16890. '--text-section-literals | --no-text-section-literals'
  16891. Control the treatment of literal pools. The default is
  16892. '--no-text-section-literals', which places literals in separate
  16893. sections in the output file. This allows the literal pool to be
  16894. placed in a data RAM/ROM. With '--text-section-literals', the
  16895. literals are interspersed in the text section in order to keep them
  16896. as close as possible to their references. This may be necessary
  16897. for large assembly files, where the literals would otherwise be out
  16898. of range of the 'L32R' instructions in the text section. Literals
  16899. are grouped into pools following '.literal_position' directives or
  16900. preceding 'ENTRY' instructions. These options only affect literals
  16901. referenced via PC-relative 'L32R' instructions; literals for
  16902. absolute mode 'L32R' instructions are handled separately. *Note
  16903. literal: Literal Directive.
  16904. '--auto-litpools | --no-auto-litpools'
  16905. Control the treatment of literal pools. The default is
  16906. '--no-auto-litpools', which in the absence of
  16907. '--text-section-literals' places literals in separate sections in
  16908. the output file. This allows the literal pool to be placed in a
  16909. data RAM/ROM. With '--auto-litpools', the literals are interspersed
  16910. in the text section in order to keep them as close as possible to
  16911. their references, explicit '.literal_position' directives are not
  16912. required. This may be necessary for very large functions, where
  16913. single literal pool at the beginning of the function may not be
  16914. reachable by 'L32R' instructions at the end. These options only
  16915. affect literals referenced via PC-relative 'L32R' instructions;
  16916. literals for absolute mode 'L32R' instructions are handled
  16917. separately. When used together with '--text-section-literals',
  16918. '--auto-litpools' takes precedence. *Note literal: Literal
  16919. Directive.
  16920. '--absolute-literals | --no-absolute-literals'
  16921. Indicate to the assembler whether 'L32R' instructions use absolute
  16922. or PC-relative addressing. If the processor includes the absolute
  16923. addressing option, the default is to use absolute 'L32R'
  16924. relocations. Otherwise, only the PC-relative 'L32R' relocations
  16925. can be used.
  16926. '--target-align | --no-target-align'
  16927. Enable or disable automatic alignment to reduce branch penalties at
  16928. some expense in code size. *Note Automatic Instruction Alignment:
  16929. Xtensa Automatic Alignment. This optimization is enabled by
  16930. default. Note that the assembler will always align instructions
  16931. like 'LOOP' that have fixed alignment requirements.
  16932. '--longcalls | --no-longcalls'
  16933. Enable or disable transformation of call instructions to allow
  16934. calls across a greater range of addresses. *Note Function Call
  16935. Relaxation: Xtensa Call Relaxation. This option should be used
  16936. when call targets can potentially be out of range. It may degrade
  16937. both code size and performance, but the linker can generally
  16938. optimize away the unnecessary overhead when a call ends up within
  16939. range. The default is '--no-longcalls'.
  16940. '--transform | --no-transform'
  16941. Enable or disable all assembler transformations of Xtensa
  16942. instructions, including both relaxation and optimization. The
  16943. default is '--transform'; '--no-transform' should only be used in
  16944. the rare cases when the instructions must be exactly as specified
  16945. in the assembly source. Using '--no-transform' causes out of range
  16946. instruction operands to be errors.
  16947. '--rename-section OLDNAME=NEWNAME'
  16948. Rename the OLDNAME section to NEWNAME. This option can be used
  16949. multiple times to rename multiple sections.
  16950. '--trampolines | --no-trampolines'
  16951. Enable or disable transformation of jump instructions to allow
  16952. jumps across a greater range of addresses. *Note Jump Trampolines:
  16953. Xtensa Jump Relaxation. This option should be used when jump
  16954. targets can potentially be out of range. In the absence of such
  16955. jumps this option does not affect code size or performance. The
  16956. default is '--trampolines'.
  16957. 
  16958. File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent
  16959. 9.53.2 Assembler Syntax
  16960. -----------------------
  16961. Block comments are delimited by '/*' and '*/'. End of line comments may
  16962. be introduced with either '#' or '//'.
  16963. If a '#' appears as the first character of a line then the whole line
  16964. is treated as a comment, but in this case the line could also be a
  16965. logical line number directive (*note Comments::) or a preprocessor
  16966. control command (*note Preprocessing::).
  16967. Instructions consist of a leading opcode or macro name followed by
  16968. whitespace and an optional comma-separated list of operands:
  16969. OPCODE [OPERAND, ...]
  16970. Instructions must be separated by a newline or semicolon (';').
  16971. FLIX instructions, which bundle multiple opcodes together in a single
  16972. instruction, are specified by enclosing the bundled opcodes inside
  16973. braces:
  16974. {
  16975. [FORMAT]
  16976. OPCODE0 [OPERANDS]
  16977. OPCODE1 [OPERANDS]
  16978. OPCODE2 [OPERANDS]
  16979. ...
  16980. }
  16981. The opcodes in a FLIX instruction are listed in the same order as the
  16982. corresponding instruction slots in the TIE format declaration.
  16983. Directives and labels are not allowed inside the braces of a FLIX
  16984. instruction. A particular TIE format name can optionally be specified
  16985. immediately after the opening brace, but this is usually unnecessary.
  16986. The assembler will automatically search for a format that can encode the
  16987. specified opcodes, so the format name need only be specified in rare
  16988. cases where there is more than one applicable format and where it
  16989. matters which of those formats is used. A FLIX instruction can also be
  16990. specified on a single line by separating the opcodes with semicolons:
  16991. { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
  16992. If an opcode can only be encoded in a FLIX instruction but is not
  16993. specified as part of a FLIX bundle, the assembler will choose the
  16994. smallest format where the opcode can be encoded and will fill unused
  16995. instruction slots with no-ops.
  16996. * Menu:
  16997. * Xtensa Opcodes:: Opcode Naming Conventions.
  16998. * Xtensa Registers:: Register Naming.
  16999. 
  17000. File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax
  17001. 9.53.2.1 Opcode Names
  17002. .....................
  17003. See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for
  17004. a complete list of opcodes and descriptions of their semantics.
  17005. If an opcode name is prefixed with an underscore character ('_'),
  17006. 'as' will not transform that instruction in any way. The underscore
  17007. prefix disables both optimization (*note Xtensa Optimizations: Xtensa
  17008. Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
  17009. Relaxation.) for that particular instruction. Only use the underscore
  17010. prefix when it is essential to select the exact opcode produced by the
  17011. assembler. Using this feature unnecessarily makes the code less
  17012. efficient by disabling assembler optimization and less flexible by
  17013. disabling relaxation.
  17014. Note that this special handling of underscore prefixes only applies
  17015. to Xtensa opcodes, not to either built-in macros or user-defined macros.
  17016. When an underscore prefix is used with a macro (e.g., '_MOV'), it refers
  17017. to a different macro. The assembler generally provides built-in macros
  17018. both with and without the underscore prefix, where the underscore
  17019. versions behave as if the underscore carries through to the instructions
  17020. in the macros. For example, '_MOV' may expand to '_MOV.N'.
  17021. The underscore prefix only applies to individual instructions, not to
  17022. series of instructions. For example, if a series of instructions have
  17023. underscore prefixes, the assembler will not transform the individual
  17024. instructions, but it may insert other instructions between them (e.g.,
  17025. to align a 'LOOP' instruction). To prevent the assembler from modifying
  17026. a series of instructions as a whole, use the 'no-transform' directive.
  17027. *Note transform: Transform Directive.
  17028. 
  17029. File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax
  17030. 9.53.2.2 Register Names
  17031. .......................
  17032. The assembly syntax for a register file entry is the "short" name for a
  17033. TIE register file followed by the index into that register file. For
  17034. example, the general-purpose 'AR' register file has a short name of 'a',
  17035. so these registers are named 'a0'...'a15'. As a special feature, 'sp'
  17036. is also supported as a synonym for 'a1'. Additional registers may be
  17037. added by processor configuration options and by designer-defined TIE
  17038. extensions. An initial '$' character is optional in all register names.
  17039. 
  17040. File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent
  17041. 9.53.3 Xtensa Optimizations
  17042. ---------------------------
  17043. The optimizations currently supported by 'as' are generation of density
  17044. instructions where appropriate and automatic branch target alignment.
  17045. * Menu:
  17046. * Density Instructions:: Using Density Instructions.
  17047. * Xtensa Automatic Alignment:: Automatic Instruction Alignment.
  17048. 
  17049. File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations
  17050. 9.53.3.1 Using Density Instructions
  17051. ...................................
  17052. The Xtensa instruction set has a code density option that provides
  17053. 16-bit versions of some of the most commonly used opcodes. Use of these
  17054. opcodes can significantly reduce code size. When possible, the
  17055. assembler automatically translates instructions from the core Xtensa
  17056. instruction set into equivalent instructions from the Xtensa code
  17057. density option. This translation can be disabled by using underscore
  17058. prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
  17059. '--no-transform' command-line option (*note Command Line Options: Xtensa
  17060. Options.), or by using the 'no-transform' directive (*note transform:
  17061. Transform Directive.).
  17062. It is a good idea _not_ to use the density instructions directly.
  17063. The assembler will automatically select dense instructions where
  17064. possible. If you later need to use an Xtensa processor without the code
  17065. density option, the same assembly code will then work without
  17066. modification.
  17067. 
  17068. File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations
  17069. 9.53.3.2 Automatic Instruction Alignment
  17070. ........................................
  17071. The Xtensa assembler will automatically align certain instructions, both
  17072. to optimize performance and to satisfy architectural requirements.
  17073. As an optimization to improve performance, the assembler attempts to
  17074. align branch targets so they do not cross instruction fetch boundaries.
  17075. (Xtensa processors can be configured with either 32-bit or 64-bit
  17076. instruction fetch widths.) An instruction immediately following a call
  17077. is treated as a branch target in this context, because it will be the
  17078. target of a return from the call. This alignment has the potential to
  17079. reduce branch penalties at some expense in code size. This optimization
  17080. is enabled by default. You can disable it with the '--no-target-align'
  17081. command-line option (*note Command Line Options: Xtensa Options.).
  17082. The target alignment optimization is done without adding instructions
  17083. that could increase the execution time of the program. If there are
  17084. density instructions in the code preceding a target, the assembler can
  17085. change the target alignment by widening some of those instructions to
  17086. the equivalent 24-bit instructions. Extra bytes of padding can be
  17087. inserted immediately following unconditional jump and return
  17088. instructions. This approach is usually successful in aligning many, but
  17089. not all, branch targets.
  17090. The 'LOOP' family of instructions must be aligned such that the first
  17091. instruction in the loop body does not cross an instruction fetch
  17092. boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be
  17093. on either a 1 or 2 mod 4 byte boundary). The assembler knows about this
  17094. restriction and inserts the minimal number of 2 or 3 byte no-op
  17095. instructions to satisfy it. When no-op instructions are added, any
  17096. label immediately preceding the original loop will be moved in order to
  17097. refer to the loop instruction, not the newly generated no-op
  17098. instruction. To preserve binary compatibility across processors with
  17099. different fetch widths, the assembler conservatively assumes a 32-bit
  17100. fetch width when aligning 'LOOP' instructions (except if the first
  17101. instruction in the loop is a 64-bit instruction).
  17102. Previous versions of the assembler automatically aligned 'ENTRY'
  17103. instructions to 4-byte boundaries, but that alignment is now the
  17104. programmer's responsibility.
  17105. 
  17106. File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent
  17107. 9.53.4 Xtensa Relaxation
  17108. ------------------------
  17109. When an instruction operand is outside the range allowed for that
  17110. particular instruction field, 'as' can transform the code to use a
  17111. functionally-equivalent instruction or sequence of instructions. This
  17112. process is known as "relaxation". This is typically done for branch
  17113. instructions because the distance of the branch targets is not known
  17114. until assembly-time. The Xtensa assembler offers branch relaxation and
  17115. also extends this concept to function calls, 'MOVI' instructions and
  17116. other instructions with immediate fields.
  17117. * Menu:
  17118. * Xtensa Branch Relaxation:: Relaxation of Branches.
  17119. * Xtensa Call Relaxation:: Relaxation of Function Calls.
  17120. * Xtensa Jump Relaxation:: Relaxation of Jumps.
  17121. * Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields.
  17122. 
  17123. File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation
  17124. 9.53.4.1 Conditional Branch Relaxation
  17125. ......................................
  17126. When the target of a branch is too far away from the branch itself,
  17127. i.e., when the offset from the branch to the target is too large to fit
  17128. in the immediate field of the branch instruction, it may be necessary to
  17129. replace the branch with a branch around a jump. For example,
  17130. beqz a2, L
  17131. may result in:
  17132. bnez.n a2, M
  17133. j L
  17134. M:
  17135. (The 'BNEZ.N' instruction would be used in this example only if the
  17136. density option is available. Otherwise, 'BNEZ' would be used.)
  17137. This relaxation works well because the unconditional jump instruction
  17138. has a much larger offset range than the various conditional branches.
  17139. However, an error will occur if a branch target is beyond the range of a
  17140. jump instruction. 'as' cannot relax unconditional jumps. Similarly, an
  17141. error will occur if the original input contains an unconditional jump to
  17142. a target that is out of range.
  17143. Branch relaxation is enabled by default. It can be disabled by using
  17144. underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
  17145. '--no-transform' command-line option (*note Command Line Options: Xtensa
  17146. Options.), or the 'no-transform' directive (*note transform: Transform
  17147. Directive.).
  17148. 
  17149. File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation
  17150. 9.53.4.2 Function Call Relaxation
  17151. .................................
  17152. Function calls may require relaxation because the Xtensa immediate call
  17153. instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a
  17154. PC-relative offset of only 512 Kbytes in either direction. For larger
  17155. programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4',
  17156. 'CALLX8' and 'CALLX12') where the target address is specified in a
  17157. register. The Xtensa assembler can automatically relax immediate call
  17158. instructions into indirect call instructions. This relaxation is done
  17159. by loading the address of the called function into the callee's return
  17160. address register and then using a 'CALLX' instruction. So, for example:
  17161. call8 func
  17162. might be relaxed to:
  17163. .literal .L1, func
  17164. l32r a8, .L1
  17165. callx8 a8
  17166. Because the addresses of targets of function calls are not generally
  17167. known until link-time, the assembler must assume the worst and relax all
  17168. the calls to functions in other source files, not just those that really
  17169. will be out of range. The linker can recognize calls that were
  17170. unnecessarily relaxed, and it will remove the overhead introduced by the
  17171. assembler for those cases where direct calls are sufficient.
  17172. Call relaxation is disabled by default because it can have a negative
  17173. effect on both code size and performance, although the linker can
  17174. usually eliminate the unnecessary overhead. If a program is too large
  17175. and some of the calls are out of range, function call relaxation can be
  17176. enabled using the '--longcalls' command-line option or the 'longcalls'
  17177. directive (*note longcalls: Longcalls Directive.).
  17178. 
  17179. File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation
  17180. 9.53.4.3 Jump Relaxation
  17181. ........................
  17182. Jump instruction may require relaxation because the Xtensa jump
  17183. instruction ('J') provide a PC-relative offset of only 128 Kbytes in
  17184. either direction. One option is to use jump long ('J.L') instruction,
  17185. which depending on jump distance may be assembled as jump ('J') or
  17186. indirect jump ('JX'). However it needs a free register. When there's
  17187. no spare register it is possible to plant intermediate jump sites
  17188. (trampolines) between the jump instruction and its target. These sites
  17189. may be located in areas unreachable by normal code execution flow, in
  17190. that case they only contain intermediate jumps, or they may be inserted
  17191. in the middle of code block, in which case there's an additional jump
  17192. from the beginning of the trampoline to the instruction past its end.
  17193. So, for example:
  17194. j 1f
  17195. ...
  17196. retw
  17197. ...
  17198. mov a10, a2
  17199. call8 func
  17200. ...
  17201. 1:
  17202. ...
  17203. might be relaxed to:
  17204. j .L0_TR_1
  17205. ...
  17206. retw
  17207. .L0_TR_1:
  17208. j 1f
  17209. ...
  17210. mov a10, a2
  17211. call8 func
  17212. ...
  17213. 1:
  17214. ...
  17215. or to:
  17216. j .L0_TR_1
  17217. ...
  17218. retw
  17219. ...
  17220. mov a10, a2
  17221. j .L0_TR_0
  17222. .L0_TR_1:
  17223. j 1f
  17224. .L0_TR_0:
  17225. call8 func
  17226. ...
  17227. 1:
  17228. ...
  17229. The Xtensa assempler uses trampolines with jump around only when it
  17230. cannot find suitable unreachable trampoline. There may be multiple
  17231. trampolines between the jump instruction and its target.
  17232. This relaxation does not apply to jumps to undefined symbols,
  17233. assuming they will reach their targets once resolved.
  17234. Jump relaxation is enabled by default because it does not affect code
  17235. size or performance while the code itself is small. This relaxation may
  17236. be disabled completely with '--no-trampolines' or '--no-transform'
  17237. command-line options (*note Command Line Options: Xtensa Options.).
  17238. 
  17239. File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation
  17240. 9.53.4.4 Other Immediate Field Relaxation
  17241. .........................................
  17242. The assembler normally performs the following other relaxations. They
  17243. can be disabled by using underscore prefixes (*note Opcode Names: Xtensa
  17244. Opcodes.), the '--no-transform' command-line option (*note Command Line
  17245. Options: Xtensa Options.), or the 'no-transform' directive (*note
  17246. transform: Transform Directive.).
  17247. The 'MOVI' machine instruction can only materialize values in the
  17248. range from -2048 to 2047. Values outside this range are best
  17249. materialized with 'L32R' instructions. Thus:
  17250. movi a0, 100000
  17251. is assembled into the following machine code:
  17252. .literal .L1, 100000
  17253. l32r a0, .L1
  17254. The 'L8UI' machine instruction can only be used with immediate
  17255. offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine
  17256. instructions can only be used with offsets from 0 to 510. The 'L32I'
  17257. machine instruction can only be used with offsets from 0 to 1020. A
  17258. load offset outside these ranges can be materialized with an 'L32R'
  17259. instruction if the destination register of the load is different than
  17260. the source address register. For example:
  17261. l32i a1, a0, 2040
  17262. is translated to:
  17263. .literal .L1, 2040
  17264. l32r a1, .L1
  17265. add a1, a0, a1
  17266. l32i a1, a1, 0
  17267. If the load destination and source address register are the same, an
  17268. out-of-range offset causes an error.
  17269. The Xtensa 'ADDI' instruction only allows immediate operands in the
  17270. range from -128 to 127. There are a number of alternate instruction
  17271. sequences for the 'ADDI' operation. First, if the immediate is 0, the
  17272. 'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR'
  17273. instruction if the code density option is not available). If the 'ADDI'
  17274. immediate is outside of the range -128 to 127, but inside the range
  17275. -32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will
  17276. be used. Finally, if the immediate is outside of this range and a free
  17277. register is available, an 'L32R'/'ADD' sequence will be used with a
  17278. literal allocated from the literal pool.
  17279. For example:
  17280. addi a5, a6, 0
  17281. addi a5, a6, 512
  17282. addi a5, a6, 513
  17283. addi a5, a6, 50000
  17284. is assembled into the following:
  17285. .literal .L1, 50000
  17286. mov.n a5, a6
  17287. addmi a5, a6, 0x200
  17288. addmi a5, a6, 0x200
  17289. addi a5, a5, 1
  17290. l32r a5, .L1
  17291. add a5, a6, a5
  17292. 
  17293. File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent
  17294. 9.53.5 Directives
  17295. -----------------
  17296. The Xtensa assembler supports a region-based directive syntax:
  17297. .begin DIRECTIVE [OPTIONS]
  17298. ...
  17299. .end DIRECTIVE
  17300. All the Xtensa-specific directives that apply to a region of code use
  17301. this syntax.
  17302. The directive applies to code between the '.begin' and the '.end'.
  17303. The state of the option after the '.end' reverts to what it was before
  17304. the '.begin'. A nested '.begin'/'.end' region can further change the
  17305. state of the directive without having to be aware of its outer state.
  17306. For example, consider:
  17307. .begin no-transform
  17308. L: add a0, a1, a2
  17309. .begin transform
  17310. M: add a0, a1, a2
  17311. .end transform
  17312. N: add a0, a1, a2
  17313. .end no-transform
  17314. The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region
  17315. both result in 'ADD' machine instructions, but the assembler selects an
  17316. 'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform'
  17317. region.
  17318. The advantage of this style is that it works well inside macros which
  17319. can preserve the context of their callers.
  17320. The following directives are available:
  17321. * Menu:
  17322. * Schedule Directive:: Enable instruction scheduling.
  17323. * Longcalls Directive:: Use Indirect Calls for Greater Range.
  17324. * Transform Directive:: Disable All Assembler Transformations.
  17325. * Literal Directive:: Intermix Literals with Instructions.
  17326. * Literal Position Directive:: Specify Inline Literal Pool Locations.
  17327. * Literal Prefix Directive:: Specify Literal Section Name Prefix.
  17328. * Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
  17329. 
  17330. File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives
  17331. 9.53.5.1 schedule
  17332. .................
  17333. The 'schedule' directive is recognized only for compatibility with
  17334. Tensilica's assembler.
  17335. .begin [no-]schedule
  17336. .end [no-]schedule
  17337. This directive is ignored and has no effect on 'as'.
  17338. 
  17339. File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives
  17340. 9.53.5.2 longcalls
  17341. ..................
  17342. The 'longcalls' directive enables or disables function call relaxation.
  17343. *Note Function Call Relaxation: Xtensa Call Relaxation.
  17344. .begin [no-]longcalls
  17345. .end [no-]longcalls
  17346. Call relaxation is disabled by default unless the '--longcalls'
  17347. command-line option is specified. The 'longcalls' directive overrides
  17348. the default determined by the command-line options.
  17349. 
  17350. File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives
  17351. 9.53.5.3 transform
  17352. ..................
  17353. This directive enables or disables all assembler transformation,
  17354. including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
  17355. optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
  17356. .begin [no-]transform
  17357. .end [no-]transform
  17358. Transformations are enabled by default unless the '--no-transform'
  17359. option is used. The 'transform' directive overrides the default
  17360. determined by the command-line options. An underscore opcode prefix,
  17361. disabling transformation of that opcode, always takes precedence over
  17362. both directives and command-line flags.
  17363. 
  17364. File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives
  17365. 9.53.5.4 literal
  17366. ................
  17367. The '.literal' directive is used to define literal pool data, i.e.,
  17368. read-only 32-bit data accessed via 'L32R' instructions.
  17369. .literal LABEL, VALUE[, VALUE...]
  17370. This directive is similar to the standard '.word' directive, except
  17371. that the actual location of the literal data is determined by the
  17372. assembler and linker, not by the position of the '.literal' directive.
  17373. Using this directive gives the assembler freedom to locate the literal
  17374. data in the most appropriate place and possibly to combine identical
  17375. literals. For example, the code:
  17376. entry sp, 40
  17377. .literal .L1, sym
  17378. l32r a4, .L1
  17379. can be used to load a pointer to the symbol 'sym' into register 'a4'.
  17380. The value of 'sym' will not be placed between the 'ENTRY' and 'L32R'
  17381. instructions; instead, the assembler puts the data in a literal pool.
  17382. Literal pools are placed by default in separate literal sections;
  17383. however, when using the '--text-section-literals' option (*note Command
  17384. Line Options: Xtensa Options.), the literal pools for PC-relative mode
  17385. 'L32R' instructions are placed in the current section.(1) These text
  17386. section literal pools are created automatically before 'ENTRY'
  17387. instructions and manually after '.literal_position' directives (*note
  17388. literal_position: Literal Position Directive.). If there are no
  17389. preceding 'ENTRY' instructions, explicit '.literal_position' directives
  17390. must be used to place the text section literal pools; otherwise, 'as'
  17391. will report an error.
  17392. When literals are placed in separate sections, the literal section
  17393. names are derived from the names of the sections where the literals are
  17394. defined. The base literal section names are '.literal' for PC-relative
  17395. mode 'L32R' instructions and '.lit4' for absolute mode 'L32R'
  17396. instructions (*note absolute-literals: Absolute Literals Directive.).
  17397. These base names are used for literals defined in the default '.text'
  17398. section. For literals defined in other sections or within the scope of
  17399. a 'literal_prefix' directive (*note literal_prefix: Literal Prefix
  17400. Directive.), the following rules determine the literal section name:
  17401. 1. If the current section is a member of a section group, the literal
  17402. section name includes the group name as a suffix to the base
  17403. '.literal' or '.lit4' name, with a period to separate the base name
  17404. and group name. The literal section is also made a member of the
  17405. group.
  17406. 2. If the current section name (or 'literal_prefix' value) begins with
  17407. "'.gnu.linkonce.KIND.'", the literal section name is formed by
  17408. replacing "'.KIND'" with the base '.literal' or '.lit4' name. For
  17409. example, for literals defined in a section named
  17410. '.gnu.linkonce.t.func', the literal section will be
  17411. '.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'.
  17412. 3. If the current section name (or 'literal_prefix' value) ends with
  17413. '.text', the literal section name is formed by replacing that
  17414. suffix with the base '.literal' or '.lit4' name. For example, for
  17415. literals defined in a section named '.iram0.text', the literal
  17416. section will be '.iram0.literal' or '.iram0.lit4'.
  17417. 4. If none of the preceding conditions apply, the literal section name
  17418. is formed by adding the base '.literal' or '.lit4' name as a suffix
  17419. to the current section name (or 'literal_prefix' value).
  17420. ---------- Footnotes ----------
  17421. (1) Literals for the '.init' and '.fini' sections are always placed
  17422. in separate sections, even when '--text-section-literals' is enabled.
  17423. 
  17424. File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives
  17425. 9.53.5.5 literal_position
  17426. .........................
  17427. When using '--text-section-literals' to place literals inline in the
  17428. section being assembled, the '.literal_position' directive can be used
  17429. to mark a potential location for a literal pool.
  17430. .literal_position
  17431. The '.literal_position' directive is ignored when the
  17432. '--text-section-literals' option is not used or when 'L32R' instructions
  17433. use the absolute addressing mode.
  17434. The assembler will automatically place text section literal pools
  17435. before 'ENTRY' instructions, so the '.literal_position' directive is
  17436. only needed to specify some other location for a literal pool. You may
  17437. need to add an explicit jump instruction to skip over an inline literal
  17438. pool.
  17439. For example, an interrupt vector does not begin with an 'ENTRY'
  17440. instruction so the assembler will be unable to automatically find a good
  17441. place to put a literal pool. Moreover, the code for the interrupt
  17442. vector must be at a specific starting address, so the literal pool
  17443. cannot come before the start of the code. The literal pool for the
  17444. vector must be explicitly positioned in the middle of the vector (before
  17445. any uses of the literals, due to the negative offsets used by
  17446. PC-relative 'L32R' instructions). The '.literal_position' directive can
  17447. be used to do this. In the following code, the literal for 'M' will
  17448. automatically be aligned correctly and is placed after the unconditional
  17449. jump.
  17450. .global M
  17451. code_start:
  17452. j continue
  17453. .literal_position
  17454. .align 4
  17455. continue:
  17456. movi a4, M
  17457. 
  17458. File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives
  17459. 9.53.5.6 literal_prefix
  17460. .......................
  17461. The 'literal_prefix' directive allows you to override the default
  17462. literal section names, which are derived from the names of the sections
  17463. where the literals are defined.
  17464. .begin literal_prefix [NAME]
  17465. .end literal_prefix
  17466. For literals defined within the delimited region, the literal section
  17467. names are derived from the NAME argument instead of the name of the
  17468. current section. The rules used to derive the literal section names do
  17469. not change. *Note literal: Literal Directive. If the NAME argument is
  17470. omitted, the literal sections revert to the defaults. This directive
  17471. has no effect when using the '--text-section-literals' option (*note
  17472. Command Line Options: Xtensa Options.).
  17473. 
  17474. File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives
  17475. 9.53.5.7 absolute-literals
  17476. ..........................
  17477. The 'absolute-literals' and 'no-absolute-literals' directives control
  17478. the absolute vs. PC-relative mode for 'L32R' instructions. These are
  17479. relevant only for Xtensa configurations that include the absolute
  17480. addressing option for 'L32R' instructions.
  17481. .begin [no-]absolute-literals
  17482. .end [no-]absolute-literals
  17483. These directives do not change the 'L32R' mode--they only cause the
  17484. assembler to emit the appropriate kind of relocation for 'L32R'
  17485. instructions and to place the literal values in the appropriate section.
  17486. To change the 'L32R' mode, the program must write the 'LITBASE' special
  17487. register. It is the programmer's responsibility to keep track of the
  17488. mode and indicate to the assembler which mode is used in each region of
  17489. code.
  17490. If the Xtensa configuration includes the absolute 'L32R' addressing
  17491. option, the default is to assume absolute 'L32R' addressing unless the
  17492. '--no-absolute-literals' command-line option is specified. Otherwise,
  17493. the default is to assume PC-relative 'L32R' addressing. The
  17494. 'absolute-literals' directive can then be used to override the default
  17495. determined by the command-line options.
  17496. 
  17497. File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies
  17498. 9.54 Z80 Dependent Features
  17499. ===========================
  17500. * Menu:
  17501. * Z80 Options:: Options
  17502. * Z80 Syntax:: Syntax
  17503. * Z80 Floating Point:: Floating Point
  17504. * Z80 Directives:: Z80 Machine Directives
  17505. * Z80 Opcodes:: Opcodes
  17506. 
  17507. File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent
  17508. 9.54.1 Options
  17509. --------------
  17510. The Zilog Z80 and Ascii R800 version of 'as' have a few machine
  17511. dependent options.
  17512. '-z80'
  17513. Produce code for the Z80 processor. There are additional options
  17514. to request warnings and error messages for undocumented
  17515. instructions.
  17516. '-ignore-undocumented-instructions'
  17517. '-Wnud'
  17518. Silently assemble undocumented Z80-instructions that have been
  17519. adopted as documented R800-instructions.
  17520. '-ignore-unportable-instructions'
  17521. '-Wnup'
  17522. Silently assemble all undocumented Z80-instructions.
  17523. '-warn-undocumented-instructions'
  17524. '-Wud'
  17525. Issue warnings for undocumented Z80-instructions that work on R800,
  17526. do not assemble other undocumented instructions without warning.
  17527. '-warn-unportable-instructions'
  17528. '-Wup'
  17529. Issue warnings for other undocumented Z80-instructions, do not
  17530. treat any undocumented instructions as errors.
  17531. '-forbid-undocumented-instructions'
  17532. '-Fud'
  17533. Treat all undocumented z80-instructions as errors.
  17534. '-forbid-unportable-instructions'
  17535. '-Fup'
  17536. Treat undocumented z80-instructions that do not work on R800 as
  17537. errors.
  17538. '-r800'
  17539. Produce code for the R800 processor. The assembler does not
  17540. support undocumented instructions for the R800. In line with
  17541. common practice, 'as' uses Z80 instruction names for the R800
  17542. processor, as far as they exist.
  17543. 
  17544. File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent
  17545. 9.54.2 Syntax
  17546. -------------
  17547. The assembler syntax closely follows the 'Z80 family CPU User Manual' by
  17548. Zilog. In expressions a single '=' may be used as "is equal to"
  17549. comparison operator.
  17550. Suffices can be used to indicate the radix of integer constants; 'H'
  17551. or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for
  17552. octal, and 'B' for binary.
  17553. The suffix 'b' denotes a backreference to local label.
  17554. * Menu:
  17555. * Z80-Chars:: Special Characters
  17556. * Z80-Regs:: Register Names
  17557. * Z80-Case:: Case Sensitivity
  17558. 
  17559. File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax
  17560. 9.54.2.1 Special Characters
  17561. ...........................
  17562. The semicolon ';' is the line comment character;
  17563. If a '#' appears as the first character of a line then the whole line
  17564. is treated as a comment, but in this case the line could also be a
  17565. logical line number directive (*note Comments::) or a preprocessor
  17566. control command (*note Preprocessing::).
  17567. The Z80 assembler does not support a line separator character.
  17568. The dollar sign '$' can be used as a prefix for hexadecimal numbers
  17569. and as a symbol denoting the current location counter.
  17570. A backslash '\' is an ordinary character for the Z80 assembler.
  17571. The single quote ''' must be followed by a closing quote. If there
  17572. is one character in between, it is a character constant, otherwise it is
  17573. a string constant.
  17574. 
  17575. File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax
  17576. 9.54.2.2 Register Names
  17577. .......................
  17578. The registers are referred to with the letters assigned to them by
  17579. Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and
  17580. most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts
  17581. of 'iy'.
  17582. 
  17583. File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax
  17584. 9.54.2.3 Case Sensitivity
  17585. .........................
  17586. Upper and lower case are equivalent in register names, opcodes,
  17587. condition codes and assembler directives. The case of letters is
  17588. significant in labels and symbol names. The case is also important to
  17589. distinguish the suffix 'b' for a backward reference to a local label
  17590. from the suffix 'B' for a number in binary notation.
  17591. 
  17592. File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent
  17593. 9.54.3 Floating Point
  17594. ---------------------
  17595. Floating-point numbers are not supported.
  17596. 
  17597. File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent
  17598. 9.54.4 Z80 Assembler Directives
  17599. -------------------------------
  17600. 'as' for the Z80 supports some additional directives for compatibility
  17601. with other assemblers.
  17602. These are the additional directives in 'as' for the Z80:
  17603. 'db EXPRESSION|STRING[,EXPRESSION|STRING...]'
  17604. 'defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
  17605. For each STRING the characters are copied to the object file, for
  17606. each other EXPRESSION the value is stored in one byte. A warning
  17607. is issued in case of an overflow.
  17608. 'dw EXPRESSION[,EXPRESSION...]'
  17609. 'defw EXPRESSION[,EXPRESSION...]'
  17610. For each EXPRESSION the value is stored in two bytes, ignoring
  17611. overflow.
  17612. 'd24 EXPRESSION[,EXPRESSION...]'
  17613. 'def24 EXPRESSION[,EXPRESSION...]'
  17614. For each EXPRESSION the value is stored in three bytes, ignoring
  17615. overflow.
  17616. 'd32 EXPRESSION[,EXPRESSION...]'
  17617. 'def32 EXPRESSION[,EXPRESSION...]'
  17618. For each EXPRESSION the value is stored in four bytes, ignoring
  17619. overflow.
  17620. 'ds COUNT[, VALUE]'
  17621. 'defs COUNT[, VALUE]'
  17622. Fill COUNT bytes in the object file with VALUE, if VALUE is omitted
  17623. it defaults to zero.
  17624. 'SYMBOL equ EXPRESSION'
  17625. 'SYMBOL defl EXPRESSION'
  17626. These directives set the value of SYMBOL to EXPRESSION. If 'equ'
  17627. is used, it is an error if SYMBOL is already defined. Symbols
  17628. defined with 'equ' are not protected from redefinition.
  17629. 'set'
  17630. This is a normal instruction on Z80, and not an assembler
  17631. directive.
  17632. 'psect NAME'
  17633. A synonym for *Note Section::, no second argument should be given.
  17634. 
  17635. File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent
  17636. 9.54.5 Opcodes
  17637. --------------
  17638. In line with common practice, Z80 mnemonics are used for both the Z80
  17639. and the R800.
  17640. In many instructions it is possible to use one of the half index
  17641. registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose
  17642. register. This yields instructions that are documented on the R800 and
  17643. undocumented on the Z80. Similarly 'in f,(c)' is documented on the R800
  17644. and undocumented on the Z80.
  17645. The assembler also supports the following undocumented
  17646. Z80-instructions, that have not been adopted in the R800 instruction
  17647. set:
  17648. 'out (c),0'
  17649. Sends zero to the port pointed to by register c.
  17650. 'sli M'
  17651. Equivalent to 'M = (M<<1)+1', the operand M can be any operand that
  17652. is valid for 'sla'. One can use 'sll' as a synonym for 'sli'.
  17653. 'OP (ix+D), R'
  17654. This is equivalent to
  17655. ld R, (ix+D)
  17656. OPC R
  17657. ld (ix+D), R
  17658. The operation 'OPC' may be any of 'res B,', 'set B,', 'rl', 'rlc',
  17659. 'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R'
  17660. may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'.
  17661. 'OPC (iy+D), R'
  17662. As above, but with 'iy' instead of 'ix'.
  17663. The web site at <http://www.z80.info> is a good starting place to
  17664. find more information on programming the Z80.
  17665. 
  17666. File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies
  17667. 9.55 Z8000 Dependent Features
  17668. =============================
  17669. The Z8000 as supports both members of the Z8000 family: the unsegmented
  17670. Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit
  17671. addresses.
  17672. When the assembler is in unsegmented mode (specified with the
  17673. 'unsegm' directive), an address takes up one word (16 bit) sized
  17674. register. When the assembler is in segmented mode (specified with the
  17675. 'segm' directive), a 24-bit address takes up a long (32 bit) register.
  17676. *Note Assembler Directives for the Z8000: Z8000 Directives, for a list
  17677. of other Z8000 specific assembler directives.
  17678. * Menu:
  17679. * Z8000 Options:: Command-line options for the Z8000
  17680. * Z8000 Syntax:: Assembler syntax for the Z8000
  17681. * Z8000 Directives:: Special directives for the Z8000
  17682. * Z8000 Opcodes:: Opcodes
  17683. 
  17684. File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
  17685. 9.55.1 Options
  17686. --------------
  17687. '-z8001'
  17688. Generate segmented code by default.
  17689. '-z8002'
  17690. Generate unsegmented code by default.
  17691. 
  17692. File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
  17693. 9.55.2 Syntax
  17694. -------------
  17695. * Menu:
  17696. * Z8000-Chars:: Special Characters
  17697. * Z8000-Regs:: Register Names
  17698. * Z8000-Addressing:: Addressing Modes
  17699. 
  17700. File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
  17701. 9.55.2.1 Special Characters
  17702. ...........................
  17703. '!' is the line comment character.
  17704. If a '#' appears as the first character of a line then the whole line
  17705. is treated as a comment, but in this case the line could also be a
  17706. logical line number directive (*note Comments::) or a preprocessor
  17707. control command (*note Preprocessing::).
  17708. You can use ';' instead of a newline to separate statements.
  17709. 
  17710. File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
  17711. 9.55.2.2 Register Names
  17712. .......................
  17713. The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
  17714. to different sized groups of registers by register number, with the
  17715. prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for
  17716. 64 bit registers. You can also refer to the contents of the first eight
  17717. (of the sixteen 16 bit registers) by bytes. They are named 'rlN' and
  17718. 'rhN'.
  17719. _byte registers_
  17720. rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
  17721. rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
  17722. _word registers_
  17723. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
  17724. _long word registers_
  17725. rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
  17726. _quad word registers_
  17727. rq0 rq4 rq8 rq12
  17728. 
  17729. File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
  17730. 9.55.2.3 Addressing Modes
  17731. .........................
  17732. as understands the following addressing modes for the Z8000:
  17733. 'rlN'
  17734. 'rhN'
  17735. 'rN'
  17736. 'rrN'
  17737. 'rqN'
  17738. Register direct: 8bit, 16bit, 32bit, and 64bit registers.
  17739. '@rN'
  17740. '@rrN'
  17741. Indirect register: @rrN in segmented mode, @rN in unsegmented mode.
  17742. 'ADDR'
  17743. Direct: the 16 bit or 24 bit address (depending on whether the
  17744. assembler is in segmented or unsegmented mode) of the operand is in
  17745. the instruction.
  17746. 'address(rN)'
  17747. Indexed: the 16 or 24 bit address is added to the 16 bit register
  17748. to produce the final address in memory of the operand.
  17749. 'rN(#IMM)'
  17750. 'rrN(#IMM)'
  17751. Base Address: the 16 or 24 bit register is added to the 16 bit sign
  17752. extended immediate displacement to produce the final address in
  17753. memory of the operand.
  17754. 'rN(rM)'
  17755. 'rrN(rM)'
  17756. Base Index: the 16 or 24 bit register rN or rrN is added to the
  17757. sign extended 16 bit index register rM to produce the final address
  17758. in memory of the operand.
  17759. '#XX'
  17760. Immediate data XX.
  17761. 
  17762. File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
  17763. 9.55.3 Assembler Directives for the Z8000
  17764. -----------------------------------------
  17765. The Z8000 port of as includes additional assembler directives, for
  17766. compatibility with other Z8000 assemblers. These do not begin with '.'
  17767. (unlike the ordinary as directives).
  17768. 'segm'
  17769. '.z8001'
  17770. Generate code for the segmented Z8001.
  17771. 'unsegm'
  17772. '.z8002'
  17773. Generate code for the unsegmented Z8002.
  17774. 'name'
  17775. Synonym for '.file'
  17776. 'global'
  17777. Synonym for '.global'
  17778. 'wval'
  17779. Synonym for '.word'
  17780. 'lval'
  17781. Synonym for '.long'
  17782. 'bval'
  17783. Synonym for '.byte'
  17784. 'sval'
  17785. Assemble a string. 'sval' expects one string literal, delimited by
  17786. single quotes. It assembles each byte of the string into
  17787. consecutive addresses. You can use the escape sequence '%XX'
  17788. (where XX represents a two-digit hexadecimal number) to represent
  17789. the character whose ASCII value is XX. Use this feature to
  17790. describe single quote and other characters that may not appear in
  17791. string literals as themselves. For example, the C statement 'char *a = "he said \"it's 50% off\"";'
  17792. is represented in Z8000 assembly language (shown with the assembler
  17793. output in hex at the left) as
  17794. 68652073 sval 'he said %22it%27s 50%25 off%22%00'
  17795. 61696420
  17796. 22697427
  17797. 73203530
  17798. 25206F66
  17799. 662200
  17800. 'rsect'
  17801. synonym for '.section'
  17802. 'block'
  17803. synonym for '.space'
  17804. 'even'
  17805. special case of '.align'; aligns output to even byte boundary.
  17806. 
  17807. File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
  17808. 9.55.4 Opcodes
  17809. --------------
  17810. For detailed information on the Z8000 machine instruction set, see
  17811. 'Z8000 Technical Manual'.
  17812. The following table summarizes the opcodes and their arguments:
  17813. rs 16 bit source register
  17814. rd 16 bit destination register
  17815. rbs 8 bit source register
  17816. rbd 8 bit destination register
  17817. rrs 32 bit source register
  17818. rrd 32 bit destination register
  17819. rqs 64 bit source register
  17820. rqd 64 bit destination register
  17821. addr 16/24 bit address
  17822. imm immediate data
  17823. adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
  17824. adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
  17825. add rd,@rs clrb rbd dab rbd
  17826. add rd,addr com @rd dbjnz rbd,disp7
  17827. add rd,addr(rs) com addr dec @rd,imm4m1
  17828. add rd,imm16 com addr(rd) dec addr(rd),imm4m1
  17829. add rd,rs com rd dec addr,imm4m1
  17830. addb rbd,@rs comb @rd dec rd,imm4m1
  17831. addb rbd,addr comb addr decb @rd,imm4m1
  17832. addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
  17833. addb rbd,imm8 comb rbd decb addr,imm4m1
  17834. addb rbd,rbs comflg flags decb rbd,imm4m1
  17835. addl rrd,@rs cp @rd,imm16 di i2
  17836. addl rrd,addr cp addr(rd),imm16 div rrd,@rs
  17837. addl rrd,addr(rs) cp addr,imm16 div rrd,addr
  17838. addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
  17839. addl rrd,rrs cp rd,addr div rrd,imm16
  17840. and rd,@rs cp rd,addr(rs) div rrd,rs
  17841. and rd,addr cp rd,imm16 divl rqd,@rs
  17842. and rd,addr(rs) cp rd,rs divl rqd,addr
  17843. and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
  17844. and rd,rs cpb addr(rd),imm8 divl rqd,imm32
  17845. andb rbd,@rs cpb addr,imm8 divl rqd,rrs
  17846. andb rbd,addr cpb rbd,@rs djnz rd,disp7
  17847. andb rbd,addr(rs) cpb rbd,addr ei i2
  17848. andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
  17849. andb rbd,rbs cpb rbd,imm8 ex rd,addr
  17850. bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
  17851. bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
  17852. bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
  17853. bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
  17854. bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
  17855. bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
  17856. bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
  17857. bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
  17858. bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
  17859. bitb rbd,rs cpl rrd,@rs ext8f imm8
  17860. bpt cpl rrd,addr exts rrd
  17861. call @rd cpl rrd,addr(rs) extsb rd
  17862. call addr cpl rrd,imm32 extsl rqd
  17863. call addr(rd) cpl rrd,rrs halt
  17864. calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
  17865. clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
  17866. clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
  17867. clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
  17868. clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
  17869. clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
  17870. inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
  17871. inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
  17872. incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
  17873. incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
  17874. incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
  17875. incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
  17876. ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
  17877. indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
  17878. inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
  17879. inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
  17880. iret ldib @rd,@rs,rr neg addr(rd)
  17881. jp cc,@rd ldir @rd,@rs,rr neg rd
  17882. jp cc,addr ldirb @rd,@rs,rr negb @rd
  17883. jp cc,addr(rd) ldk rd,imm4 negb addr
  17884. jr cc,disp8 ldl @rd,rrs negb addr(rd)
  17885. ld @rd,imm16 ldl addr(rd),rrs negb rbd
  17886. ld @rd,rs ldl addr,rrs nop
  17887. ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
  17888. ld addr(rd),rs ldl rd(rx),rrs or rd,addr
  17889. ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
  17890. ld addr,rs ldl rrd,addr or rd,imm16
  17891. ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
  17892. ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
  17893. ld rd,@rs ldl rrd,rrs orb rbd,addr
  17894. ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
  17895. ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
  17896. ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
  17897. ld rd,rs ldm addr(rd),rs,n out @rd,rs
  17898. ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
  17899. ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
  17900. lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
  17901. lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
  17902. lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
  17903. lda rd,rs(rx) ldps addr outib @rd,@rs,ra
  17904. ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
  17905. ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
  17906. ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
  17907. ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
  17908. ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
  17909. ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
  17910. ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
  17911. ldb rbd,@rs mbit popl addr,@rs
  17912. ldb rbd,addr mreq rd popl rrd,@rs
  17913. ldb rbd,addr(rs) mres push @rd,@rs
  17914. ldb rbd,imm8 mset push @rd,addr
  17915. ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
  17916. ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
  17917. push @rd,rs set addr,imm4 subl rrd,imm32
  17918. pushl @rd,@rs set rd,imm4 subl rrd,rrs
  17919. pushl @rd,addr set rd,rs tcc cc,rd
  17920. pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
  17921. pushl @rd,rrs setb addr(rd),imm4 test @rd
  17922. res @rd,imm4 setb addr,imm4 test addr
  17923. res addr(rd),imm4 setb rbd,imm4 test addr(rd)
  17924. res addr,imm4 setb rbd,rs test rd
  17925. res rd,imm4 setflg imm4 testb @rd
  17926. res rd,rs sinb rbd,imm16 testb addr
  17927. resb @rd,imm4 sinb rd,imm16 testb addr(rd)
  17928. resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
  17929. resb addr,imm4 sindb @rd,@rs,rba testl @rd
  17930. resb rbd,imm4 sinib @rd,@rs,ra testl addr
  17931. resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
  17932. resflg imm4 sla rd,imm8 testl rrd
  17933. ret cc slab rbd,imm8 trdb @rd,@rs,rba
  17934. rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
  17935. rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
  17936. rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
  17937. rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
  17938. rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
  17939. rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
  17940. rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
  17941. rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
  17942. rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
  17943. rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
  17944. rsvd36 sra rd,imm8 tset rd
  17945. rsvd38 srab rbd,imm8 tsetb @rd
  17946. rsvd78 sral rrd,imm8 tsetb addr
  17947. rsvd7e srl rd,imm8 tsetb addr(rd)
  17948. rsvd9d srlb rbd,imm8 tsetb rbd
  17949. rsvd9f srll rrd,imm8 xor rd,@rs
  17950. rsvdb9 sub rd,@rs xor rd,addr
  17951. rsvdbf sub rd,addr xor rd,addr(rs)
  17952. sbc rd,rs sub rd,addr(rs) xor rd,imm16
  17953. sbcb rbd,rbs sub rd,imm16 xor rd,rs
  17954. sc imm8 sub rd,rs xorb rbd,@rs
  17955. sda rd,rs subb rbd,@rs xorb rbd,addr
  17956. sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
  17957. sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
  17958. sdl rd,rs subb rbd,imm8 xorb rbd,rbs
  17959. sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
  17960. sdll rrd,rs subl rrd,@rs
  17961. set @rd,imm4 subl rrd,addr
  17962. set addr(rd),imm4 subl rrd,addr(rs)
  17963. 
  17964. File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
  17965. 10 Reporting Bugs
  17966. *****************
  17967. Your bug reports play an essential role in making 'as' reliable.
  17968. Reporting a bug may help you by bringing a solution to your problem,
  17969. or it may not. But in any case the principal function of a bug report
  17970. is to help the entire community by making the next version of 'as' work
  17971. better. Bug reports are your contribution to the maintenance of 'as'.
  17972. In order for a bug report to serve its purpose, you must include the
  17973. information that enables us to fix the bug.
  17974. * Menu:
  17975. * Bug Criteria:: Have you found a bug?
  17976. * Bug Reporting:: How to report bugs
  17977. 
  17978. File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
  17979. 10.1 Have You Found a Bug?
  17980. ==========================
  17981. If you are not sure whether you have found a bug, here are some
  17982. guidelines:
  17983. * If the assembler gets a fatal signal, for any input whatever, that
  17984. is a 'as' bug. Reliable assemblers never crash.
  17985. * If 'as' produces an error message for valid input, that is a bug.
  17986. * If 'as' does not produce an error message for invalid input, that
  17987. is a bug. However, you should note that your idea of "invalid
  17988. input" might be our idea of "an extension" or "support for
  17989. traditional practice".
  17990. * If you are an experienced user of assemblers, your suggestions for
  17991. improvement of 'as' are welcome in any case.
  17992. 
  17993. File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs
  17994. 10.2 How to Report Bugs
  17995. =======================
  17996. A number of companies and individuals offer support for GNU products.
  17997. If you obtained 'as' from a support organization, we recommend you
  17998. contact that organization first.
  17999. You can find contact information for many support companies and
  18000. individuals in the file 'etc/SERVICE' in the GNU Emacs distribution.
  18001. In any event, we also recommend that you send bug reports for 'as' to
  18002. <http://www.sourceware.org/bugzilla/>.
  18003. The fundamental principle of reporting bugs usefully is this: *report
  18004. all the facts*. If you are not sure whether to state a fact or leave it
  18005. out, state it!
  18006. Often people omit facts because they think they know what causes the
  18007. problem and assume that some details do not matter. Thus, you might
  18008. assume that the name of a symbol you use in an example does not matter.
  18009. Well, probably it does not, but one cannot be sure. Perhaps the bug is
  18010. a stray memory reference which happens to fetch from the location where
  18011. that name is stored in memory; perhaps, if the name were different, the
  18012. contents of that location would fool the assembler into doing the right
  18013. thing despite the bug. Play it safe and give a specific, complete
  18014. example. That is the easiest thing for you to do, and the most helpful.
  18015. Keep in mind that the purpose of a bug report is to enable us to fix
  18016. the bug if it is new to us. Therefore, always write your bug reports on
  18017. the assumption that the bug has not been reported previously.
  18018. Sometimes people give a few sketchy facts and ask, "Does this ring a
  18019. bell?" This cannot help us fix a bug, so it is basically useless. We
  18020. respond by asking for enough details to enable us to investigate. You
  18021. might as well expedite matters by sending them to begin with.
  18022. To enable us to fix the bug, you should include all these things:
  18023. * The version of 'as'. 'as' announces it if you start it with the
  18024. '--version' argument.
  18025. Without this, we will not know whether there is any point in
  18026. looking for the bug in the current version of 'as'.
  18027. * Any patches you may have applied to the 'as' source.
  18028. * The type of machine you are using, and the operating system name
  18029. and version number.
  18030. * What compiler (and its version) was used to compile 'as'--e.g.
  18031. "'gcc-2.7'".
  18032. * The command arguments you gave the assembler to assemble your
  18033. example and observe the bug. To guarantee you will not omit
  18034. something important, list them all. A copy of the Makefile (or the
  18035. output from make) is sufficient.
  18036. If we were to try to guess the arguments, we would probably guess
  18037. wrong and then we might not encounter the bug.
  18038. * A complete input file that will reproduce the bug. If the bug is
  18039. observed when the assembler is invoked via a compiler, send the
  18040. assembler source, not the high level language source. Most
  18041. compilers will produce the assembler source when run with the '-S'
  18042. option. If you are using 'gcc', use the options '-v --save-temps';
  18043. this will save the assembler source in a file with an extension of
  18044. '.s', and also show you exactly how 'as' is being run.
  18045. * A description of what behavior you observe that you believe is
  18046. incorrect. For example, "It gets a fatal signal."
  18047. Of course, if the bug is that 'as' gets a fatal signal, then we
  18048. will certainly notice it. But if the bug is incorrect output, we
  18049. might not notice unless it is glaringly wrong. You might as well
  18050. not give us a chance to make a mistake.
  18051. Even if the problem you experience is a fatal signal, you should
  18052. still say so explicitly. Suppose something strange is going on,
  18053. such as, your copy of 'as' is out of sync, or you have encountered
  18054. a bug in the C library on your system. (This has happened!) Your
  18055. copy might crash and ours would not. If you told us to expect a
  18056. crash, then when ours fails to crash, we would know that the bug
  18057. was not happening for us. If you had not told us to expect a
  18058. crash, then we would not be able to draw any conclusion from our
  18059. observations.
  18060. * If you wish to suggest changes to the 'as' source, send us context
  18061. diffs, as generated by 'diff' with the '-u', '-c', or '-p' option.
  18062. Always send diffs from the old file to the new file. If you even
  18063. discuss something in the 'as' source, refer to it by context, not
  18064. by line number.
  18065. The line numbers in our development sources will not match those in
  18066. your sources. Your line numbers would convey no useful information
  18067. to us.
  18068. Here are some things that are not necessary:
  18069. * A description of the envelope of the bug.
  18070. Often people who encounter a bug spend a lot of time investigating
  18071. which changes to the input file will make the bug go away and which
  18072. changes will not affect it.
  18073. This is often time consuming and not very useful, because the way
  18074. we will find the bug is by running a single example under the
  18075. debugger with breakpoints, not by pure deduction from a series of
  18076. examples. We recommend that you save your time for something else.
  18077. Of course, if you can find a simpler example to report _instead_ of
  18078. the original one, that is a convenience for us. Errors in the
  18079. output will be easier to spot, running under the debugger will take
  18080. less time, and so on.
  18081. However, simplification is not vital; if you do not want to do
  18082. this, report the bug anyway and send us the entire test case you
  18083. used.
  18084. * A patch for the bug.
  18085. A patch for the bug does help us if it is a good one. But do not
  18086. omit the necessary information, such as the test case, on the
  18087. assumption that a patch is all we need. We might see problems with
  18088. your patch and decide to fix the problem another way, or we might
  18089. not understand it at all.
  18090. Sometimes with a program as complicated as 'as' it is very hard to
  18091. construct an example that will make the program follow a certain
  18092. path through the code. If you do not send us the example, we will
  18093. not be able to construct one, so we will not be able to verify that
  18094. the bug is fixed.
  18095. And if we cannot understand what bug you are trying to fix, or why
  18096. your patch should be an improvement, we will not install it. A
  18097. test case will help us to understand.
  18098. * A guess about what the bug is or what it depends on.
  18099. Such guesses are usually wrong. Even we cannot guess right about
  18100. such things without first using the debugger to find the facts.
  18101. 
  18102. File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top
  18103. 11 Acknowledgements
  18104. *******************
  18105. If you have contributed to GAS and your name isn't listed here, it is
  18106. not meant as a slight. We just don't know about it. Send mail to the
  18107. maintainer, and we'll correct the situation. Currently the maintainer
  18108. is Nick Clifton (email address 'nickc@redhat.com').
  18109. Dean Elsner wrote the original GNU assembler for the VAX.(1)
  18110. Jay Fenlason maintained GAS for a while, adding support for
  18111. GDB-specific debug information and the 68k series machines, most of the
  18112. preprocessing pass, and extensive changes in 'messages.c',
  18113. 'input-file.c', 'write.c'.
  18114. K. Richard Pixley maintained GAS for a while, adding various
  18115. enhancements and many bug fixes, including merging support for several
  18116. processors, breaking GAS up to handle multiple object file format back
  18117. ends (including heavy rewrite, testing, an integration of the coff and
  18118. b.out back ends), adding configuration including heavy testing and
  18119. verification of cross assemblers and file splits and renaming, converted
  18120. GAS to strictly ANSI C including full prototypes, added support for
  18121. m680[34]0 and cpu32, did considerable work on i960 including a COFF port
  18122. (including considerable amounts of reverse engineering), a SPARC opcode
  18123. file rewrite, DECstation, rs6000, and hp300hpux host ports, updated
  18124. "know" assertions and made them work, much other reorganization,
  18125. cleanup, and lint.
  18126. Ken Raeburn wrote the high-level BFD interface code to replace most
  18127. of the code in format-specific I/O modules.
  18128. The original VMS support was contributed by David L. Kashtan. Eric
  18129. Youngdale has done much work with it since.
  18130. The Intel 80386 machine description was written by Eliot Dresselhaus.
  18131. Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
  18132. The Motorola 88k machine description was contributed by Devon Bowen
  18133. of Buffalo University and Torbjorn Granlund of the Swedish Institute of
  18134. Computer Science.
  18135. Keith Knowles at the Open Software Foundation wrote the original MIPS
  18136. back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support
  18137. (which hasn't been merged in yet). Ralph Campbell worked with the MIPS
  18138. code to support a.out format.
  18139. Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
  18140. tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
  18141. Steve Chamberlain of Cygnus Support. Steve also modified the COFF back
  18142. end to use BFD for some low-level operations, for use with the H8/300
  18143. and AMD 29k targets.
  18144. John Gilmore built the AMD 29000 support, added '.include' support,
  18145. and simplified the configuration of which versions accept which
  18146. directives. He updated the 68k machine description so that Motorola's
  18147. opcodes always produced fixed-size instructions (e.g., 'jsr'), while
  18148. synthetic instructions remained shrinkable ('jbsr'). John fixed many
  18149. bugs, including true tested cross-compilation support, and one bug in
  18150. relaxation that took a week and required the proverbial one-bit fix.
  18151. Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax
  18152. for the 68k, completed support for some COFF targets (68k, i386 SVR3,
  18153. and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the
  18154. initial RS/6000 and PowerPC assembler, and made a few other minor
  18155. patches.
  18156. Steve Chamberlain made GAS able to generate listings.
  18157. Hewlett-Packard contributed support for the HP9000/300.
  18158. Jeff Law wrote GAS and BFD support for the native HPPA object format
  18159. (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF
  18160. object formats). This work was supported by both the Center for
  18161. Software Science at the University of Utah and Cygnus Support.
  18162. Support for ELF format files has been worked on by Mark Eichin of
  18163. Cygnus Support (original, incomplete implementation for SPARC), Pete
  18164. Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael
  18165. Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn
  18166. of Cygnus Support (sparc, and some initial 64-bit support).
  18167. Linas Vepstas added GAS support for the ESA/390 "IBM 370"
  18168. architecture.
  18169. Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
  18170. GAS and BFD support for openVMS/Alpha.
  18171. Timothy Wall, Michael Hayes, and Greg Smart contributed to the
  18172. various tic* flavors.
  18173. David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
  18174. Tensilica, Inc. added support for Xtensa processors.
  18175. Several engineers at Cygnus Support have also provided many small bug
  18176. fixes and configuration enhancements.
  18177. Jon Beniston added support for the Lattice Mico32 architecture.
  18178. Many others have contributed large or small bugfixes and
  18179. enhancements. If you have contributed significant work and are not
  18180. mentioned on this list, and want to be, let us know. Some of the
  18181. history has been lost; we are not intentionally leaving anyone out.
  18182. ---------- Footnotes ----------
  18183. (1) Any more details?
  18184. 
  18185. File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top
  18186. Appendix A GNU Free Documentation License
  18187. *****************************************
  18188. Version 1.3, 3 November 2008
  18189. Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
  18190. <http://fsf.org/>
  18191. Everyone is permitted to copy and distribute verbatim copies
  18192. of this license document, but changing it is not allowed.
  18193. 0. PREAMBLE
  18194. The purpose of this License is to make a manual, textbook, or other
  18195. functional and useful document "free" in the sense of freedom: to
  18196. assure everyone the effective freedom to copy and redistribute it,
  18197. with or without modifying it, either commercially or
  18198. noncommercially. Secondarily, this License preserves for the
  18199. author and publisher a way to get credit for their work, while not
  18200. being considered responsible for modifications made by others.
  18201. This License is a kind of "copyleft", which means that derivative
  18202. works of the document must themselves be free in the same sense.
  18203. It complements the GNU General Public License, which is a copyleft
  18204. license designed for free software.
  18205. We have designed this License in order to use it for manuals for
  18206. free software, because free software needs free documentation: a
  18207. free program should come with manuals providing the same freedoms
  18208. that the software does. But this License is not limited to
  18209. software manuals; it can be used for any textual work, regardless
  18210. of subject matter or whether it is published as a printed book. We
  18211. recommend this License principally for works whose purpose is
  18212. instruction or reference.
  18213. 1. APPLICABILITY AND DEFINITIONS
  18214. This License applies to any manual or other work, in any medium,
  18215. that contains a notice placed by the copyright holder saying it can
  18216. be distributed under the terms of this License. Such a notice
  18217. grants a world-wide, royalty-free license, unlimited in duration,
  18218. to use that work under the conditions stated herein. The
  18219. "Document", below, refers to any such manual or work. Any member
  18220. of the public is a licensee, and is addressed as "you". You accept
  18221. the license if you copy, modify or distribute the work in a way
  18222. requiring permission under copyright law.
  18223. A "Modified Version" of the Document means any work containing the
  18224. Document or a portion of it, either copied verbatim, or with
  18225. modifications and/or translated into another language.
  18226. A "Secondary Section" is a named appendix or a front-matter section
  18227. of the Document that deals exclusively with the relationship of the
  18228. publishers or authors of the Document to the Document's overall
  18229. subject (or to related matters) and contains nothing that could
  18230. fall directly within that overall subject. (Thus, if the Document
  18231. is in part a textbook of mathematics, a Secondary Section may not
  18232. explain any mathematics.) The relationship could be a matter of
  18233. historical connection with the subject or with related matters, or
  18234. of legal, commercial, philosophical, ethical or political position
  18235. regarding them.
  18236. The "Invariant Sections" are certain Secondary Sections whose
  18237. titles are designated, as being those of Invariant Sections, in the
  18238. notice that says that the Document is released under this License.
  18239. If a section does not fit the above definition of Secondary then it
  18240. is not allowed to be designated as Invariant. The Document may
  18241. contain zero Invariant Sections. If the Document does not identify
  18242. any Invariant Sections then there are none.
  18243. The "Cover Texts" are certain short passages of text that are
  18244. listed, as Front-Cover Texts or Back-Cover Texts, in the notice
  18245. that says that the Document is released under this License. A
  18246. Front-Cover Text may be at most 5 words, and a Back-Cover Text may
  18247. be at most 25 words.
  18248. A "Transparent" copy of the Document means a machine-readable copy,
  18249. represented in a format whose specification is available to the
  18250. general public, that is suitable for revising the document
  18251. straightforwardly with generic text editors or (for images composed
  18252. of pixels) generic paint programs or (for drawings) some widely
  18253. available drawing editor, and that is suitable for input to text
  18254. formatters or for automatic translation to a variety of formats
  18255. suitable for input to text formatters. A copy made in an otherwise
  18256. Transparent file format whose markup, or absence of markup, has
  18257. been arranged to thwart or discourage subsequent modification by
  18258. readers is not Transparent. An image format is not Transparent if
  18259. used for any substantial amount of text. A copy that is not
  18260. "Transparent" is called "Opaque".
  18261. Examples of suitable formats for Transparent copies include plain
  18262. ASCII without markup, Texinfo input format, LaTeX input format,
  18263. SGML or XML using a publicly available DTD, and standard-conforming
  18264. simple HTML, PostScript or PDF designed for human modification.
  18265. Examples of transparent image formats include PNG, XCF and JPG.
  18266. Opaque formats include proprietary formats that can be read and
  18267. edited only by proprietary word processors, SGML or XML for which
  18268. the DTD and/or processing tools are not generally available, and
  18269. the machine-generated HTML, PostScript or PDF produced by some word
  18270. processors for output purposes only.
  18271. The "Title Page" means, for a printed book, the title page itself,
  18272. plus such following pages as are needed to hold, legibly, the
  18273. material this License requires to appear in the title page. For
  18274. works in formats which do not have any title page as such, "Title
  18275. Page" means the text near the most prominent appearance of the
  18276. work's title, preceding the beginning of the body of the text.
  18277. The "publisher" means any person or entity that distributes copies
  18278. of the Document to the public.
  18279. A section "Entitled XYZ" means a named subunit of the Document
  18280. whose title either is precisely XYZ or contains XYZ in parentheses
  18281. following text that translates XYZ in another language. (Here XYZ
  18282. stands for a specific section name mentioned below, such as
  18283. "Acknowledgements", "Dedications", "Endorsements", or "History".)
  18284. To "Preserve the Title" of such a section when you modify the
  18285. Document means that it remains a section "Entitled XYZ" according
  18286. to this definition.
  18287. The Document may include Warranty Disclaimers next to the notice
  18288. which states that this License applies to the Document. These
  18289. Warranty Disclaimers are considered to be included by reference in
  18290. this License, but only as regards disclaiming warranties: any other
  18291. implication that these Warranty Disclaimers may have is void and
  18292. has no effect on the meaning of this License.
  18293. 2. VERBATIM COPYING
  18294. You may copy and distribute the Document in any medium, either
  18295. commercially or noncommercially, provided that this License, the
  18296. copyright notices, and the license notice saying this License
  18297. applies to the Document are reproduced in all copies, and that you
  18298. add no other conditions whatsoever to those of this License. You
  18299. may not use technical measures to obstruct or control the reading
  18300. or further copying of the copies you make or distribute. However,
  18301. you may accept compensation in exchange for copies. If you
  18302. distribute a large enough number of copies you must also follow the
  18303. conditions in section 3.
  18304. You may also lend copies, under the same conditions stated above,
  18305. and you may publicly display copies.
  18306. 3. COPYING IN QUANTITY
  18307. If you publish printed copies (or copies in media that commonly
  18308. have printed covers) of the Document, numbering more than 100, and
  18309. the Document's license notice requires Cover Texts, you must
  18310. enclose the copies in covers that carry, clearly and legibly, all
  18311. these Cover Texts: Front-Cover Texts on the front cover, and
  18312. Back-Cover Texts on the back cover. Both covers must also clearly
  18313. and legibly identify you as the publisher of these copies. The
  18314. front cover must present the full title with all words of the title
  18315. equally prominent and visible. You may add other material on the
  18316. covers in addition. Copying with changes limited to the covers, as
  18317. long as they preserve the title of the Document and satisfy these
  18318. conditions, can be treated as verbatim copying in other respects.
  18319. If the required texts for either cover are too voluminous to fit
  18320. legibly, you should put the first ones listed (as many as fit
  18321. reasonably) on the actual cover, and continue the rest onto
  18322. adjacent pages.
  18323. If you publish or distribute Opaque copies of the Document
  18324. numbering more than 100, you must either include a machine-readable
  18325. Transparent copy along with each Opaque copy, or state in or with
  18326. each Opaque copy a computer-network location from which the general
  18327. network-using public has access to download using public-standard
  18328. network protocols a complete Transparent copy of the Document, free
  18329. of added material. If you use the latter option, you must take
  18330. reasonably prudent steps, when you begin distribution of Opaque
  18331. copies in quantity, to ensure that this Transparent copy will
  18332. remain thus accessible at the stated location until at least one
  18333. year after the last time you distribute an Opaque copy (directly or
  18334. through your agents or retailers) of that edition to the public.
  18335. It is requested, but not required, that you contact the authors of
  18336. the Document well before redistributing any large number of copies,
  18337. to give them a chance to provide you with an updated version of the
  18338. Document.
  18339. 4. MODIFICATIONS
  18340. You may copy and distribute a Modified Version of the Document
  18341. under the conditions of sections 2 and 3 above, provided that you
  18342. release the Modified Version under precisely this License, with the
  18343. Modified Version filling the role of the Document, thus licensing
  18344. distribution and modification of the Modified Version to whoever
  18345. possesses a copy of it. In addition, you must do these things in
  18346. the Modified Version:
  18347. A. Use in the Title Page (and on the covers, if any) a title
  18348. distinct from that of the Document, and from those of previous
  18349. versions (which should, if there were any, be listed in the
  18350. History section of the Document). You may use the same title
  18351. as a previous version if the original publisher of that
  18352. version gives permission.
  18353. B. List on the Title Page, as authors, one or more persons or
  18354. entities responsible for authorship of the modifications in
  18355. the Modified Version, together with at least five of the
  18356. principal authors of the Document (all of its principal
  18357. authors, if it has fewer than five), unless they release you
  18358. from this requirement.
  18359. C. State on the Title page the name of the publisher of the
  18360. Modified Version, as the publisher.
  18361. D. Preserve all the copyright notices of the Document.
  18362. E. Add an appropriate copyright notice for your modifications
  18363. adjacent to the other copyright notices.
  18364. F. Include, immediately after the copyright notices, a license
  18365. notice giving the public permission to use the Modified
  18366. Version under the terms of this License, in the form shown in
  18367. the Addendum below.
  18368. G. Preserve in that license notice the full lists of Invariant
  18369. Sections and required Cover Texts given in the Document's
  18370. license notice.
  18371. H. Include an unaltered copy of this License.
  18372. I. Preserve the section Entitled "History", Preserve its Title,
  18373. and add to it an item stating at least the title, year, new
  18374. authors, and publisher of the Modified Version as given on the
  18375. Title Page. If there is no section Entitled "History" in the
  18376. Document, create one stating the title, year, authors, and
  18377. publisher of the Document as given on its Title Page, then add
  18378. an item describing the Modified Version as stated in the
  18379. previous sentence.
  18380. J. Preserve the network location, if any, given in the Document
  18381. for public access to a Transparent copy of the Document, and
  18382. likewise the network locations given in the Document for
  18383. previous versions it was based on. These may be placed in the
  18384. "History" section. You may omit a network location for a work
  18385. that was published at least four years before the Document
  18386. itself, or if the original publisher of the version it refers
  18387. to gives permission.
  18388. K. For any section Entitled "Acknowledgements" or "Dedications",
  18389. Preserve the Title of the section, and preserve in the section
  18390. all the substance and tone of each of the contributor
  18391. acknowledgements and/or dedications given therein.
  18392. L. Preserve all the Invariant Sections of the Document, unaltered
  18393. in their text and in their titles. Section numbers or the
  18394. equivalent are not considered part of the section titles.
  18395. M. Delete any section Entitled "Endorsements". Such a section
  18396. may not be included in the Modified Version.
  18397. N. Do not retitle any existing section to be Entitled
  18398. "Endorsements" or to conflict in title with any Invariant
  18399. Section.
  18400. O. Preserve any Warranty Disclaimers.
  18401. If the Modified Version includes new front-matter sections or
  18402. appendices that qualify as Secondary Sections and contain no
  18403. material copied from the Document, you may at your option designate
  18404. some or all of these sections as invariant. To do this, add their
  18405. titles to the list of Invariant Sections in the Modified Version's
  18406. license notice. These titles must be distinct from any other
  18407. section titles.
  18408. You may add a section Entitled "Endorsements", provided it contains
  18409. nothing but endorsements of your Modified Version by various
  18410. parties--for example, statements of peer review or that the text
  18411. has been approved by an organization as the authoritative
  18412. definition of a standard.
  18413. You may add a passage of up to five words as a Front-Cover Text,
  18414. and a passage of up to 25 words as a Back-Cover Text, to the end of
  18415. the list of Cover Texts in the Modified Version. Only one passage
  18416. of Front-Cover Text and one of Back-Cover Text may be added by (or
  18417. through arrangements made by) any one entity. If the Document
  18418. already includes a cover text for the same cover, previously added
  18419. by you or by arrangement made by the same entity you are acting on
  18420. behalf of, you may not add another; but you may replace the old
  18421. one, on explicit permission from the previous publisher that added
  18422. the old one.
  18423. The author(s) and publisher(s) of the Document do not by this
  18424. License give permission to use their names for publicity for or to
  18425. assert or imply endorsement of any Modified Version.
  18426. 5. COMBINING DOCUMENTS
  18427. You may combine the Document with other documents released under
  18428. this License, under the terms defined in section 4 above for
  18429. modified versions, provided that you include in the combination all
  18430. of the Invariant Sections of all of the original documents,
  18431. unmodified, and list them all as Invariant Sections of your
  18432. combined work in its license notice, and that you preserve all
  18433. their Warranty Disclaimers.
  18434. The combined work need only contain one copy of this License, and
  18435. multiple identical Invariant Sections may be replaced with a single
  18436. copy. If there are multiple Invariant Sections with the same name
  18437. but different contents, make the title of each such section unique
  18438. by adding at the end of it, in parentheses, the name of the
  18439. original author or publisher of that section if known, or else a
  18440. unique number. Make the same adjustment to the section titles in
  18441. the list of Invariant Sections in the license notice of the
  18442. combined work.
  18443. In the combination, you must combine any sections Entitled
  18444. "History" in the various original documents, forming one section
  18445. Entitled "History"; likewise combine any sections Entitled
  18446. "Acknowledgements", and any sections Entitled "Dedications". You
  18447. must delete all sections Entitled "Endorsements."
  18448. 6. COLLECTIONS OF DOCUMENTS
  18449. You may make a collection consisting of the Document and other
  18450. documents released under this License, and replace the individual
  18451. copies of this License in the various documents with a single copy
  18452. that is included in the collection, provided that you follow the
  18453. rules of this License for verbatim copying of each of the documents
  18454. in all other respects.
  18455. You may extract a single document from such a collection, and
  18456. distribute it individually under this License, provided you insert
  18457. a copy of this License into the extracted document, and follow this
  18458. License in all other respects regarding verbatim copying of that
  18459. document.
  18460. 7. AGGREGATION WITH INDEPENDENT WORKS
  18461. A compilation of the Document or its derivatives with other
  18462. separate and independent documents or works, in or on a volume of a
  18463. storage or distribution medium, is called an "aggregate" if the
  18464. copyright resulting from the compilation is not used to limit the
  18465. legal rights of the compilation's users beyond what the individual
  18466. works permit. When the Document is included in an aggregate, this
  18467. License does not apply to the other works in the aggregate which
  18468. are not themselves derivative works of the Document.
  18469. If the Cover Text requirement of section 3 is applicable to these
  18470. copies of the Document, then if the Document is less than one half
  18471. of the entire aggregate, the Document's Cover Texts may be placed
  18472. on covers that bracket the Document within the aggregate, or the
  18473. electronic equivalent of covers if the Document is in electronic
  18474. form. Otherwise they must appear on printed covers that bracket
  18475. the whole aggregate.
  18476. 8. TRANSLATION
  18477. Translation is considered a kind of modification, so you may
  18478. distribute translations of the Document under the terms of section
  18479. 4. Replacing Invariant Sections with translations requires special
  18480. permission from their copyright holders, but you may include
  18481. translations of some or all Invariant Sections in addition to the
  18482. original versions of these Invariant Sections. You may include a
  18483. translation of this License, and all the license notices in the
  18484. Document, and any Warranty Disclaimers, provided that you also
  18485. include the original English version of this License and the
  18486. original versions of those notices and disclaimers. In case of a
  18487. disagreement between the translation and the original version of
  18488. this License or a notice or disclaimer, the original version will
  18489. prevail.
  18490. If a section in the Document is Entitled "Acknowledgements",
  18491. "Dedications", or "History", the requirement (section 4) to
  18492. Preserve its Title (section 1) will typically require changing the
  18493. actual title.
  18494. 9. TERMINATION
  18495. You may not copy, modify, sublicense, or distribute the Document
  18496. except as expressly provided under this License. Any attempt
  18497. otherwise to copy, modify, sublicense, or distribute it is void,
  18498. and will automatically terminate your rights under this License.
  18499. However, if you cease all violation of this License, then your
  18500. license from a particular copyright holder is reinstated (a)
  18501. provisionally, unless and until the copyright holder explicitly and
  18502. finally terminates your license, and (b) permanently, if the
  18503. copyright holder fails to notify you of the violation by some
  18504. reasonable means prior to 60 days after the cessation.
  18505. Moreover, your license from a particular copyright holder is
  18506. reinstated permanently if the copyright holder notifies you of the
  18507. violation by some reasonable means, this is the first time you have
  18508. received notice of violation of this License (for any work) from
  18509. that copyright holder, and you cure the violation prior to 30 days
  18510. after your receipt of the notice.
  18511. Termination of your rights under this section does not terminate
  18512. the licenses of parties who have received copies or rights from you
  18513. under this License. If your rights have been terminated and not
  18514. permanently reinstated, receipt of a copy of some or all of the
  18515. same material does not give you any rights to use it.
  18516. 10. FUTURE REVISIONS OF THIS LICENSE
  18517. The Free Software Foundation may publish new, revised versions of
  18518. the GNU Free Documentation License from time to time. Such new
  18519. versions will be similar in spirit to the present version, but may
  18520. differ in detail to address new problems or concerns. See
  18521. <http://www.gnu.org/copyleft/>.
  18522. Each version of the License is given a distinguishing version
  18523. number. If the Document specifies that a particular numbered
  18524. version of this License "or any later version" applies to it, you
  18525. have the option of following the terms and conditions either of
  18526. that specified version or of any later version that has been
  18527. published (not as a draft) by the Free Software Foundation. If the
  18528. Document does not specify a version number of this License, you may
  18529. choose any version ever published (not as a draft) by the Free
  18530. Software Foundation. If the Document specifies that a proxy can
  18531. decide which future versions of this License can be used, that
  18532. proxy's public statement of acceptance of a version permanently
  18533. authorizes you to choose that version for the Document.
  18534. 11. RELICENSING
  18535. "Massive Multiauthor Collaboration Site" (or "MMC Site") means any
  18536. World Wide Web server that publishes copyrightable works and also
  18537. provides prominent facilities for anybody to edit those works. A
  18538. public wiki that anybody can edit is an example of such a server.
  18539. A "Massive Multiauthor Collaboration" (or "MMC") contained in the
  18540. site means any set of copyrightable works thus published on the MMC
  18541. site.
  18542. "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
  18543. license published by Creative Commons Corporation, a not-for-profit
  18544. corporation with a principal place of business in San Francisco,
  18545. California, as well as future copyleft versions of that license
  18546. published by that same organization.
  18547. "Incorporate" means to publish or republish a Document, in whole or
  18548. in part, as part of another Document.
  18549. An MMC is "eligible for relicensing" if it is licensed under this
  18550. License, and if all works that were first published under this
  18551. License somewhere other than this MMC, and subsequently
  18552. incorporated in whole or in part into the MMC, (1) had no cover
  18553. texts or invariant sections, and (2) were thus incorporated prior
  18554. to November 1, 2008.
  18555. The operator of an MMC Site may republish an MMC contained in the
  18556. site under CC-BY-SA on the same site at any time before August 1,
  18557. 2009, provided the MMC is eligible for relicensing.
  18558. ADDENDUM: How to use this License for your documents
  18559. ====================================================
  18560. To use this License in a document you have written, include a copy of
  18561. the License in the document and put the following copyright and license
  18562. notices just after the title page:
  18563. Copyright (C) YEAR YOUR NAME.
  18564. Permission is granted to copy, distribute and/or modify this document
  18565. under the terms of the GNU Free Documentation License, Version 1.3
  18566. or any later version published by the Free Software Foundation;
  18567. with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
  18568. Texts. A copy of the license is included in the section entitled ``GNU
  18569. Free Documentation License''.
  18570. If you have Invariant Sections, Front-Cover Texts and Back-Cover
  18571. Texts, replace the "with...Texts." line with this:
  18572. with the Invariant Sections being LIST THEIR TITLES, with
  18573. the Front-Cover Texts being LIST, and with the Back-Cover Texts
  18574. being LIST.
  18575. If you have Invariant Sections without Cover Texts, or some other
  18576. combination of the three, merge those two alternatives to suit the
  18577. situation.
  18578. If your document contains nontrivial examples of program code, we
  18579. recommend releasing these examples in parallel under your choice of free
  18580. software license, such as the GNU General Public License, to permit
  18581. their use in free software.
  18582. 
  18583. File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top
  18584. AS Index
  18585. ********
  18586. �[index�]
  18587. * Menu:
  18588. * ' \"' (doublequote character): Strings. (line 43)
  18589. * ' \b' (backspace character): Strings. (line 15)
  18590. * ' \DDD' (octal character code): Strings. (line 30)
  18591. * ' \f' (formfeed character): Strings. (line 18)
  18592. * ' \n' (newline character): Strings. (line 21)
  18593. * ' \r' (carriage return character): Strings. (line 24)
  18594. * ' \t' (tab): Strings. (line 27)
  18595. * ' \XD...' (hex character code): Strings. (line 36)
  18596. * ' \\' ('\' character): Strings. (line 40)
  18597. * #: Comments. (line 33)
  18598. * #APP: Preprocessing. (line 26)
  18599. * #NO_APP: Preprocessing. (line 26)
  18600. * '$' in symbol names: D10V-Chars. (line 46)
  18601. * '$' in symbol names <1>: D30V-Chars. (line 70)
  18602. * '$' in symbol names <2>: Meta-Chars. (line 10)
  18603. * '$' in symbol names <3>: SH-Chars. (line 15)
  18604. * '$' in symbol names <4>: SH64-Chars. (line 15)
  18605. * '$a': ARM Mapping Symbols.
  18606. (line 9)
  18607. * '$acos' math builtin, TIC54X: TIC54X-Builtins. (line 10)
  18608. * '$asin' math builtin, TIC54X: TIC54X-Builtins. (line 13)
  18609. * '$atan' math builtin, TIC54X: TIC54X-Builtins. (line 16)
  18610. * '$atan2' math builtin, TIC54X: TIC54X-Builtins. (line 19)
  18611. * '$ceil' math builtin, TIC54X: TIC54X-Builtins. (line 22)
  18612. * '$cos' math builtin, TIC54X: TIC54X-Builtins. (line 28)
  18613. * '$cosh' math builtin, TIC54X: TIC54X-Builtins. (line 25)
  18614. * '$cvf' math builtin, TIC54X: TIC54X-Builtins. (line 31)
  18615. * '$cvi' math builtin, TIC54X: TIC54X-Builtins. (line 34)
  18616. * '$d': AArch64 Mapping Symbols.
  18617. (line 12)
  18618. * '$d' <1>: ARM Mapping Symbols.
  18619. (line 15)
  18620. * '$exp' math builtin, TIC54X: TIC54X-Builtins. (line 37)
  18621. * '$fabs' math builtin, TIC54X: TIC54X-Builtins. (line 40)
  18622. * '$firstch' subsym builtin, TIC54X: TIC54X-Macros. (line 26)
  18623. * '$floor' math builtin, TIC54X: TIC54X-Builtins. (line 43)
  18624. * '$fmod' math builtin, TIC54X: TIC54X-Builtins. (line 47)
  18625. * '$int' math builtin, TIC54X: TIC54X-Builtins. (line 50)
  18626. * '$iscons' subsym builtin, TIC54X: TIC54X-Macros. (line 43)
  18627. * '$isdefed' subsym builtin, TIC54X: TIC54X-Macros. (line 34)
  18628. * '$ismember' subsym builtin, TIC54X: TIC54X-Macros. (line 38)
  18629. * '$isname' subsym builtin, TIC54X: TIC54X-Macros. (line 47)
  18630. * '$isreg' subsym builtin, TIC54X: TIC54X-Macros. (line 50)
  18631. * '$lastch' subsym builtin, TIC54X: TIC54X-Macros. (line 30)
  18632. * '$ldexp' math builtin, TIC54X: TIC54X-Builtins. (line 53)
  18633. * '$log' math builtin, TIC54X: TIC54X-Builtins. (line 59)
  18634. * '$log10' math builtin, TIC54X: TIC54X-Builtins. (line 56)
  18635. * '$max' math builtin, TIC54X: TIC54X-Builtins. (line 62)
  18636. * '$min' math builtin, TIC54X: TIC54X-Builtins. (line 65)
  18637. * '$pow' math builtin, TIC54X: TIC54X-Builtins. (line 68)
  18638. * '$round' math builtin, TIC54X: TIC54X-Builtins. (line 71)
  18639. * '$sgn' math builtin, TIC54X: TIC54X-Builtins. (line 74)
  18640. * '$sin' math builtin, TIC54X: TIC54X-Builtins. (line 77)
  18641. * '$sinh' math builtin, TIC54X: TIC54X-Builtins. (line 80)
  18642. * '$sqrt' math builtin, TIC54X: TIC54X-Builtins. (line 83)
  18643. * '$structacc' subsym builtin, TIC54X: TIC54X-Macros. (line 57)
  18644. * '$structsz' subsym builtin, TIC54X: TIC54X-Macros. (line 54)
  18645. * '$symcmp' subsym builtin, TIC54X: TIC54X-Macros. (line 23)
  18646. * '$symlen' subsym builtin, TIC54X: TIC54X-Macros. (line 20)
  18647. * '$t': ARM Mapping Symbols.
  18648. (line 12)
  18649. * '$tan' math builtin, TIC54X: TIC54X-Builtins. (line 86)
  18650. * '$tanh' math builtin, TIC54X: TIC54X-Builtins. (line 89)
  18651. * '$trunc' math builtin, TIC54X: TIC54X-Builtins. (line 92)
  18652. * '$x': AArch64 Mapping Symbols.
  18653. (line 9)
  18654. * %gp: RX-Modifiers. (line 6)
  18655. * '%gpreg': RX-Modifiers. (line 22)
  18656. * '%pidreg': RX-Modifiers. (line 25)
  18657. * '-+' option, VAX/VMS: VAX-Opts. (line 71)
  18658. * --: Command Line. (line 10)
  18659. * '--32' option, i386: i386-Options. (line 8)
  18660. * '--32' option, x86-64: i386-Options. (line 8)
  18661. * '--64' option, i386: i386-Options. (line 8)
  18662. * '--64' option, x86-64: i386-Options. (line 8)
  18663. * --absolute-literals: Xtensa Options. (line 39)
  18664. * --allow-reg-prefix: SH Options. (line 9)
  18665. * --alternate: alternate. (line 6)
  18666. * --auto-litpools: Xtensa Options. (line 22)
  18667. * '--base-size-default-16': M68K-Opts. (line 66)
  18668. * '--base-size-default-32': M68K-Opts. (line 66)
  18669. * --big: SH Options. (line 9)
  18670. * '--bitwise-or' option, M680x0: M68K-Opts. (line 59)
  18671. * '--compress-debug-sections=' option: Overview. (line 346)
  18672. * '--disp-size-default-16': M68K-Opts. (line 75)
  18673. * '--disp-size-default-32': M68K-Opts. (line 75)
  18674. * '--divide' option, i386: i386-Options. (line 24)
  18675. * --dsp: SH Options. (line 9)
  18676. * '--emulation=crisaout' command line option, CRIS: CRIS-Opts.
  18677. (line 9)
  18678. * '--emulation=criself' command line option, CRIS: CRIS-Opts.
  18679. (line 9)
  18680. * --enforce-aligned-data: Sparc-Aligned-Data. (line 11)
  18681. * --fatal-warnings: W. (line 16)
  18682. * --fdpic: SH Options. (line 31)
  18683. * '--fix-v4bx' command line option, ARM: ARM Options. (line 192)
  18684. * '--fixed-special-register-names' command line option, MMIX: MMIX-Opts.
  18685. (line 8)
  18686. * '--force-long-branches': M68HC11-Opts. (line 81)
  18687. * '--generate-example': M68HC11-Opts. (line 98)
  18688. * '--globalize-symbols' command line option, MMIX: MMIX-Opts.
  18689. (line 12)
  18690. * '--gnu-syntax' command line option, MMIX: MMIX-Opts. (line 16)
  18691. * '--linker-allocated-gregs' command line option, MMIX: MMIX-Opts.
  18692. (line 67)
  18693. * --listing-cont-lines: listing. (line 34)
  18694. * --listing-lhs-width: listing. (line 16)
  18695. * --listing-lhs-width2: listing. (line 21)
  18696. * --listing-rhs-width: listing. (line 28)
  18697. * --little: SH Options. (line 9)
  18698. * --longcalls: Xtensa Options. (line 53)
  18699. * '--march=ARCHITECTURE' command line option, CRIS: CRIS-Opts.
  18700. (line 34)
  18701. * --MD: MD. (line 6)
  18702. * '--mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63)
  18703. * --no-absolute-literals: Xtensa Options. (line 39)
  18704. * --no-auto-litpools: Xtensa Options. (line 22)
  18705. * '--no-expand' command line option, MMIX: MMIX-Opts. (line 31)
  18706. * --no-longcalls: Xtensa Options. (line 53)
  18707. * '--no-merge-gregs' command line option, MMIX: MMIX-Opts. (line 36)
  18708. * '--no-mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63)
  18709. * --no-pad-sections: no-pad-sections. (line 6)
  18710. * '--no-predefined-syms' command line option, MMIX: MMIX-Opts.
  18711. (line 22)
  18712. * '--no-pushj-stubs' command line option, MMIX: MMIX-Opts. (line 54)
  18713. * '--no-stubs' command line option, MMIX: MMIX-Opts. (line 54)
  18714. * --no-target-align: Xtensa Options. (line 46)
  18715. * --no-text-section-literals: Xtensa Options. (line 7)
  18716. * --no-trampolines: Xtensa Options. (line 74)
  18717. * --no-transform: Xtensa Options. (line 62)
  18718. * '--no-underscore' command line option, CRIS: CRIS-Opts. (line 15)
  18719. * --no-warn: W. (line 11)
  18720. * '--pcrel': M68K-Opts. (line 87)
  18721. * '--pic' command line option, CRIS: CRIS-Opts. (line 27)
  18722. * '--print-insn-syntax': M68HC11-Opts. (line 87)
  18723. * '--print-insn-syntax' <1>: XGATE-Opts. (line 25)
  18724. * '--print-opcodes': M68HC11-Opts. (line 91)
  18725. * '--print-opcodes' <1>: XGATE-Opts. (line 29)
  18726. * '--register-prefix-optional' option, M680x0: M68K-Opts. (line 46)
  18727. * --relax: SH Options. (line 9)
  18728. * '--relax' command line option, MMIX: MMIX-Opts. (line 19)
  18729. * --rename-section: Xtensa Options. (line 70)
  18730. * --renesas: SH Options. (line 9)
  18731. * --sectname-subst: Section. (line 71)
  18732. * '--short-branches': M68HC11-Opts. (line 67)
  18733. * --small: SH Options. (line 9)
  18734. * --statistics: statistics. (line 6)
  18735. * '--strict-direct-mode': M68HC11-Opts. (line 57)
  18736. * --target-align: Xtensa Options. (line 46)
  18737. * --text-section-literals: Xtensa Options. (line 7)
  18738. * --traditional-format: traditional-format. (line 6)
  18739. * --trampolines: Xtensa Options. (line 74)
  18740. * --transform: Xtensa Options. (line 62)
  18741. * '--underscore' command line option, CRIS: CRIS-Opts. (line 15)
  18742. * --warn: W. (line 19)
  18743. * '--x32' option, i386: i386-Options. (line 8)
  18744. * '--x32' option, x86-64: i386-Options. (line 8)
  18745. * '--xgate-ramoffset': M68HC11-Opts. (line 36)
  18746. * '-1' option, VAX/VMS: VAX-Opts. (line 77)
  18747. * '-32addr' command line option, Alpha: Alpha Options. (line 57)
  18748. * -a: a. (line 6)
  18749. * '-A' options, i960: Options-i960. (line 6)
  18750. * -ac: a. (line 6)
  18751. * -ad: a. (line 6)
  18752. * -ag: a. (line 6)
  18753. * -ah: a. (line 6)
  18754. * -al: a. (line 6)
  18755. * -Aleon: Sparc-Opts. (line 25)
  18756. * -an: a. (line 6)
  18757. * -as: a. (line 6)
  18758. * -Asparc: Sparc-Opts. (line 25)
  18759. * -Asparcfmaf: Sparc-Opts. (line 25)
  18760. * -Asparcima: Sparc-Opts. (line 25)
  18761. * -Asparclet: Sparc-Opts. (line 25)
  18762. * -Asparclite: Sparc-Opts. (line 25)
  18763. * -Asparcvis: Sparc-Opts. (line 25)
  18764. * -Asparcvis2: Sparc-Opts. (line 25)
  18765. * -Asparcvis3: Sparc-Opts. (line 25)
  18766. * -Asparcvis3r: Sparc-Opts. (line 25)
  18767. * -Av6: Sparc-Opts. (line 25)
  18768. * -Av7: Sparc-Opts. (line 25)
  18769. * -Av8: Sparc-Opts. (line 25)
  18770. * -Av9: Sparc-Opts. (line 25)
  18771. * -Av9a: Sparc-Opts. (line 25)
  18772. * -Av9b: Sparc-Opts. (line 25)
  18773. * -Av9c: Sparc-Opts. (line 25)
  18774. * -Av9d: Sparc-Opts. (line 25)
  18775. * -Av9e: Sparc-Opts. (line 25)
  18776. * -Av9m: Sparc-Opts. (line 25)
  18777. * -Av9v: Sparc-Opts. (line 25)
  18778. * '-b' option, i960: Options-i960. (line 22)
  18779. * '-big' option, M32R: M32R-Opts. (line 35)
  18780. * -D: D. (line 6)
  18781. * '-D', ignored on VAX: VAX-Opts. (line 11)
  18782. * '-d', VAX option: VAX-Opts. (line 16)
  18783. * '-eabi=' command line option, ARM: ARM Options. (line 168)
  18784. * '-EB' command line option, AArch64: AArch64 Options. (line 6)
  18785. * '-EB' command line option, ARC: ARC Options. (line 84)
  18786. * '-EB' command line option, ARM: ARM Options. (line 173)
  18787. * '-EB' option (MIPS): MIPS Options. (line 13)
  18788. * '-EB' option, M32R: M32R-Opts. (line 39)
  18789. * '-EB' option, TILE-Gx: TILE-Gx Options. (line 11)
  18790. * '-EL' command line option, AArch64: AArch64 Options. (line 10)
  18791. * '-EL' command line option, ARC: ARC Options. (line 88)
  18792. * '-EL' command line option, ARM: ARM Options. (line 184)
  18793. * '-EL' option (MIPS): MIPS Options. (line 13)
  18794. * '-EL' option, M32R: M32R-Opts. (line 32)
  18795. * '-EL' option, TILE-Gx: TILE-Gx Options. (line 11)
  18796. * -f: f. (line 6)
  18797. * '-F' command line option, Alpha: Alpha Options. (line 57)
  18798. * '-fno-pic' option, RISC-V: RISC-V-Opts. (line 11)
  18799. * '-fpic' option, RISC-V: RISC-V-Opts. (line 8)
  18800. * '-g' command line option, Alpha: Alpha Options. (line 47)
  18801. * '-G' command line option, Alpha: Alpha Options. (line 53)
  18802. * '-G' option (MIPS): MIPS Options. (line 8)
  18803. * '-h' option, VAX/VMS: VAX-Opts. (line 45)
  18804. * '-H' option, VAX/VMS: VAX-Opts. (line 81)
  18805. * -I PATH: I. (line 6)
  18806. * '-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 87)
  18807. * '-Ip' option, M32RX: M32R-Opts. (line 97)
  18808. * '-J', ignored on VAX: VAX-Opts. (line 27)
  18809. * -K: K. (line 6)
  18810. * '-k' command line option, ARM: ARM Options. (line 188)
  18811. * '-KPIC' option, M32R: M32R-Opts. (line 42)
  18812. * '-KPIC' option, MIPS: MIPS Options. (line 21)
  18813. * -L: L. (line 6)
  18814. * '-l' option, M680x0: M68K-Opts. (line 34)
  18815. * '-little' option, M32R: M32R-Opts. (line 27)
  18816. * -M: M. (line 6)
  18817. * -m11/03: PDP-11-Options. (line 140)
  18818. * -m11/04: PDP-11-Options. (line 143)
  18819. * -m11/05: PDP-11-Options. (line 146)
  18820. * -m11/10: PDP-11-Options. (line 146)
  18821. * -m11/15: PDP-11-Options. (line 149)
  18822. * -m11/20: PDP-11-Options. (line 149)
  18823. * -m11/21: PDP-11-Options. (line 152)
  18824. * -m11/23: PDP-11-Options. (line 155)
  18825. * -m11/24: PDP-11-Options. (line 155)
  18826. * -m11/34: PDP-11-Options. (line 158)
  18827. * -m11/34a: PDP-11-Options. (line 161)
  18828. * -m11/35: PDP-11-Options. (line 164)
  18829. * -m11/40: PDP-11-Options. (line 164)
  18830. * -m11/44: PDP-11-Options. (line 167)
  18831. * -m11/45: PDP-11-Options. (line 170)
  18832. * -m11/50: PDP-11-Options. (line 170)
  18833. * -m11/53: PDP-11-Options. (line 173)
  18834. * -m11/55: PDP-11-Options. (line 170)
  18835. * -m11/60: PDP-11-Options. (line 176)
  18836. * -m11/70: PDP-11-Options. (line 170)
  18837. * -m11/73: PDP-11-Options. (line 173)
  18838. * -m11/83: PDP-11-Options. (line 173)
  18839. * -m11/84: PDP-11-Options. (line 173)
  18840. * -m11/93: PDP-11-Options. (line 173)
  18841. * -m11/94: PDP-11-Options. (line 173)
  18842. * '-m16c' option, M16C: M32C-Opts. (line 12)
  18843. * '-m31' option, s390: s390 Options. (line 8)
  18844. * '-m32' option, TILE-Gx: TILE-Gx Options. (line 8)
  18845. * '-m32bit-doubles': RX-Opts. (line 9)
  18846. * '-m32c' option, M32C: M32C-Opts. (line 9)
  18847. * '-m32r' option, M32R: M32R-Opts. (line 21)
  18848. * '-m32rx' option, M32R2: M32R-Opts. (line 17)
  18849. * '-m32rx' option, M32RX: M32R-Opts. (line 9)
  18850. * '-m4byte-align' command line option, V850: V850 Options. (line 90)
  18851. * '-m64' option, s390: s390 Options. (line 8)
  18852. * '-m64' option, TILE-Gx: TILE-Gx Options. (line 8)
  18853. * '-m64bit-doubles': RX-Opts. (line 15)
  18854. * '-m68000' and related options: M68K-Opts. (line 99)
  18855. * '-m68hc11': M68HC11-Opts. (line 9)
  18856. * '-m68hc12': M68HC11-Opts. (line 14)
  18857. * '-m68hcs12': M68HC11-Opts. (line 21)
  18858. * '-m8byte-align' command line option, V850: V850 Options. (line 86)
  18859. * '-mabi=' command line option, AArch64: AArch64 Options. (line 14)
  18860. * '-mabi=ABI' option, RISC-V: RISC-V-Opts. (line 18)
  18861. * '-madd-bnd-prefix' option, i386: i386-Options. (line 134)
  18862. * '-madd-bnd-prefix' option, x86-64: i386-Options. (line 134)
  18863. * -mall: PDP-11-Options. (line 26)
  18864. * '-mall-enabled' command line option, LM32: LM32 Options. (line 30)
  18865. * -mall-extensions: PDP-11-Options. (line 26)
  18866. * '-mall-opcodes' command line option, AVR: AVR Options. (line 108)
  18867. * '-mamd64' option, x86-64: i386-Options. (line 190)
  18868. * '-mapcs-26' command line option, ARM: ARM Options. (line 140)
  18869. * '-mapcs-32' command line option, ARM: ARM Options. (line 140)
  18870. * '-mapcs-float' command line option, ARM: ARM Options. (line 154)
  18871. * '-mapcs-reentrant' command line option, ARM: ARM Options. (line 159)
  18872. * '-march=' command line option, AArch64: AArch64 Options. (line 39)
  18873. * '-march=' command line option, ARM: ARM Options. (line 74)
  18874. * '-march=' command line option, M680x0: M68K-Opts. (line 8)
  18875. * '-march=' command line option, TIC6X: TIC6X Options. (line 6)
  18876. * '-march=' option, i386: i386-Options. (line 31)
  18877. * '-march=' option, s390: s390 Options. (line 25)
  18878. * '-march=' option, x86-64: i386-Options. (line 31)
  18879. * '-march=ISA' option, RISC-V: RISC-V-Opts. (line 14)
  18880. * '-matpcs' command line option, ARM: ARM Options. (line 146)
  18881. * '-mavxscalar=' option, i386: i386-Options. (line 92)
  18882. * '-mavxscalar=' option, x86-64: i386-Options. (line 92)
  18883. * '-mbarrel-shift-enabled' command line option, LM32: LM32 Options.
  18884. (line 12)
  18885. * '-mbig-endian': RX-Opts. (line 20)
  18886. * '-mbig-obj' option, x86-64: i386-Options. (line 148)
  18887. * '-mbreak-enabled' command line option, LM32: LM32 Options. (line 27)
  18888. * '-mccs' command line option, ARM: ARM Options. (line 201)
  18889. * -mcis: PDP-11-Options. (line 32)
  18890. * '-mcode-density' command line option, ARC: ARC Options. (line 93)
  18891. * '-mconstant-gp' command line option, IA-64: IA-64 Options. (line 6)
  18892. * '-mCPU' command line option, Alpha: Alpha Options. (line 6)
  18893. * '-mcpu' option, cpu: TIC54X-Opts. (line 15)
  18894. * '-mcpu=': RX-Opts. (line 75)
  18895. * '-mcpu=' command line option, AArch64: AArch64 Options. (line 19)
  18896. * '-mcpu=' command line option, ARM: ARM Options. (line 6)
  18897. * '-mcpu=' command line option, Blackfin: Blackfin Options. (line 6)
  18898. * '-mcpu=' command line option, M680x0: M68K-Opts. (line 14)
  18899. * '-mcpu=CPU' command line option, ARC: ARC Options. (line 10)
  18900. * -mcsm: PDP-11-Options. (line 43)
  18901. * '-mdcache-enabled' command line option, LM32: LM32 Options.
  18902. (line 24)
  18903. * '-mdebug' command line option, Alpha: Alpha Options. (line 25)
  18904. * '-mdivide-enabled' command line option, LM32: LM32 Options.
  18905. (line 9)
  18906. * '-mdpfp' command line option, ARC: ARC Options. (line 108)
  18907. * '-mdsbt' command line option, TIC6X: TIC6X Options. (line 13)
  18908. * '-me' option, stderr redirect: TIC54X-Opts. (line 20)
  18909. * -meis: PDP-11-Options. (line 46)
  18910. * '-mepiphany' command line option, Epiphany: Epiphany Options.
  18911. (line 9)
  18912. * '-mepiphany16' command line option, Epiphany: Epiphany Options.
  18913. (line 13)
  18914. * '-merrors-to-file' option, stderr redirect: TIC54X-Opts. (line 20)
  18915. * '-mesa' option, s390: s390 Options. (line 17)
  18916. * '-mevexlig=' option, i386: i386-Options. (line 100)
  18917. * '-mevexlig=' option, x86-64: i386-Options. (line 100)
  18918. * '-mevexrcig=' option, i386: i386-Options. (line 180)
  18919. * '-mevexrcig=' option, x86-64: i386-Options. (line 180)
  18920. * '-mevexwig=' option, i386: i386-Options. (line 110)
  18921. * '-mevexwig=' option, x86-64: i386-Options. (line 110)
  18922. * '-mf' option, far-mode: TIC54X-Opts. (line 8)
  18923. * -mf11: PDP-11-Options. (line 122)
  18924. * '-mfar-mode' option, far-mode: TIC54X-Opts. (line 8)
  18925. * '-mfdpic' command line option, Blackfin: Blackfin Options. (line 19)
  18926. * '-mfence-as-lock-add=' option, i386: i386-Options. (line 161)
  18927. * '-mfence-as-lock-add=' option, x86-64: i386-Options. (line 161)
  18928. * -mfis: PDP-11-Options. (line 51)
  18929. * '-mfloat-abi=' command line option, ARM: ARM Options. (line 163)
  18930. * -mfp-11: PDP-11-Options. (line 56)
  18931. * -mfpp: PDP-11-Options. (line 56)
  18932. * -mfpu: PDP-11-Options. (line 56)
  18933. * '-mfpu=' command line option, ARM: ARM Options. (line 91)
  18934. * '-mfpuda' command line option, ARC: ARC Options. (line 111)
  18935. * '-mgcc-abi': RX-Opts. (line 63)
  18936. * '-mgcc-abi' command line option, V850: V850 Options. (line 79)
  18937. * '-mhard-float' command line option, V850: V850 Options. (line 101)
  18938. * '-micache-enabled' command line option, LM32: LM32 Options.
  18939. (line 21)
  18940. * '-mimplicit-it' command line option, ARM: ARM Options. (line 124)
  18941. * '-mint-register': RX-Opts. (line 57)
  18942. * '-mintel64' option, x86-64: i386-Options. (line 190)
  18943. * '-mip2022' option, IP2K: IP2K-Opts. (line 14)
  18944. * '-mip2022ext' option, IP2022: IP2K-Opts. (line 9)
  18945. * -mj11: PDP-11-Options. (line 126)
  18946. * -mka11: PDP-11-Options. (line 92)
  18947. * -mkb11: PDP-11-Options. (line 95)
  18948. * -mkd11a: PDP-11-Options. (line 98)
  18949. * -mkd11b: PDP-11-Options. (line 101)
  18950. * -mkd11d: PDP-11-Options. (line 104)
  18951. * -mkd11e: PDP-11-Options. (line 107)
  18952. * -mkd11f: PDP-11-Options. (line 110)
  18953. * -mkd11h: PDP-11-Options. (line 110)
  18954. * -mkd11k: PDP-11-Options. (line 114)
  18955. * -mkd11q: PDP-11-Options. (line 110)
  18956. * -mkd11z: PDP-11-Options. (line 118)
  18957. * -mkev11: PDP-11-Options. (line 51)
  18958. * -mkev11 <1>: PDP-11-Options. (line 51)
  18959. * -mlimited-eis: PDP-11-Options. (line 64)
  18960. * '-mlink-relax' command line option, AVR: AVR Options. (line 120)
  18961. * '-mlittle-endian': RX-Opts. (line 26)
  18962. * '-mlong': M68HC11-Opts. (line 45)
  18963. * '-mlong' <1>: XGATE-Opts. (line 13)
  18964. * '-mlong-double': M68HC11-Opts. (line 53)
  18965. * '-mlong-double' <1>: XGATE-Opts. (line 21)
  18966. * '-mm9s12x': M68HC11-Opts. (line 27)
  18967. * '-mm9s12xg': M68HC11-Opts. (line 32)
  18968. * '-mmcu=' command line option, AVR: AVR Options. (line 6)
  18969. * -mmfpt: PDP-11-Options. (line 70)
  18970. * -mmicrocode: PDP-11-Options. (line 83)
  18971. * '-mmnemonic=' option, i386: i386-Options. (line 117)
  18972. * '-mmnemonic=' option, x86-64: i386-Options. (line 117)
  18973. * '-mmultiply-enabled' command line option, LM32: LM32 Options.
  18974. (line 6)
  18975. * -mmutiproc: PDP-11-Options. (line 73)
  18976. * -mmxps: PDP-11-Options. (line 77)
  18977. * '-mnaked-reg' option, i386: i386-Options. (line 129)
  18978. * '-mnaked-reg' option, x86-64: i386-Options. (line 129)
  18979. * '-mnan=' command line option, MIPS: MIPS Options. (line 379)
  18980. * '-mno-allow-string-insns': RX-Opts. (line 82)
  18981. * -mno-cis: PDP-11-Options. (line 32)
  18982. * -mno-csm: PDP-11-Options. (line 43)
  18983. * '-mno-dsbt' command line option, TIC6X: TIC6X Options. (line 13)
  18984. * -mno-eis: PDP-11-Options. (line 46)
  18985. * -mno-extensions: PDP-11-Options. (line 29)
  18986. * '-mno-fdpic' command line option, Blackfin: Blackfin Options.
  18987. (line 22)
  18988. * -mno-fis: PDP-11-Options. (line 51)
  18989. * -mno-fp-11: PDP-11-Options. (line 56)
  18990. * -mno-fpp: PDP-11-Options. (line 56)
  18991. * -mno-fpu: PDP-11-Options. (line 56)
  18992. * -mno-kev11: PDP-11-Options. (line 51)
  18993. * -mno-limited-eis: PDP-11-Options. (line 64)
  18994. * '-mno-link-relax' command line option, AVR: AVR Options. (line 124)
  18995. * -mno-mfpt: PDP-11-Options. (line 70)
  18996. * -mno-microcode: PDP-11-Options. (line 83)
  18997. * -mno-mutiproc: PDP-11-Options. (line 73)
  18998. * -mno-mxps: PDP-11-Options. (line 77)
  18999. * -mno-pic: PDP-11-Options. (line 11)
  19000. * '-mno-pic' command line option, TIC6X: TIC6X Options. (line 36)
  19001. * '-mno-regnames' option, s390: s390 Options. (line 50)
  19002. * '-mno-skip-bug' command line option, AVR: AVR Options. (line 111)
  19003. * -mno-spl: PDP-11-Options. (line 80)
  19004. * -mno-sym32: MIPS Options. (line 288)
  19005. * '-mno-verbose-error' command line option, AArch64: AArch64 Options.
  19006. (line 59)
  19007. * '-mno-wrap' command line option, AVR: AVR Options. (line 114)
  19008. * '-mnopic' command line option, Blackfin: Blackfin Options. (line 22)
  19009. * '-mnps400' command line option, ARC: ARC Options. (line 102)
  19010. * '-momit-lock-prefix=' option, i386: i386-Options. (line 152)
  19011. * '-momit-lock-prefix=' option, x86-64: i386-Options. (line 152)
  19012. * -mpic: PDP-11-Options. (line 11)
  19013. * '-mpic' command line option, TIC6X: TIC6X Options. (line 36)
  19014. * '-mpid': RX-Opts. (line 50)
  19015. * '-mpid=' command line option, TIC6X: TIC6X Options. (line 23)
  19016. * '-mregnames' option, s390: s390 Options. (line 47)
  19017. * '-mrelax' command line option, ARC: ARC Options. (line 97)
  19018. * '-mrelax' command line option, V850: V850 Options. (line 72)
  19019. * '-mrelax-relocations=' option, i386: i386-Options. (line 170)
  19020. * '-mrelax-relocations=' option, x86-64: i386-Options. (line 170)
  19021. * '-mrh850-abi' command line option, V850: V850 Options. (line 82)
  19022. * '-mrmw' command line option, AVR: AVR Options. (line 117)
  19023. * '-mrx-abi': RX-Opts. (line 69)
  19024. * '-mshared' option, i386: i386-Options. (line 139)
  19025. * '-mshared' option, x86-64: i386-Options. (line 139)
  19026. * '-mshort': M68HC11-Opts. (line 40)
  19027. * '-mshort' <1>: XGATE-Opts. (line 8)
  19028. * '-mshort-double': M68HC11-Opts. (line 49)
  19029. * '-mshort-double' <1>: XGATE-Opts. (line 17)
  19030. * '-msign-extend-enabled' command line option, LM32: LM32 Options.
  19031. (line 15)
  19032. * '-msmall-data-limit': RX-Opts. (line 42)
  19033. * '-msoft-float' command line option, V850: V850 Options. (line 95)
  19034. * '-mspfp' command line option, ARC: ARC Options. (line 105)
  19035. * -mspl: PDP-11-Options. (line 80)
  19036. * '-msse-check=' option, i386: i386-Options. (line 82)
  19037. * '-msse-check=' option, x86-64: i386-Options. (line 82)
  19038. * '-msse2avx' option, i386: i386-Options. (line 78)
  19039. * '-msse2avx' option, x86-64: i386-Options. (line 78)
  19040. * -msym32: MIPS Options. (line 288)
  19041. * '-msyntax=' option, i386: i386-Options. (line 123)
  19042. * '-msyntax=' option, x86-64: i386-Options. (line 123)
  19043. * -mt11: PDP-11-Options. (line 130)
  19044. * '-mthumb' command line option, ARM: ARM Options. (line 115)
  19045. * '-mthumb-interwork' command line option, ARM: ARM Options. (line 120)
  19046. * '-mtune=' option, i386: i386-Options. (line 70)
  19047. * '-mtune=' option, x86-64: i386-Options. (line 70)
  19048. * '-mtune=ARCH' command line option, Visium: Visium Options. (line 8)
  19049. * '-muse-conventional-section-names': RX-Opts. (line 33)
  19050. * '-muse-renesas-section-names': RX-Opts. (line 37)
  19051. * '-muser-enabled' command line option, LM32: LM32 Options. (line 18)
  19052. * '-mv850' command line option, V850: V850 Options. (line 23)
  19053. * '-mv850any' command line option, V850: V850 Options. (line 41)
  19054. * '-mv850e' command line option, V850: V850 Options. (line 29)
  19055. * '-mv850e1' command line option, V850: V850 Options. (line 35)
  19056. * '-mv850e2' command line option, V850: V850 Options. (line 51)
  19057. * '-mv850e2v3' command line option, V850: V850 Options. (line 57)
  19058. * '-mv850e2v4' command line option, V850: V850 Options. (line 63)
  19059. * '-mv850e3v5' command line option, V850: V850 Options. (line 66)
  19060. * '-mverbose-error' command line option, AArch64: AArch64 Options.
  19061. (line 55)
  19062. * '-mvxworks-pic' option, MIPS: MIPS Options. (line 26)
  19063. * '-mwarn-areg-zero' option, s390: s390 Options. (line 53)
  19064. * '-mwarn-deprecated' command line option, ARM: ARM Options. (line 196)
  19065. * '-mwarn-syms' command line option, ARM: ARM Options. (line 204)
  19066. * '-mzarch' option, s390: s390 Options. (line 17)
  19067. * '-m[no-]68851' command line option, M680x0: M68K-Opts. (line 21)
  19068. * '-m[no-]68881' command line option, M680x0: M68K-Opts. (line 21)
  19069. * '-m[no-]div' command line option, M680x0: M68K-Opts. (line 21)
  19070. * '-m[no-]emac' command line option, M680x0: M68K-Opts. (line 21)
  19071. * '-m[no-]float' command line option, M680x0: M68K-Opts. (line 21)
  19072. * '-m[no-]mac' command line option, M680x0: M68K-Opts. (line 21)
  19073. * '-m[no-]usp' command line option, M680x0: M68K-Opts. (line 21)
  19074. * '-N' command line option, CRIS: CRIS-Opts. (line 59)
  19075. * '-nIp' option, M32RX: M32R-Opts. (line 101)
  19076. * '-no-bitinst', M32R2: M32R-Opts. (line 54)
  19077. * '-no-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 93)
  19078. * '-no-mdebug' command line option, Alpha: Alpha Options. (line 25)
  19079. * '-no-parallel' option, M32RX: M32R-Opts. (line 51)
  19080. * '-no-relax' option, i960: Options-i960. (line 66)
  19081. * '-no-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts.
  19082. (line 79)
  19083. * '-no-warn-unmatched-high' option, M32R: M32R-Opts. (line 111)
  19084. * '-nocpp' ignored (MIPS): MIPS Options. (line 291)
  19085. * '-noreplace' command line option, Alpha: Alpha Options. (line 40)
  19086. * -o: o. (line 6)
  19087. * '-O' option, M32RX: M32R-Opts. (line 59)
  19088. * '-parallel' option, M32RX: M32R-Opts. (line 46)
  19089. * -R: R. (line 6)
  19090. * '-r800' command line option, Z80: Z80 Options. (line 35)
  19091. * '-relax' command line option, Alpha: Alpha Options. (line 32)
  19092. * '-replace' command line option, Alpha: Alpha Options. (line 40)
  19093. * '-S', ignored on VAX: VAX-Opts. (line 11)
  19094. * '-T', ignored on VAX: VAX-Opts. (line 11)
  19095. * '-t', ignored on VAX: VAX-Opts. (line 36)
  19096. * -v: v. (line 6)
  19097. * '-V', redundant on VAX: VAX-Opts. (line 22)
  19098. * -version: v. (line 6)
  19099. * -W: W. (line 11)
  19100. * '-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts.
  19101. (line 65)
  19102. * '-warn-unmatched-high' option, M32R: M32R-Opts. (line 105)
  19103. * '-Wnp' option, M32RX: M32R-Opts. (line 83)
  19104. * '-Wnuh' option, M32RX: M32R-Opts. (line 117)
  19105. * '-Wp' option, M32RX: M32R-Opts. (line 75)
  19106. * '-wsigned_overflow' command line option, V850: V850 Options.
  19107. (line 9)
  19108. * '-Wuh' option, M32RX: M32R-Opts. (line 114)
  19109. * '-wunsigned_overflow' command line option, V850: V850 Options.
  19110. (line 16)
  19111. * '-x' command line option, MMIX: MMIX-Opts. (line 44)
  19112. * '-z80' command line option, Z80: Z80 Options. (line 8)
  19113. * '-z8001' command line option, Z8000: Z8000 Options. (line 6)
  19114. * '-z8002' command line option, Z8000: Z8000 Options. (line 9)
  19115. * '.' (symbol): Dot. (line 6)
  19116. * '.2byte' directive, ARM: ARM Directives. (line 6)
  19117. * '.4byte' directive, ARM: ARM Directives. (line 6)
  19118. * '.8byte' directive, ARM: ARM Directives. (line 6)
  19119. * '.align' directive, ARM: ARM Directives. (line 11)
  19120. * '.align' directive, TILE-Gx: TILE-Gx Directives. (line 6)
  19121. * '.align' directive, TILEPro: TILEPro Directives. (line 6)
  19122. * '.allow_suspicious_bundles' directive, TILE-Gx: TILE-Gx Directives.
  19123. (line 10)
  19124. * '.allow_suspicious_bundles' directive, TILEPro: TILEPro Directives.
  19125. (line 10)
  19126. * '.arch' directive, AArch64: AArch64 Directives. (line 6)
  19127. * '.arch' directive, ARM: ARM Directives. (line 18)
  19128. * '.arch' directive, TIC6X: TIC6X Directives. (line 10)
  19129. * '.arch_extension' directive, AArch64: AArch64 Directives. (line 13)
  19130. * '.arch_extension' directive, ARM: ARM Directives. (line 25)
  19131. * '.arm' directive, ARM: ARM Directives. (line 33)
  19132. * '.big' directive, M32RX: M32R-Directives. (line 88)
  19133. * '.bss' directive, AArch64: AArch64 Directives. (line 21)
  19134. * '.bss' directive, ARM: ARM Directives. (line 36)
  19135. * '.c6xabi_attribute' directive, TIC6X: TIC6X Directives. (line 20)
  19136. * '.cantunwind' directive, ARM: ARM Directives. (line 39)
  19137. * '.cantunwind' directive, TIC6X: TIC6X Directives. (line 13)
  19138. * '.code' directive, ARM: ARM Directives. (line 43)
  19139. * '.cpu' directive, AArch64: AArch64 Directives. (line 24)
  19140. * '.cpu' directive, ARM: ARM Directives. (line 47)
  19141. * '.dn' and '.qn' directives, ARM: ARM Directives. (line 54)
  19142. * '.dword' directive, AArch64: AArch64 Directives. (line 28)
  19143. * '.eabi_attribute' directive, ARM: ARM Directives. (line 78)
  19144. * '.ehtype' directive, TIC6X: TIC6X Directives. (line 31)
  19145. * '.endp' directive, TIC6X: TIC6X Directives. (line 34)
  19146. * '.even' directive, AArch64: AArch64 Directives. (line 31)
  19147. * '.even' directive, ARM: ARM Directives. (line 106)
  19148. * '.extend' directive, ARM: ARM Directives. (line 109)
  19149. * '.fnend' directive, ARM: ARM Directives. (line 115)
  19150. * '.fnstart' directive, ARM: ARM Directives. (line 123)
  19151. * '.force_thumb' directive, ARM: ARM Directives. (line 126)
  19152. * '.fpu' directive, ARM: ARM Directives. (line 130)
  19153. * '.global': MIPS insn. (line 12)
  19154. * '.gnu_attribute 4, N' directive, MIPS: MIPS FP ABI History.
  19155. (line 6)
  19156. * '.gnu_attribute Tag_GNU_MIPS_ABI_FP, N' directive, MIPS: MIPS FP ABI History.
  19157. (line 6)
  19158. * '.handlerdata' directive, ARM: ARM Directives. (line 134)
  19159. * '.handlerdata' directive, TIC6X: TIC6X Directives. (line 39)
  19160. * '.insn': MIPS insn. (line 6)
  19161. * '.insn' directive, s390: s390 Directives. (line 11)
  19162. * '.inst' directive, AArch64: AArch64 Directives. (line 35)
  19163. * '.inst' directive, ARM: ARM Directives. (line 143)
  19164. * '.ldouble' directive, ARM: ARM Directives. (line 109)
  19165. * '.little' directive, M32RX: M32R-Directives. (line 82)
  19166. * '.long' directive, s390: s390 Directives. (line 16)
  19167. * '.ltorg' directive, AArch64: AArch64 Directives. (line 39)
  19168. * '.ltorg' directive, ARM: ARM Directives. (line 153)
  19169. * '.ltorg' directive, s390: s390 Directives. (line 79)
  19170. * '.m32r' directive, M32R: M32R-Directives. (line 66)
  19171. * '.m32r2' directive, M32R2: M32R-Directives. (line 77)
  19172. * '.m32rx' directive, M32RX: M32R-Directives. (line 72)
  19173. * '.machine' directive, s390: s390 Directives. (line 84)
  19174. * '.machinemode' directive, s390: s390 Directives. (line 101)
  19175. * '.module': MIPS assembly options.
  19176. (line 6)
  19177. * '.module fp=NN' directive, MIPS: MIPS FP ABI Selection.
  19178. (line 6)
  19179. * '.movsp' directive, ARM: ARM Directives. (line 167)
  19180. * '.nan' directive, MIPS: MIPS NaN Encodings. (line 6)
  19181. * '.nocmp' directive, TIC6X: TIC6X Directives. (line 47)
  19182. * '.no_pointers' directive, XStormy16: XStormy16 Directives.
  19183. (line 14)
  19184. * .o: Object. (line 6)
  19185. * '.object_arch' directive, ARM: ARM Directives. (line 172)
  19186. * '.packed' directive, ARM: ARM Directives. (line 178)
  19187. * '.pad' directive, ARM: ARM Directives. (line 183)
  19188. * '.param' on HPPA: HPPA Directives. (line 19)
  19189. * '.personality' directive, ARM: ARM Directives. (line 188)
  19190. * '.personality' directive, TIC6X: TIC6X Directives. (line 55)
  19191. * '.personalityindex' directive, ARM: ARM Directives. (line 191)
  19192. * '.personalityindex' directive, TIC6X: TIC6X Directives. (line 51)
  19193. * '.pool' directive, AArch64: AArch64 Directives. (line 53)
  19194. * '.pool' directive, ARM: ARM Directives. (line 195)
  19195. * '.quad' directive, s390: s390 Directives. (line 16)
  19196. * '.req' directive, AArch64: AArch64 Directives. (line 56)
  19197. * '.req' directive, ARM: ARM Directives. (line 198)
  19198. * '.require_canonical_reg_names' directive, TILE-Gx: TILE-Gx Directives.
  19199. (line 19)
  19200. * '.require_canonical_reg_names' directive, TILEPro: TILEPro Directives.
  19201. (line 19)
  19202. * '.save' directive, ARM: ARM Directives. (line 203)
  19203. * '.scomm' directive, TIC6X: TIC6X Directives. (line 58)
  19204. * '.secrel32' directive, ARM: ARM Directives. (line 241)
  19205. * '.set arch=CPU': MIPS ISA. (line 18)
  19206. * '.set at': MIPS Macros. (line 41)
  19207. * '.set at=REG': MIPS Macros. (line 35)
  19208. * '.set autoextend': MIPS autoextend. (line 6)
  19209. * '.set doublefloat': MIPS Floating-Point.
  19210. (line 12)
  19211. * '.set dsp': MIPS ASE Instruction Generation Overrides.
  19212. (line 21)
  19213. * '.set dspr2': MIPS ASE Instruction Generation Overrides.
  19214. (line 26)
  19215. * '.set dspr3': MIPS ASE Instruction Generation Overrides.
  19216. (line 31)
  19217. * '.set hardfloat': MIPS Floating-Point.
  19218. (line 6)
  19219. * '.set insn32': MIPS assembly options.
  19220. (line 18)
  19221. * '.set macro': MIPS Macros. (line 30)
  19222. * '.set mcu': MIPS ASE Instruction Generation Overrides.
  19223. (line 42)
  19224. * '.set mdmx': MIPS ASE Instruction Generation Overrides.
  19225. (line 16)
  19226. * '.set mips3d': MIPS ASE Instruction Generation Overrides.
  19227. (line 6)
  19228. * '.set mipsN': MIPS ISA. (line 6)
  19229. * '.set msa': MIPS ASE Instruction Generation Overrides.
  19230. (line 47)
  19231. * '.set mt': MIPS ASE Instruction Generation Overrides.
  19232. (line 37)
  19233. * '.set noat': MIPS Macros. (line 41)
  19234. * '.set noautoextend': MIPS autoextend. (line 6)
  19235. * '.set nodsp': MIPS ASE Instruction Generation Overrides.
  19236. (line 21)
  19237. * '.set nodspr2': MIPS ASE Instruction Generation Overrides.
  19238. (line 26)
  19239. * '.set nodspr3': MIPS ASE Instruction Generation Overrides.
  19240. (line 31)
  19241. * '.set noinsn32': MIPS assembly options.
  19242. (line 18)
  19243. * '.set nomacro': MIPS Macros. (line 30)
  19244. * '.set nomcu': MIPS ASE Instruction Generation Overrides.
  19245. (line 42)
  19246. * '.set nomdmx': MIPS ASE Instruction Generation Overrides.
  19247. (line 16)
  19248. * '.set nomips3d': MIPS ASE Instruction Generation Overrides.
  19249. (line 6)
  19250. * '.set nomsa': MIPS ASE Instruction Generation Overrides.
  19251. (line 47)
  19252. * '.set nomt': MIPS ASE Instruction Generation Overrides.
  19253. (line 37)
  19254. * '.set nosmartmips': MIPS ASE Instruction Generation Overrides.
  19255. (line 11)
  19256. * '.set nosym32': MIPS Symbol Sizes. (line 6)
  19257. * '.set novirt': MIPS ASE Instruction Generation Overrides.
  19258. (line 52)
  19259. * '.set noxpa': MIPS ASE Instruction Generation Overrides.
  19260. (line 57)
  19261. * '.set pop': MIPS Option Stack. (line 6)
  19262. * '.set push': MIPS Option Stack. (line 6)
  19263. * '.set singlefloat': MIPS Floating-Point.
  19264. (line 12)
  19265. * '.set smartmips': MIPS ASE Instruction Generation Overrides.
  19266. (line 11)
  19267. * '.set softfloat': MIPS Floating-Point.
  19268. (line 6)
  19269. * '.set sym32': MIPS Symbol Sizes. (line 6)
  19270. * '.set virt': MIPS ASE Instruction Generation Overrides.
  19271. (line 52)
  19272. * '.set xpa': MIPS ASE Instruction Generation Overrides.
  19273. (line 57)
  19274. * '.setfp' directive, ARM: ARM Directives. (line 227)
  19275. * '.short' directive, s390: s390 Directives. (line 16)
  19276. * '.syntax' directive, ARM: ARM Directives. (line 246)
  19277. * '.thumb' directive, ARM: ARM Directives. (line 250)
  19278. * '.thumb_func' directive, ARM: ARM Directives. (line 253)
  19279. * '.thumb_set' directive, ARM: ARM Directives. (line 264)
  19280. * '.tlsdescadd' directive, AArch64: AArch64 Directives. (line 61)
  19281. * '.tlsdesccall' directive, AArch64: AArch64 Directives. (line 64)
  19282. * '.tlsdescldr' directive, AArch64: AArch64 Directives. (line 67)
  19283. * '.tlsdescseq' directive, ARM: ARM Directives. (line 271)
  19284. * '.unreq' directive, AArch64: AArch64 Directives. (line 70)
  19285. * '.unreq' directive, ARM: ARM Directives. (line 276)
  19286. * '.unwind_raw' directive, ARM: ARM Directives. (line 287)
  19287. * '.v850' directive, V850: V850 Directives. (line 14)
  19288. * '.v850e' directive, V850: V850 Directives. (line 20)
  19289. * '.v850e1' directive, V850: V850 Directives. (line 26)
  19290. * '.v850e2' directive, V850: V850 Directives. (line 32)
  19291. * '.v850e2v3' directive, V850: V850 Directives. (line 38)
  19292. * '.v850e2v4' directive, V850: V850 Directives. (line 44)
  19293. * '.v850e3v5' directive, V850: V850 Directives. (line 50)
  19294. * '.vsave' directive, ARM: ARM Directives. (line 294)
  19295. * '.xword' directive, AArch64: AArch64 Directives. (line 81)
  19296. * .z8001: Z8000 Directives. (line 11)
  19297. * .z8002: Z8000 Directives. (line 15)
  19298. * 16-bit code, i386: i386-16bit. (line 6)
  19299. * '16bit_pointers' directive, XStormy16: XStormy16 Directives.
  19300. (line 6)
  19301. * '16byte' directive, Nios II: Nios II Directives. (line 28)
  19302. * '2byte' directive, Nios II: Nios II Directives. (line 19)
  19303. * '32bit_pointers' directive, XStormy16: XStormy16 Directives.
  19304. (line 10)
  19305. * 3DNow!, i386: i386-SIMD. (line 6)
  19306. * 3DNow!, x86-64: i386-SIMD. (line 6)
  19307. * 430 support: MSP430-Dependent. (line 6)
  19308. * '4byte' directive, Nios II: Nios II Directives. (line 22)
  19309. * '8byte' directive, Nios II: Nios II Directives. (line 25)
  19310. * ':' (label): Statements. (line 31)
  19311. * @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20)
  19312. * @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16)
  19313. * '@hi' pseudo-op, XStormy16: XStormy16 Opcodes. (line 21)
  19314. * '@lo' pseudo-op, XStormy16: XStormy16 Opcodes. (line 10)
  19315. * @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12)
  19316. * @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23)
  19317. * @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28)
  19318. * @word modifier, D10V: D10V-Word. (line 6)
  19319. * _ opcode prefix: Xtensa Opcodes. (line 9)
  19320. * __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14)
  19321. * __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols.
  19322. (line 11)
  19323. * a.out: Object. (line 6)
  19324. * 'a.out' symbol attributes: a.out Symbols. (line 6)
  19325. * AArch64 floating point (IEEE): AArch64 Floating Point.
  19326. (line 6)
  19327. * AArch64 immediate character: AArch64-Chars. (line 13)
  19328. * AArch64 line comment character: AArch64-Chars. (line 6)
  19329. * AArch64 line separator: AArch64-Chars. (line 10)
  19330. * AArch64 machine directives: AArch64 Directives. (line 6)
  19331. * AArch64 opcodes: AArch64 Opcodes. (line 6)
  19332. * AArch64 options (none): AArch64 Options. (line 6)
  19333. * AArch64 register names: AArch64-Regs. (line 6)
  19334. * AArch64 relocations: AArch64-Relocations.
  19335. (line 6)
  19336. * AArch64 support: AArch64-Dependent. (line 6)
  19337. * ABI options, SH64: SH64 Options. (line 25)
  19338. * 'abort' directive: Abort. (line 6)
  19339. * 'ABORT' directive: ABORT (COFF). (line 6)
  19340. * absolute section: Ld Sections. (line 29)
  19341. * 'absolute-literals' directive: Absolute Literals Directive.
  19342. (line 6)
  19343. * 'ADDI' instructions, relaxation: Xtensa Immediate Relaxation.
  19344. (line 43)
  19345. * addition, permitted arguments: Infix Ops. (line 45)
  19346. * addresses: Expressions. (line 6)
  19347. * addresses, format of: Secs Background. (line 65)
  19348. * addressing modes, D10V: D10V-Addressing. (line 6)
  19349. * addressing modes, D30V: D30V-Addressing. (line 6)
  19350. * addressing modes, H8/300: H8/300-Addressing. (line 6)
  19351. * addressing modes, M680x0: M68K-Syntax. (line 21)
  19352. * addressing modes, M68HC11: M68HC11-Syntax. (line 29)
  19353. * addressing modes, SH: SH-Addressing. (line 6)
  19354. * addressing modes, SH64: SH64-Addressing. (line 6)
  19355. * addressing modes, XGATE: XGATE-Syntax. (line 28)
  19356. * addressing modes, Z8000: Z8000-Addressing. (line 6)
  19357. * 'ADR reg,<label>' pseudo op, ARM: ARM Opcodes. (line 25)
  19358. * 'ADRL reg,<label>' pseudo op, ARM: ARM Opcodes. (line 35)
  19359. * ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations.
  19360. (line 14)
  19361. * advancing location counter: Org. (line 6)
  19362. * 'align' directive: Align. (line 6)
  19363. * 'align' directive, Nios II: Nios II Directives. (line 6)
  19364. * 'align' directive, SPARC: Sparc-Directives. (line 9)
  19365. * 'align' directive, TIC54X: TIC54X-Directives. (line 6)
  19366. * aligned instruction bundle: Bundle directives. (line 9)
  19367. * alignment for NEON instructions: ARM-Neon-Alignment. (line 6)
  19368. * alignment of branch targets: Xtensa Automatic Alignment.
  19369. (line 6)
  19370. * alignment of 'LOOP' instructions: Xtensa Automatic Alignment.
  19371. (line 6)
  19372. * Alpha floating point (IEEE): Alpha Floating Point.
  19373. (line 6)
  19374. * Alpha line comment character: Alpha-Chars. (line 6)
  19375. * Alpha line separator: Alpha-Chars. (line 11)
  19376. * Alpha notes: Alpha Notes. (line 6)
  19377. * Alpha options: Alpha Options. (line 6)
  19378. * Alpha registers: Alpha-Regs. (line 6)
  19379. * Alpha relocations: Alpha-Relocs. (line 6)
  19380. * Alpha support: Alpha-Dependent. (line 6)
  19381. * Alpha Syntax: Alpha Options. (line 60)
  19382. * Alpha-only directives: Alpha Directives. (line 9)
  19383. * Altera Nios II support: NiosII-Dependent. (line 6)
  19384. * altered difference tables: Word. (line 12)
  19385. * alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6)
  19386. * ARC Branch Target Address: ARC-Regs. (line 60)
  19387. * ARC BTA saved on exception entry: ARC-Regs. (line 79)
  19388. * ARC Build configuration for: BTA Registers: ARC-Regs. (line 89)
  19389. * ARC Build configuration for: Core Registers: ARC-Regs. (line 97)
  19390. * ARC Build configuration for: Interrupts: ARC-Regs. (line 93)
  19391. * ARC Build Configuration Registers Version: ARC-Regs. (line 85)
  19392. * ARC C preprocessor macro separator: ARC-Chars. (line 31)
  19393. * ARC core general registers: ARC-Regs. (line 10)
  19394. * ARC DCCM RAM Configuration Register: ARC-Regs. (line 101)
  19395. * ARC Exception Cause Register: ARC-Regs. (line 63)
  19396. * ARC Exception Return Address: ARC-Regs. (line 76)
  19397. * ARC extension core registers: ARC-Regs. (line 38)
  19398. * ARC frame pointer: ARC-Regs. (line 17)
  19399. * ARC global pointer: ARC-Regs. (line 14)
  19400. * ARC interrupt link register: ARC-Regs. (line 27)
  19401. * ARC Interrupt Vector Base address: ARC-Regs. (line 66)
  19402. * ARC level 1 interrupt link register: ARC-Regs. (line 23)
  19403. * ARC level 2 interrupt link register: ARC-Regs. (line 31)
  19404. * ARC line comment character: ARC-Chars. (line 11)
  19405. * ARC line separator: ARC-Chars. (line 27)
  19406. * ARC link register: ARC-Regs. (line 35)
  19407. * ARC loop counter: ARC-Regs. (line 41)
  19408. * ARC machine directives: ARC Directives. (line 6)
  19409. * ARC opcodes: ARC Opcodes. (line 6)
  19410. * ARC options: ARC Options. (line 6)
  19411. * ARC Processor Identification register: ARC-Regs. (line 51)
  19412. * ARC Program Counter: ARC-Regs. (line 54)
  19413. * ARC register name prefix character: ARC-Chars. (line 7)
  19414. * ARC register names: ARC-Regs. (line 6)
  19415. * ARC Saved User Stack Pointer: ARC-Regs. (line 73)
  19416. * ARC stack pointer: ARC-Regs. (line 20)
  19417. * ARC Status register: ARC-Regs. (line 57)
  19418. * ARC STATUS32 saved on exception: ARC-Regs. (line 82)
  19419. * ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs.
  19420. (line 69)
  19421. * ARC support: ARC-Dependent. (line 6)
  19422. * ARC symbol prefix character: ARC-Chars. (line 20)
  19423. * ARC word aligned program counter: ARC-Regs. (line 44)
  19424. * arch directive, i386: i386-Arch. (line 6)
  19425. * 'arch' directive, M680x0: M68K-Directives. (line 22)
  19426. * 'arch' directive, MSP 430: MSP430 Directives. (line 18)
  19427. * arch directive, x86-64: i386-Arch. (line 6)
  19428. * architecture options, i960: Options-i960. (line 6)
  19429. * architecture options, IP2022: IP2K-Opts. (line 9)
  19430. * architecture options, IP2K: IP2K-Opts. (line 14)
  19431. * architecture options, M16C: M32C-Opts. (line 12)
  19432. * architecture options, M32C: M32C-Opts. (line 9)
  19433. * architecture options, M32R: M32R-Opts. (line 21)
  19434. * architecture options, M32R2: M32R-Opts. (line 17)
  19435. * architecture options, M32RX: M32R-Opts. (line 9)
  19436. * architecture options, M680x0: M68K-Opts. (line 99)
  19437. * Architecture variant option, CRIS: CRIS-Opts. (line 34)
  19438. * architectures, Meta: Meta Options. (line 6)
  19439. * architectures, PowerPC: PowerPC-Opts. (line 6)
  19440. * architectures, SCORE: SCORE-Opts. (line 6)
  19441. * architectures, SPARC: Sparc-Opts. (line 6)
  19442. * arguments for addition: Infix Ops. (line 45)
  19443. * arguments for subtraction: Infix Ops. (line 50)
  19444. * arguments in expressions: Arguments. (line 6)
  19445. * arithmetic functions: Operators. (line 6)
  19446. * arithmetic operands: Arguments. (line 6)
  19447. * ARM data relocations: ARM-Relocations. (line 6)
  19448. * ARM floating point (IEEE): ARM Floating Point. (line 6)
  19449. * ARM identifiers: ARM-Chars. (line 19)
  19450. * ARM immediate character: ARM-Chars. (line 17)
  19451. * ARM line comment character: ARM-Chars. (line 6)
  19452. * ARM line separator: ARM-Chars. (line 14)
  19453. * ARM machine directives: ARM Directives. (line 6)
  19454. * ARM opcodes: ARM Opcodes. (line 6)
  19455. * ARM options (none): ARM Options. (line 6)
  19456. * ARM register names: ARM-Regs. (line 6)
  19457. * ARM support: ARM-Dependent. (line 6)
  19458. * 'ascii' directive: Ascii. (line 6)
  19459. * 'asciz' directive: Asciz. (line 6)
  19460. * 'asg' directive, TIC54X: TIC54X-Directives. (line 18)
  19461. * assembler bugs, reporting: Bug Reporting. (line 6)
  19462. * assembler crash: Bug Criteria. (line 9)
  19463. * assembler directive .3byte, RX: RX-Directives. (line 9)
  19464. * assembler directive .arch, CRIS: CRIS-Pseudos. (line 50)
  19465. * assembler directive .dword, CRIS: CRIS-Pseudos. (line 12)
  19466. * assembler directive .far, M68HC11: M68HC11-Directives. (line 20)
  19467. * assembler directive .fetchalign, RX: RX-Directives. (line 13)
  19468. * assembler directive .interrupt, M68HC11: M68HC11-Directives.
  19469. (line 26)
  19470. * assembler directive .mode, M68HC11: M68HC11-Directives. (line 16)
  19471. * assembler directive .relax, M68HC11: M68HC11-Directives. (line 10)
  19472. * assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18)
  19473. * assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31)
  19474. * assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137)
  19475. * assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101)
  19476. * assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137)
  19477. * assembler directive GREG, MMIX: MMIX-Pseudos. (line 53)
  19478. * assembler directive IS, MMIX: MMIX-Pseudos. (line 44)
  19479. * assembler directive LOC, MMIX: MMIX-Pseudos. (line 7)
  19480. * assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29)
  19481. * assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113)
  19482. * assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125)
  19483. * assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113)
  19484. * assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113)
  19485. * assembler directives, CRIS: CRIS-Pseudos. (line 6)
  19486. * assembler directives, M68HC11: M68HC11-Directives. (line 6)
  19487. * assembler directives, M68HC12: M68HC11-Directives. (line 6)
  19488. * assembler directives, MMIX: MMIX-Pseudos. (line 6)
  19489. * assembler directives, RL78: RL78-Directives. (line 6)
  19490. * assembler directives, RX: RX-Directives. (line 6)
  19491. * assembler directives, XGATE: XGATE-Directives. (line 6)
  19492. * assembler internal logic error: As Sections. (line 13)
  19493. * assembler version: v. (line 6)
  19494. * assembler, and linker: Secs Background. (line 10)
  19495. * assembly listings, enabling: a. (line 6)
  19496. * assigning values to symbols: Setting Symbols. (line 6)
  19497. * assigning values to symbols <1>: Equ. (line 6)
  19498. * 'at' register, MIPS: MIPS Macros. (line 35)
  19499. * 'atmp' directive, i860: Directives-i860. (line 16)
  19500. * attributes, symbol: Symbol Attributes. (line 6)
  19501. * att_syntax pseudo op, i386: i386-Variations. (line 6)
  19502. * att_syntax pseudo op, x86-64: i386-Variations. (line 6)
  19503. * auxiliary attributes, COFF symbols: COFF Symbols. (line 19)
  19504. * auxiliary symbol information, COFF: Dim. (line 6)
  19505. * AVR line comment character: AVR-Chars. (line 6)
  19506. * AVR line separator: AVR-Chars. (line 14)
  19507. * AVR modifiers: AVR-Modifiers. (line 6)
  19508. * AVR opcode summary: AVR Opcodes. (line 6)
  19509. * AVR options (none): AVR Options. (line 6)
  19510. * AVR register names: AVR-Regs. (line 6)
  19511. * AVR support: AVR-Dependent. (line 6)
  19512. * 'A_DIR' environment variable, TIC54X: TIC54X-Env. (line 6)
  19513. * backslash ('\\'): Strings. (line 40)
  19514. * backspace ('\b'): Strings. (line 15)
  19515. * 'balign' directive: Balign. (line 6)
  19516. * 'balignl' directive: Balign. (line 27)
  19517. * 'balignw' directive: Balign. (line 27)
  19518. * 'bes' directive, TIC54X: TIC54X-Directives. (line 194)
  19519. * big endian output, MIPS: Overview. (line 806)
  19520. * big endian output, PJ: Overview. (line 713)
  19521. * big-endian output, MIPS: MIPS Options. (line 13)
  19522. * big-endian output, TIC6X: TIC6X Options. (line 46)
  19523. * bignums: Bignums. (line 6)
  19524. * binary constants, TIC54X: TIC54X-Constants. (line 8)
  19525. * binary files, including: Incbin. (line 6)
  19526. * binary integers: Integers. (line 6)
  19527. * bit names, IA-64: IA-64-Bits. (line 6)
  19528. * bitfields, not supported on VAX: VAX-no. (line 6)
  19529. * Blackfin directives: Blackfin Directives.
  19530. (line 6)
  19531. * Blackfin options (none): Blackfin Options. (line 6)
  19532. * Blackfin support: Blackfin-Dependent. (line 6)
  19533. * Blackfin syntax: Blackfin Syntax. (line 6)
  19534. * block: Z8000 Directives. (line 54)
  19535. * BMI, i386: i386-BMI. (line 6)
  19536. * BMI, x86-64: i386-BMI. (line 6)
  19537. * branch improvement, M680x0: M68K-Branch. (line 6)
  19538. * branch improvement, M68HC11: M68HC11-Branch. (line 6)
  19539. * branch improvement, VAX: VAX-branch. (line 6)
  19540. * branch instructions, relaxation: Xtensa Branch Relaxation.
  19541. (line 6)
  19542. * branch recording, i960: Options-i960. (line 22)
  19543. * branch statistics table, i960: Options-i960. (line 40)
  19544. * Branch Target Address, ARC: ARC-Regs. (line 60)
  19545. * branch target alignment: Xtensa Automatic Alignment.
  19546. (line 6)
  19547. * 'break' directive, TIC54X: TIC54X-Directives. (line 141)
  19548. * BSD syntax: PDP-11-Syntax. (line 6)
  19549. * 'bss' directive, i960: Directives-i960. (line 6)
  19550. * 'bss' directive, TIC54X: TIC54X-Directives. (line 27)
  19551. * bss section: Ld Sections. (line 20)
  19552. * bss section <1>: bss. (line 6)
  19553. * BTA saved on exception entry, ARC: ARC-Regs. (line 79)
  19554. * bug criteria: Bug Criteria. (line 6)
  19555. * bug reports: Bug Reporting. (line 6)
  19556. * bugs in assembler: Reporting Bugs. (line 6)
  19557. * Build configuration for: BTA Registers, ARC: ARC-Regs. (line 89)
  19558. * Build configuration for: Core Registers, ARC: ARC-Regs. (line 97)
  19559. * Build configuration for: Interrupts, ARC: ARC-Regs. (line 93)
  19560. * Build Configuration Registers Version, ARC: ARC-Regs. (line 85)
  19561. * Built-in symbols, CRIS: CRIS-Symbols. (line 6)
  19562. * builtin math functions, TIC54X: TIC54X-Builtins. (line 6)
  19563. * builtin subsym functions, TIC54X: TIC54X-Macros. (line 16)
  19564. * bundle: Bundle directives. (line 9)
  19565. * bundle-locked: Bundle directives. (line 39)
  19566. * 'bundle_align_mode' directive: Bundle directives. (line 9)
  19567. * 'bundle_lock' directive: Bundle directives. (line 31)
  19568. * 'bundle_unlock' directive: Bundle directives. (line 31)
  19569. * bus lock prefixes, i386: i386-Prefixes. (line 36)
  19570. * bval: Z8000 Directives. (line 30)
  19571. * 'byte' directive: Byte. (line 6)
  19572. * 'byte' directive, TIC54X: TIC54X-Directives. (line 34)
  19573. * C preprocessor macro separator, ARC: ARC-Chars. (line 31)
  19574. * 'C54XDSP_DIR' environment variable, TIC54X: TIC54X-Env. (line 6)
  19575. * 'call' directive, Nios II: Nios II Relocations.
  19576. (line 38)
  19577. * call instructions, i386: i386-Mnemonics. (line 58)
  19578. * call instructions, relaxation: Xtensa Call Relaxation.
  19579. (line 6)
  19580. * call instructions, x86-64: i386-Mnemonics. (line 58)
  19581. * 'callj', i960 pseudo-opcode: callj-i960. (line 6)
  19582. * 'call_hiadj' directive, Nios II: Nios II Relocations.
  19583. (line 38)
  19584. * 'call_lo' directive, Nios II: Nios II Relocations.
  19585. (line 38)
  19586. * carriage return ('backslash-r'): Strings. (line 24)
  19587. * case sensitivity, Z80: Z80-Case. (line 6)
  19588. * 'cfi_endproc' directive: CFI directives. (line 40)
  19589. * 'cfi_fde_data' directive: CFI directives. (line 66)
  19590. * 'cfi_personality' directive: CFI directives. (line 47)
  19591. * 'cfi_personality_id' directive: CFI directives. (line 59)
  19592. * 'cfi_sections' directive: CFI directives. (line 9)
  19593. * 'cfi_startproc' directive: CFI directives. (line 30)
  19594. * 'char' directive, TIC54X: TIC54X-Directives. (line 34)
  19595. * character constant, Z80: Z80-Chars. (line 20)
  19596. * character constants: Characters. (line 6)
  19597. * character escape codes: Strings. (line 15)
  19598. * character escapes, Z80: Z80-Chars. (line 18)
  19599. * character, single: Chars. (line 6)
  19600. * characters used in symbols: Symbol Intro. (line 6)
  19601. * 'clink' directive, TIC54X: TIC54X-Directives. (line 43)
  19602. * 'code16' directive, i386: i386-16bit. (line 6)
  19603. * 'code16gcc' directive, i386: i386-16bit. (line 6)
  19604. * 'code32' directive, i386: i386-16bit. (line 6)
  19605. * 'code64' directive, i386: i386-16bit. (line 6)
  19606. * 'code64' directive, x86-64: i386-16bit. (line 6)
  19607. * COFF auxiliary symbol information: Dim. (line 6)
  19608. * COFF structure debugging: Tag. (line 6)
  19609. * COFF symbol attributes: COFF Symbols. (line 6)
  19610. * COFF symbol descriptor: Desc. (line 6)
  19611. * COFF symbol storage class: Scl. (line 6)
  19612. * COFF symbol type: Type. (line 11)
  19613. * COFF symbols, debugging: Def. (line 6)
  19614. * COFF value attribute: Val. (line 6)
  19615. * COMDAT: Linkonce. (line 6)
  19616. * 'comm' directive: Comm. (line 6)
  19617. * command line conventions: Command Line. (line 6)
  19618. * command line options, V850: V850 Options. (line 9)
  19619. * command-line options ignored, VAX: VAX-Opts. (line 6)
  19620. * comment character, XStormy16: XStormy16-Chars. (line 11)
  19621. * comments: Comments. (line 6)
  19622. * comments, M680x0: M68K-Chars. (line 6)
  19623. * comments, removed by preprocessor: Preprocessing. (line 11)
  19624. * 'common' directive, SPARC: Sparc-Directives. (line 12)
  19625. * common sections: Linkonce. (line 6)
  19626. * common variable storage: bss. (line 6)
  19627. * compare and jump expansions, i960: Compare-and-branch-i960.
  19628. (line 13)
  19629. * compare/branch instructions, i960: Compare-and-branch-i960.
  19630. (line 6)
  19631. * comparison expressions: Infix Ops. (line 56)
  19632. * conditional assembly: If. (line 6)
  19633. * constant, single character: Chars. (line 6)
  19634. * constants: Constants. (line 6)
  19635. * constants, bignum: Bignums. (line 6)
  19636. * constants, character: Characters. (line 6)
  19637. * constants, converted by preprocessor: Preprocessing. (line 14)
  19638. * constants, floating point: Flonums. (line 6)
  19639. * constants, integer: Integers. (line 6)
  19640. * constants, number: Numbers. (line 6)
  19641. * constants, Sparc: Sparc-Constants. (line 6)
  19642. * constants, string: Strings. (line 6)
  19643. * constants, TIC54X: TIC54X-Constants. (line 6)
  19644. * conversion instructions, i386: i386-Mnemonics. (line 39)
  19645. * conversion instructions, x86-64: i386-Mnemonics. (line 39)
  19646. * coprocessor wait, i386: i386-Prefixes. (line 40)
  19647. * 'copy' directive, TIC54X: TIC54X-Directives. (line 52)
  19648. * core general registers, ARC: ARC-Regs. (line 10)
  19649. * 'cpu' directive, ARC: ARC Directives. (line 27)
  19650. * 'cpu' directive, M680x0: M68K-Directives. (line 30)
  19651. * 'cpu' directive, MSP 430: MSP430 Directives. (line 22)
  19652. * CR16 line comment character: CR16-Chars. (line 6)
  19653. * CR16 line separator: CR16-Chars. (line 12)
  19654. * CR16 Operand Qualifiers: CR16 Operand Qualifiers.
  19655. (line 6)
  19656. * CR16 support: CR16-Dependent. (line 6)
  19657. * crash of assembler: Bug Criteria. (line 9)
  19658. * CRIS '--emulation=crisaout' command line option: CRIS-Opts.
  19659. (line 9)
  19660. * CRIS '--emulation=criself' command line option: CRIS-Opts. (line 9)
  19661. * CRIS '--march=ARCHITECTURE' command line option: CRIS-Opts.
  19662. (line 34)
  19663. * CRIS '--mul-bug-abort' command line option: CRIS-Opts. (line 63)
  19664. * CRIS '--no-mul-bug-abort' command line option: CRIS-Opts. (line 63)
  19665. * CRIS '--no-underscore' command line option: CRIS-Opts. (line 15)
  19666. * CRIS '--pic' command line option: CRIS-Opts. (line 27)
  19667. * CRIS '--underscore' command line option: CRIS-Opts. (line 15)
  19668. * CRIS '-N' command line option: CRIS-Opts. (line 59)
  19669. * CRIS architecture variant option: CRIS-Opts. (line 34)
  19670. * CRIS assembler directive .arch: CRIS-Pseudos. (line 50)
  19671. * CRIS assembler directive .dword: CRIS-Pseudos. (line 12)
  19672. * CRIS assembler directive .syntax: CRIS-Pseudos. (line 18)
  19673. * CRIS assembler directives: CRIS-Pseudos. (line 6)
  19674. * CRIS built-in symbols: CRIS-Symbols. (line 6)
  19675. * CRIS instruction expansion: CRIS-Expand. (line 6)
  19676. * CRIS line comment characters: CRIS-Chars. (line 6)
  19677. * CRIS options: CRIS-Opts. (line 6)
  19678. * CRIS position-independent code: CRIS-Opts. (line 27)
  19679. * CRIS pseudo-op .arch: CRIS-Pseudos. (line 50)
  19680. * CRIS pseudo-op .dword: CRIS-Pseudos. (line 12)
  19681. * CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18)
  19682. * CRIS pseudo-ops: CRIS-Pseudos. (line 6)
  19683. * CRIS register names: CRIS-Regs. (line 6)
  19684. * CRIS support: CRIS-Dependent. (line 6)
  19685. * CRIS symbols in position-independent code: CRIS-Pic. (line 6)
  19686. * 'ctbp' register, V850: V850-Regs. (line 90)
  19687. * 'ctoff' pseudo-op, V850: V850 Opcodes. (line 110)
  19688. * 'ctpc' register, V850: V850-Regs. (line 82)
  19689. * 'ctpsw' register, V850: V850-Regs. (line 84)
  19690. * current address: Dot. (line 6)
  19691. * current address, advancing: Org. (line 6)
  19692. * 'c_mode' directive, TIC54X: TIC54X-Directives. (line 49)
  19693. * D10V @word modifier: D10V-Word. (line 6)
  19694. * D10V addressing modes: D10V-Addressing. (line 6)
  19695. * D10V floating point: D10V-Float. (line 6)
  19696. * D10V line comment character: D10V-Chars. (line 6)
  19697. * D10V opcode summary: D10V-Opcodes. (line 6)
  19698. * D10V optimization: Overview. (line 579)
  19699. * D10V options: D10V-Opts. (line 6)
  19700. * D10V registers: D10V-Regs. (line 6)
  19701. * D10V size modifiers: D10V-Size. (line 6)
  19702. * D10V sub-instruction ordering: D10V-Chars. (line 14)
  19703. * D10V sub-instructions: D10V-Subs. (line 6)
  19704. * D10V support: D10V-Dependent. (line 6)
  19705. * D10V syntax: D10V-Syntax. (line 6)
  19706. * D30V addressing modes: D30V-Addressing. (line 6)
  19707. * D30V floating point: D30V-Float. (line 6)
  19708. * D30V Guarded Execution: D30V-Guarded. (line 6)
  19709. * D30V line comment character: D30V-Chars. (line 6)
  19710. * D30V nops: Overview. (line 587)
  19711. * D30V nops after 32-bit multiply: Overview. (line 590)
  19712. * D30V opcode summary: D30V-Opcodes. (line 6)
  19713. * D30V optimization: Overview. (line 584)
  19714. * D30V options: D30V-Opts. (line 6)
  19715. * D30V registers: D30V-Regs. (line 6)
  19716. * D30V size modifiers: D30V-Size. (line 6)
  19717. * D30V sub-instruction ordering: D30V-Chars. (line 14)
  19718. * D30V sub-instructions: D30V-Subs. (line 6)
  19719. * D30V support: D30V-Dependent. (line 6)
  19720. * D30V syntax: D30V-Syntax. (line 6)
  19721. * data alignment on SPARC: Sparc-Aligned-Data. (line 6)
  19722. * data and text sections, joining: R. (line 6)
  19723. * 'data' directive: Data. (line 6)
  19724. * 'data' directive, TIC54X: TIC54X-Directives. (line 59)
  19725. * data relocations, ARM: ARM-Relocations. (line 6)
  19726. * data section: Ld Sections. (line 9)
  19727. * 'data1' directive, M680x0: M68K-Directives. (line 9)
  19728. * 'data2' directive, M680x0: M68K-Directives. (line 12)
  19729. * datalabel, SH64: SH64-Addressing. (line 16)
  19730. * 'dbpc' register, V850: V850-Regs. (line 86)
  19731. * 'dbpsw' register, V850: V850-Regs. (line 88)
  19732. * DCCM RAM Configuration Register, ARC: ARC-Regs. (line 101)
  19733. * debuggers, and symbol order: Symbols. (line 10)
  19734. * debugging COFF symbols: Def. (line 6)
  19735. * DEC syntax: PDP-11-Syntax. (line 6)
  19736. * decimal integers: Integers. (line 12)
  19737. * 'def' directive: Def. (line 6)
  19738. * 'def' directive, TIC54X: TIC54X-Directives. (line 101)
  19739. * density instructions: Density Instructions.
  19740. (line 6)
  19741. * dependency tracking: MD. (line 6)
  19742. * deprecated directives: Deprecated. (line 6)
  19743. * 'desc' directive: Desc. (line 6)
  19744. * descriptor, of 'a.out' symbol: Symbol Desc. (line 6)
  19745. * 'dfloat' directive, VAX: VAX-directives. (line 9)
  19746. * difference tables altered: Word. (line 12)
  19747. * difference tables, warning: K. (line 6)
  19748. * differences, mmixal: MMIX-mmixal. (line 6)
  19749. * 'dim' directive: Dim. (line 6)
  19750. * directives and instructions: Statements. (line 20)
  19751. * directives for PowerPC: PowerPC-Pseudo. (line 6)
  19752. * directives for SCORE: SCORE-Pseudo. (line 6)
  19753. * directives, Blackfin: Blackfin Directives.
  19754. (line 6)
  19755. * directives, M32R: M32R-Directives. (line 6)
  19756. * directives, M680x0: M68K-Directives. (line 6)
  19757. * directives, machine independent: Pseudo Ops. (line 6)
  19758. * directives, Xtensa: Xtensa Directives. (line 6)
  19759. * directives, Z8000: Z8000 Directives. (line 6)
  19760. * Disable floating-point instructions: MIPS Floating-Point.
  19761. (line 6)
  19762. * Disable single-precision floating-point operations: MIPS Floating-Point.
  19763. (line 12)
  19764. * displacement sizing character, VAX: VAX-operands. (line 12)
  19765. * dollar local symbols: Symbol Names. (line 113)
  19766. * dot (symbol): Dot. (line 6)
  19767. * 'double' directive: Double. (line 6)
  19768. * 'double' directive, i386: i386-Float. (line 14)
  19769. * 'double' directive, M680x0: M68K-Float. (line 14)
  19770. * 'double' directive, M68HC11: M68HC11-Float. (line 14)
  19771. * 'double' directive, RX: RX-Float. (line 11)
  19772. * 'double' directive, TIC54X: TIC54X-Directives. (line 62)
  19773. * 'double' directive, VAX: VAX-float. (line 15)
  19774. * 'double' directive, x86-64: i386-Float. (line 14)
  19775. * 'double' directive, XGATE: XGATE-Float. (line 13)
  19776. * doublequote ('\"'): Strings. (line 43)
  19777. * 'drlist' directive, TIC54X: TIC54X-Directives. (line 71)
  19778. * 'drnolist' directive, TIC54X: TIC54X-Directives. (line 71)
  19779. * 'dual' directive, i860: Directives-i860. (line 6)
  19780. * 'dword' directive, Nios II: Nios II Directives. (line 16)
  19781. * 'EB' command line option, Nios II: Nios II Options. (line 22)
  19782. * 'ecr' register, V850: V850-Regs. (line 78)
  19783. * eight-byte integer: Quad. (line 9)
  19784. * 'eipc' register, V850: V850-Regs. (line 70)
  19785. * 'eipsw' register, V850: V850-Regs. (line 72)
  19786. * 'eject' directive: Eject. (line 6)
  19787. * 'EL' command line option, Nios II: Nios II Options. (line 25)
  19788. * ELF symbol type: Type. (line 22)
  19789. * 'else' directive: Else. (line 6)
  19790. * 'elseif' directive: Elseif. (line 6)
  19791. * empty expressions: Empty Exprs. (line 6)
  19792. * 'emsg' directive, TIC54X: TIC54X-Directives. (line 75)
  19793. * emulation: Overview. (line 1007)
  19794. * encoding options, i386: i386-Mnemonics. (line 34)
  19795. * encoding options, x86-64: i386-Mnemonics. (line 34)
  19796. * 'end' directive: End. (line 6)
  19797. * 'enddual' directive, i860: Directives-i860. (line 11)
  19798. * 'endef' directive: Endef. (line 6)
  19799. * 'endfunc' directive: Endfunc. (line 6)
  19800. * endianness, MIPS: Overview. (line 806)
  19801. * endianness, PJ: Overview. (line 713)
  19802. * 'endif' directive: Endif. (line 6)
  19803. * 'endloop' directive, TIC54X: TIC54X-Directives. (line 141)
  19804. * 'endm' directive: Macro. (line 137)
  19805. * 'endm' directive, TIC54X: TIC54X-Directives. (line 151)
  19806. * 'endstruct' directive, TIC54X: TIC54X-Directives. (line 214)
  19807. * 'endunion' directive, TIC54X: TIC54X-Directives. (line 248)
  19808. * environment settings, TIC54X: TIC54X-Env. (line 6)
  19809. * EOF, newline must precede: Statements. (line 14)
  19810. * 'ep' register, V850: V850-Regs. (line 66)
  19811. * Epiphany line comment character: Epiphany-Chars. (line 6)
  19812. * Epiphany line separator: Epiphany-Chars. (line 14)
  19813. * Epiphany options: Epiphany Options. (line 6)
  19814. * Epiphany support: Epiphany-Dependent. (line 6)
  19815. * 'equ' directive: Equ. (line 6)
  19816. * 'equ' directive, TIC54X: TIC54X-Directives. (line 189)
  19817. * 'equiv' directive: Equiv. (line 6)
  19818. * 'eqv' directive: Eqv. (line 6)
  19819. * 'err' directive: Err. (line 6)
  19820. * error directive: Error. (line 6)
  19821. * error messages: Errors. (line 6)
  19822. * error on valid input: Bug Criteria. (line 12)
  19823. * errors, caused by warnings: W. (line 16)
  19824. * errors, continuing after: Z. (line 6)
  19825. * ESA/390 floating point (IEEE): ESA/390 Floating Point.
  19826. (line 6)
  19827. * ESA/390 support: ESA/390-Dependent. (line 6)
  19828. * ESA/390 Syntax: ESA/390 Options. (line 7)
  19829. * ESA/390-only directives: ESA/390 Directives. (line 12)
  19830. * escape codes, character: Strings. (line 15)
  19831. * 'eval' directive, TIC54X: TIC54X-Directives. (line 22)
  19832. * even: Z8000 Directives. (line 57)
  19833. * 'even' directive, M680x0: M68K-Directives. (line 15)
  19834. * 'even' directive, TIC54X: TIC54X-Directives. (line 6)
  19835. * Exception Cause Register, ARC: ARC-Regs. (line 63)
  19836. * Exception Return Address, ARC: ARC-Regs. (line 76)
  19837. * 'exitm' directive: Macro. (line 140)
  19838. * expr (internal section): As Sections. (line 17)
  19839. * expression arguments: Arguments. (line 6)
  19840. * expressions: Expressions. (line 6)
  19841. * expressions, comparison: Infix Ops. (line 56)
  19842. * expressions, empty: Empty Exprs. (line 6)
  19843. * expressions, integer: Integer Exprs. (line 6)
  19844. * 'extAuxRegister' directive, ARC: ARC Directives. (line 105)
  19845. * 'extCondCode' directive, ARC: ARC Directives. (line 126)
  19846. * 'extCoreRegister' directive, ARC: ARC Directives. (line 137)
  19847. * 'extend' directive M680x0: M68K-Float. (line 17)
  19848. * 'extend' directive M68HC11: M68HC11-Float. (line 17)
  19849. * 'extend' directive XGATE: XGATE-Float. (line 16)
  19850. * 'extended' directive, i960: Directives-i960. (line 13)
  19851. * extension core registers, ARC: ARC-Regs. (line 38)
  19852. * 'extern' directive: Extern. (line 6)
  19853. * 'extInstruction' directive, ARC: ARC Directives. (line 164)
  19854. * 'fail' directive: Fail. (line 6)
  19855. * 'far_mode' directive, TIC54X: TIC54X-Directives. (line 80)
  19856. * faster processing ('-f'): f. (line 6)
  19857. * fatal signal: Bug Criteria. (line 9)
  19858. * 'fclist' directive, TIC54X: TIC54X-Directives. (line 85)
  19859. * 'fcnolist' directive, TIC54X: TIC54X-Directives. (line 85)
  19860. * 'fepc' register, V850: V850-Regs. (line 74)
  19861. * 'fepsw' register, V850: V850-Regs. (line 76)
  19862. * 'ffloat' directive, VAX: VAX-directives. (line 13)
  19863. * 'field' directive, TIC54X: TIC54X-Directives. (line 89)
  19864. * 'file' directive: File. (line 6)
  19865. * 'file' directive, MSP 430: MSP430 Directives. (line 6)
  19866. * file name, logical: File. (line 13)
  19867. * file names and line numbers, in warnings/errors: Errors. (line 16)
  19868. * files, including: Include. (line 6)
  19869. * files, input: Input Files. (line 6)
  19870. * 'fill' directive: Fill. (line 6)
  19871. * filling memory: Skip. (line 6)
  19872. * filling memory <1>: Space. (line 6)
  19873. * filling memory with zero bytes: Zero. (line 6)
  19874. * FLIX syntax: Xtensa Syntax. (line 6)
  19875. * 'float' directive: Float. (line 6)
  19876. * 'float' directive, i386: i386-Float. (line 14)
  19877. * 'float' directive, M680x0: M68K-Float. (line 11)
  19878. * 'float' directive, M68HC11: M68HC11-Float. (line 11)
  19879. * 'float' directive, RX: RX-Float. (line 8)
  19880. * 'float' directive, TIC54X: TIC54X-Directives. (line 62)
  19881. * 'float' directive, VAX: VAX-float. (line 15)
  19882. * 'float' directive, x86-64: i386-Float. (line 14)
  19883. * 'float' directive, XGATE: XGATE-Float. (line 10)
  19884. * floating point numbers: Flonums. (line 6)
  19885. * floating point numbers (double): Double. (line 6)
  19886. * floating point numbers (single): Float. (line 6)
  19887. * floating point numbers (single) <1>: Single. (line 6)
  19888. * floating point, AArch64 (IEEE): AArch64 Floating Point.
  19889. (line 6)
  19890. * floating point, Alpha (IEEE): Alpha Floating Point.
  19891. (line 6)
  19892. * floating point, ARM (IEEE): ARM Floating Point. (line 6)
  19893. * floating point, D10V: D10V-Float. (line 6)
  19894. * floating point, D30V: D30V-Float. (line 6)
  19895. * floating point, ESA/390 (IEEE): ESA/390 Floating Point.
  19896. (line 6)
  19897. * floating point, H8/300 (IEEE): H8/300 Floating Point.
  19898. (line 6)
  19899. * floating point, HPPA (IEEE): HPPA Floating Point.
  19900. (line 6)
  19901. * floating point, i386: i386-Float. (line 6)
  19902. * floating point, i960 (IEEE): Floating Point-i960.
  19903. (line 6)
  19904. * floating point, M680x0: M68K-Float. (line 6)
  19905. * floating point, M68HC11: M68HC11-Float. (line 6)
  19906. * floating point, MSP 430 (IEEE): MSP430 Floating Point.
  19907. (line 6)
  19908. * floating point, RX: RX-Float. (line 6)
  19909. * floating point, s390: s390 Floating Point.
  19910. (line 6)
  19911. * floating point, SH (IEEE): SH Floating Point. (line 6)
  19912. * floating point, SPARC (IEEE): Sparc-Float. (line 6)
  19913. * floating point, V850 (IEEE): V850 Floating Point.
  19914. (line 6)
  19915. * floating point, VAX: VAX-float. (line 6)
  19916. * floating point, x86-64: i386-Float. (line 6)
  19917. * floating point, XGATE: XGATE-Float. (line 6)
  19918. * floating point, Z80: Z80 Floating Point. (line 6)
  19919. * flonums: Flonums. (line 6)
  19920. * format of error messages: Errors. (line 38)
  19921. * format of warning messages: Errors. (line 12)
  19922. * formfeed ('\f'): Strings. (line 18)
  19923. * frame pointer, ARC: ARC-Regs. (line 17)
  19924. * 'func' directive: Func. (line 6)
  19925. * functions, in expressions: Operators. (line 6)
  19926. * 'gbr960', i960 postprocessor: Options-i960. (line 40)
  19927. * 'gfloat' directive, VAX: VAX-directives. (line 17)
  19928. * global: Z8000 Directives. (line 21)
  19929. * 'global' directive: Global. (line 6)
  19930. * 'global' directive, TIC54X: TIC54X-Directives. (line 101)
  19931. * global pointer, ARC: ARC-Regs. (line 14)
  19932. * 'got' directive, Nios II: Nios II Relocations.
  19933. (line 38)
  19934. * 'gotoff' directive, Nios II: Nios II Relocations.
  19935. (line 38)
  19936. * 'gotoff_hiadj' directive, Nios II: Nios II Relocations.
  19937. (line 38)
  19938. * 'gotoff_lo' directive, Nios II: Nios II Relocations.
  19939. (line 38)
  19940. * 'got_hiadj' directive, Nios II: Nios II Relocations.
  19941. (line 38)
  19942. * 'got_lo' directive, Nios II: Nios II Relocations.
  19943. (line 38)
  19944. * 'gp' register, MIPS: MIPS Small Data. (line 6)
  19945. * 'gp' register, V850: V850-Regs. (line 14)
  19946. * 'gprel' directive, Nios II: Nios II Relocations.
  19947. (line 26)
  19948. * grouping data: Sub-Sections. (line 6)
  19949. * H8/300 addressing modes: H8/300-Addressing. (line 6)
  19950. * H8/300 floating point (IEEE): H8/300 Floating Point.
  19951. (line 6)
  19952. * H8/300 line comment character: H8/300-Chars. (line 6)
  19953. * H8/300 line separator: H8/300-Chars. (line 8)
  19954. * H8/300 machine directives (none): H8/300 Directives. (line 6)
  19955. * H8/300 opcode summary: H8/300 Opcodes. (line 6)
  19956. * H8/300 options: H8/300 Options. (line 6)
  19957. * H8/300 registers: H8/300-Regs. (line 6)
  19958. * H8/300 size suffixes: H8/300 Opcodes. (line 160)
  19959. * H8/300 support: H8/300-Dependent. (line 6)
  19960. * H8/300H, assembling for: H8/300 Directives. (line 8)
  19961. * 'half' directive, Nios II: Nios II Directives. (line 10)
  19962. * 'half' directive, SPARC: Sparc-Directives. (line 17)
  19963. * 'half' directive, TIC54X: TIC54X-Directives. (line 109)
  19964. * hex character code ('\XD...'): Strings. (line 36)
  19965. * hexadecimal integers: Integers. (line 15)
  19966. * hexadecimal prefix, Z80: Z80-Chars. (line 15)
  19967. * 'hfloat' directive, VAX: VAX-directives. (line 21)
  19968. * 'hi' directive, Nios II: Nios II Relocations.
  19969. (line 20)
  19970. * 'hi' pseudo-op, V850: V850 Opcodes. (line 33)
  19971. * 'hi0' pseudo-op, V850: V850 Opcodes. (line 10)
  19972. * 'hiadj' directive, Nios II: Nios II Relocations.
  19973. (line 6)
  19974. * 'hidden' directive: Hidden. (line 6)
  19975. * 'high' directive, M32R: M32R-Directives. (line 18)
  19976. * 'hilo' pseudo-op, V850: V850 Opcodes. (line 55)
  19977. * HPPA directives not supported: HPPA Directives. (line 11)
  19978. * HPPA floating point (IEEE): HPPA Floating Point.
  19979. (line 6)
  19980. * HPPA Syntax: HPPA Options. (line 7)
  19981. * HPPA-only directives: HPPA Directives. (line 24)
  19982. * 'hword' directive: hword. (line 6)
  19983. * i370 support: ESA/390-Dependent. (line 6)
  19984. * i386 16-bit code: i386-16bit. (line 6)
  19985. * i386 arch directive: i386-Arch. (line 6)
  19986. * i386 att_syntax pseudo op: i386-Variations. (line 6)
  19987. * i386 conversion instructions: i386-Mnemonics. (line 39)
  19988. * i386 floating point: i386-Float. (line 6)
  19989. * i386 immediate operands: i386-Variations. (line 15)
  19990. * i386 instruction naming: i386-Mnemonics. (line 9)
  19991. * i386 instruction prefixes: i386-Prefixes. (line 6)
  19992. * i386 intel_syntax pseudo op: i386-Variations. (line 6)
  19993. * i386 jump optimization: i386-Jumps. (line 6)
  19994. * i386 jump, call, return: i386-Variations. (line 40)
  19995. * i386 jump/call operands: i386-Variations. (line 15)
  19996. * i386 line comment character: i386-Chars. (line 6)
  19997. * i386 line separator: i386-Chars. (line 18)
  19998. * i386 memory references: i386-Memory. (line 6)
  19999. * i386 mnemonic compatibility: i386-Mnemonics. (line 64)
  20000. * i386 'mul', 'imul' instructions: i386-Notes. (line 6)
  20001. * i386 options: i386-Options. (line 6)
  20002. * i386 register operands: i386-Variations. (line 15)
  20003. * i386 registers: i386-Regs. (line 6)
  20004. * i386 sections: i386-Variations. (line 46)
  20005. * i386 size suffixes: i386-Variations. (line 28)
  20006. * i386 source, destination operands: i386-Variations. (line 21)
  20007. * i386 support: i386-Dependent. (line 6)
  20008. * i386 syntax compatibility: i386-Variations. (line 6)
  20009. * i80386 support: i386-Dependent. (line 6)
  20010. * i860 line comment character: i860-Chars. (line 6)
  20011. * i860 line separator: i860-Chars. (line 14)
  20012. * i860 machine directives: Directives-i860. (line 6)
  20013. * i860 opcodes: Opcodes for i860. (line 6)
  20014. * i860 support: i860-Dependent. (line 6)
  20015. * i960 architecture options: Options-i960. (line 6)
  20016. * i960 branch recording: Options-i960. (line 22)
  20017. * i960 'callj' pseudo-opcode: callj-i960. (line 6)
  20018. * i960 compare and jump expansions: Compare-and-branch-i960.
  20019. (line 13)
  20020. * i960 compare/branch instructions: Compare-and-branch-i960.
  20021. (line 6)
  20022. * i960 floating point (IEEE): Floating Point-i960.
  20023. (line 6)
  20024. * i960 line comment character: i960-Chars. (line 6)
  20025. * i960 line separator: i960-Chars. (line 14)
  20026. * i960 machine directives: Directives-i960. (line 6)
  20027. * i960 opcodes: Opcodes for i960. (line 6)
  20028. * i960 options: Options-i960. (line 6)
  20029. * i960 support: i960-Dependent. (line 6)
  20030. * IA-64 line comment character: IA-64-Chars. (line 6)
  20031. * IA-64 line separator: IA-64-Chars. (line 8)
  20032. * IA-64 options: IA-64 Options. (line 6)
  20033. * IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6)
  20034. * IA-64 registers: IA-64-Regs. (line 6)
  20035. * IA-64 relocations: IA-64-Relocs. (line 6)
  20036. * IA-64 support: IA-64-Dependent. (line 6)
  20037. * IA-64 Syntax: IA-64 Options. (line 85)
  20038. * 'ident' directive: Ident. (line 6)
  20039. * identifiers, ARM: ARM-Chars. (line 19)
  20040. * identifiers, MSP 430: MSP430-Chars. (line 17)
  20041. * 'if' directive: If. (line 6)
  20042. * 'ifb' directive: If. (line 21)
  20043. * 'ifc' directive: If. (line 25)
  20044. * 'ifdef' directive: If. (line 16)
  20045. * 'ifeq' directive: If. (line 33)
  20046. * 'ifeqs' directive: If. (line 36)
  20047. * 'ifge' directive: If. (line 40)
  20048. * 'ifgt' directive: If. (line 44)
  20049. * 'ifle' directive: If. (line 48)
  20050. * 'iflt' directive: If. (line 52)
  20051. * 'ifnb' directive: If. (line 56)
  20052. * 'ifnc' directive: If. (line 61)
  20053. * 'ifndef' directive: If. (line 65)
  20054. * 'ifne' directive: If. (line 72)
  20055. * 'ifnes' directive: If. (line 76)
  20056. * 'ifnotdef' directive: If. (line 65)
  20057. * immediate character, AArch64: AArch64-Chars. (line 13)
  20058. * immediate character, ARM: ARM-Chars. (line 17)
  20059. * immediate character, M680x0: M68K-Chars. (line 13)
  20060. * immediate character, VAX: VAX-operands. (line 6)
  20061. * immediate fields, relaxation: Xtensa Immediate Relaxation.
  20062. (line 6)
  20063. * immediate operands, i386: i386-Variations. (line 15)
  20064. * immediate operands, x86-64: i386-Variations. (line 15)
  20065. * 'imul' instruction, i386: i386-Notes. (line 6)
  20066. * 'imul' instruction, x86-64: i386-Notes. (line 6)
  20067. * 'incbin' directive: Incbin. (line 6)
  20068. * 'include' directive: Include. (line 6)
  20069. * 'include' directive search path: I. (line 6)
  20070. * indirect character, VAX: VAX-operands. (line 9)
  20071. * infix operators: Infix Ops. (line 6)
  20072. * inhibiting interrupts, i386: i386-Prefixes. (line 36)
  20073. * input: Input Files. (line 6)
  20074. * input file linenumbers: Input Files. (line 35)
  20075. * instruction aliases, s390: s390 Aliases. (line 6)
  20076. * instruction bundle: Bundle directives. (line 9)
  20077. * instruction expansion, CRIS: CRIS-Expand. (line 6)
  20078. * instruction expansion, MMIX: MMIX-Expand. (line 6)
  20079. * instruction formats, s390: s390 Formats. (line 6)
  20080. * instruction marker, s390: s390 Instruction Marker.
  20081. (line 6)
  20082. * instruction mnemonics, s390: s390 Mnemonics. (line 6)
  20083. * instruction naming, i386: i386-Mnemonics. (line 9)
  20084. * instruction naming, x86-64: i386-Mnemonics. (line 9)
  20085. * instruction operand modifier, s390: s390 Operand Modifier.
  20086. (line 6)
  20087. * instruction operands, s390: s390 Operands. (line 6)
  20088. * instruction prefixes, i386: i386-Prefixes. (line 6)
  20089. * instruction set, M680x0: M68K-opcodes. (line 6)
  20090. * instruction set, M68HC11: M68HC11-opcodes. (line 6)
  20091. * instruction set, XGATE: XGATE-opcodes. (line 5)
  20092. * instruction summary, AVR: AVR Opcodes. (line 6)
  20093. * instruction summary, D10V: D10V-Opcodes. (line 6)
  20094. * instruction summary, D30V: D30V-Opcodes. (line 6)
  20095. * instruction summary, H8/300: H8/300 Opcodes. (line 6)
  20096. * instruction summary, LM32: LM32 Opcodes. (line 6)
  20097. * instruction summary, SH: SH Opcodes. (line 6)
  20098. * instruction summary, SH64: SH64 Opcodes. (line 6)
  20099. * instruction summary, Z8000: Z8000 Opcodes. (line 6)
  20100. * instruction syntax, s390: s390 Syntax. (line 6)
  20101. * instructions and directives: Statements. (line 20)
  20102. * 'int' directive: Int. (line 6)
  20103. * 'int' directive, H8/300: H8/300 Directives. (line 6)
  20104. * 'int' directive, i386: i386-Float. (line 21)
  20105. * 'int' directive, TIC54X: TIC54X-Directives. (line 109)
  20106. * 'int' directive, x86-64: i386-Float. (line 21)
  20107. * integer expressions: Integer Exprs. (line 6)
  20108. * integer, 16-byte: Octa. (line 6)
  20109. * integer, 8-byte: Quad. (line 9)
  20110. * integers: Integers. (line 6)
  20111. * integers, 16-bit: hword. (line 6)
  20112. * integers, 32-bit: Int. (line 6)
  20113. * integers, binary: Integers. (line 6)
  20114. * integers, decimal: Integers. (line 12)
  20115. * integers, hexadecimal: Integers. (line 15)
  20116. * integers, octal: Integers. (line 9)
  20117. * integers, one byte: Byte. (line 6)
  20118. * intel_syntax pseudo op, i386: i386-Variations. (line 6)
  20119. * intel_syntax pseudo op, x86-64: i386-Variations. (line 6)
  20120. * internal assembler sections: As Sections. (line 6)
  20121. * 'internal' directive: Internal. (line 6)
  20122. * interrupt link register, ARC: ARC-Regs. (line 27)
  20123. * Interrupt Vector Base address, ARC: ARC-Regs. (line 66)
  20124. * invalid input: Bug Criteria. (line 14)
  20125. * invocation summary: Overview. (line 6)
  20126. * IP2K architecture options: IP2K-Opts. (line 9)
  20127. * IP2K architecture options <1>: IP2K-Opts. (line 14)
  20128. * IP2K line comment character: IP2K-Chars. (line 6)
  20129. * IP2K line separator: IP2K-Chars. (line 14)
  20130. * IP2K options: IP2K-Opts. (line 6)
  20131. * IP2K support: IP2K-Dependent. (line 6)
  20132. * 'irp' directive: Irp. (line 6)
  20133. * 'irpc' directive: Irpc. (line 6)
  20134. * ISA options, SH64: SH64 Options. (line 6)
  20135. * joining text and data sections: R. (line 6)
  20136. * jump instructions, i386: i386-Mnemonics. (line 58)
  20137. * jump instructions, relaxation: Xtensa Jump Relaxation.
  20138. (line 6)
  20139. * jump instructions, x86-64: i386-Mnemonics. (line 58)
  20140. * jump optimization, i386: i386-Jumps. (line 6)
  20141. * jump optimization, x86-64: i386-Jumps. (line 6)
  20142. * jump/call operands, i386: i386-Variations. (line 15)
  20143. * jump/call operands, x86-64: i386-Variations. (line 15)
  20144. * 'L16SI' instructions, relaxation: Xtensa Immediate Relaxation.
  20145. (line 23)
  20146. * 'L16UI' instructions, relaxation: Xtensa Immediate Relaxation.
  20147. (line 23)
  20148. * 'L32I' instructions, relaxation: Xtensa Immediate Relaxation.
  20149. (line 23)
  20150. * 'L8UI' instructions, relaxation: Xtensa Immediate Relaxation.
  20151. (line 23)
  20152. * label (':'): Statements. (line 31)
  20153. * 'label' directive, TIC54X: TIC54X-Directives. (line 121)
  20154. * labels: Labels. (line 6)
  20155. * 'lcomm' directive: Lcomm. (line 6)
  20156. * 'lcomm' directive <1>: ARC Directives. (line 9)
  20157. * 'lcomm' directive, COFF: i386-Directives. (line 6)
  20158. * 'lcommon' directive, ARC: ARC Directives. (line 24)
  20159. * ld: Object. (line 15)
  20160. * 'ldouble' directive M680x0: M68K-Float. (line 17)
  20161. * 'ldouble' directive M68HC11: M68HC11-Float. (line 17)
  20162. * 'ldouble' directive XGATE: XGATE-Float. (line 16)
  20163. * 'ldouble' directive, TIC54X: TIC54X-Directives. (line 62)
  20164. * 'LDR reg,=<expr>' pseudo op, AArch64: AArch64 Opcodes. (line 9)
  20165. * 'LDR reg,=<label>' pseudo op, ARM: ARM Opcodes. (line 15)
  20166. * 'leafproc' directive, i960: Directives-i960. (line 18)
  20167. * 'length' directive, TIC54X: TIC54X-Directives. (line 125)
  20168. * length of symbols: Symbol Intro. (line 19)
  20169. * level 1 interrupt link register, ARC: ARC-Regs. (line 23)
  20170. * level 2 interrupt link register, ARC: ARC-Regs. (line 31)
  20171. * 'lflags' directive (ignored): Lflags. (line 6)
  20172. * line: ARC-Chars. (line 30)
  20173. * line comment character: Comments. (line 19)
  20174. * line comment character, AArch64: AArch64-Chars. (line 6)
  20175. * line comment character, Alpha: Alpha-Chars. (line 6)
  20176. * line comment character, ARC: ARC-Chars. (line 11)
  20177. * line comment character, ARM: ARM-Chars. (line 6)
  20178. * line comment character, AVR: AVR-Chars. (line 6)
  20179. * line comment character, CR16: CR16-Chars. (line 6)
  20180. * line comment character, D10V: D10V-Chars. (line 6)
  20181. * line comment character, D30V: D30V-Chars. (line 6)
  20182. * line comment character, Epiphany: Epiphany-Chars. (line 6)
  20183. * line comment character, H8/300: H8/300-Chars. (line 6)
  20184. * line comment character, i386: i386-Chars. (line 6)
  20185. * line comment character, i860: i860-Chars. (line 6)
  20186. * line comment character, i960: i960-Chars. (line 6)
  20187. * line comment character, IA-64: IA-64-Chars. (line 6)
  20188. * line comment character, IP2K: IP2K-Chars. (line 6)
  20189. * line comment character, LM32: LM32-Chars. (line 6)
  20190. * line comment character, M32C: M32C-Chars. (line 6)
  20191. * line comment character, M680x0: M68K-Chars. (line 6)
  20192. * line comment character, M68HC11: M68HC11-Syntax. (line 17)
  20193. * line comment character, Meta: Meta-Chars. (line 6)
  20194. * line comment character, MicroBlaze: MicroBlaze-Chars. (line 6)
  20195. * line comment character, MIPS: MIPS-Chars. (line 6)
  20196. * line comment character, MSP 430: MSP430-Chars. (line 6)
  20197. * line comment character, Nios II: Nios II Chars. (line 6)
  20198. * line comment character, NS32K: NS32K-Chars. (line 6)
  20199. * line comment character, PJ: PJ-Chars. (line 6)
  20200. * line comment character, PowerPC: PowerPC-Chars. (line 6)
  20201. * line comment character, RL78: RL78-Chars. (line 6)
  20202. * line comment character, RX: RX-Chars. (line 6)
  20203. * line comment character, s390: s390 Characters. (line 6)
  20204. * line comment character, SCORE: SCORE-Chars. (line 6)
  20205. * line comment character, SH: SH-Chars. (line 6)
  20206. * line comment character, SH64: SH64-Chars. (line 6)
  20207. * line comment character, Sparc: Sparc-Chars. (line 6)
  20208. * line comment character, TIC54X: TIC54X-Chars. (line 6)
  20209. * line comment character, TIC6X: TIC6X Syntax. (line 6)
  20210. * line comment character, V850: V850-Chars. (line 6)
  20211. * line comment character, VAX: VAX-Chars. (line 6)
  20212. * line comment character, Visium: Visium Characters. (line 6)
  20213. * line comment character, XGATE: XGATE-Syntax. (line 16)
  20214. * line comment character, XStormy16: XStormy16-Chars. (line 6)
  20215. * line comment character, Z80: Z80-Chars. (line 6)
  20216. * line comment character, Z8000: Z8000-Chars. (line 6)
  20217. * line comment characters, CRIS: CRIS-Chars. (line 6)
  20218. * line comment characters, MMIX: MMIX-Chars. (line 6)
  20219. * 'line' directive: Line. (line 6)
  20220. * 'line' directive, MSP 430: MSP430 Directives. (line 14)
  20221. * line numbers, in input files: Input Files. (line 35)
  20222. * line separator character: Statements. (line 6)
  20223. * line separator character, Nios II: Nios II Chars. (line 6)
  20224. * line separator, AArch64: AArch64-Chars. (line 10)
  20225. * line separator, Alpha: Alpha-Chars. (line 11)
  20226. * line separator, ARC: ARC-Chars. (line 27)
  20227. * line separator, ARM: ARM-Chars. (line 14)
  20228. * line separator, AVR: AVR-Chars. (line 14)
  20229. * line separator, CR16: CR16-Chars. (line 12)
  20230. * line separator, Epiphany: Epiphany-Chars. (line 14)
  20231. * line separator, H8/300: H8/300-Chars. (line 8)
  20232. * line separator, i386: i386-Chars. (line 18)
  20233. * line separator, i860: i860-Chars. (line 14)
  20234. * line separator, i960: i960-Chars. (line 14)
  20235. * line separator, IA-64: IA-64-Chars. (line 8)
  20236. * line separator, IP2K: IP2K-Chars. (line 14)
  20237. * line separator, LM32: LM32-Chars. (line 12)
  20238. * line separator, M32C: M32C-Chars. (line 14)
  20239. * line separator, M680x0: M68K-Chars. (line 20)
  20240. * line separator, M68HC11: M68HC11-Syntax. (line 26)
  20241. * line separator, Meta: Meta-Chars. (line 8)
  20242. * line separator, MicroBlaze: MicroBlaze-Chars. (line 14)
  20243. * line separator, MIPS: MIPS-Chars. (line 14)
  20244. * line separator, MSP 430: MSP430-Chars. (line 14)
  20245. * line separator, NS32K: NS32K-Chars. (line 18)
  20246. * line separator, PJ: PJ-Chars. (line 14)
  20247. * line separator, PowerPC: PowerPC-Chars. (line 18)
  20248. * line separator, RL78: RL78-Chars. (line 14)
  20249. * line separator, RX: RX-Chars. (line 14)
  20250. * line separator, s390: s390 Characters. (line 13)
  20251. * line separator, SCORE: SCORE-Chars. (line 14)
  20252. * line separator, SH: SH-Chars. (line 8)
  20253. * line separator, SH64: SH64-Chars. (line 13)
  20254. * line separator, Sparc: Sparc-Chars. (line 14)
  20255. * line separator, TIC54X: TIC54X-Chars. (line 17)
  20256. * line separator, TIC6X: TIC6X Syntax. (line 13)
  20257. * line separator, V850: V850-Chars. (line 13)
  20258. * line separator, VAX: VAX-Chars. (line 14)
  20259. * line separator, Visium: Visium Characters. (line 14)
  20260. * line separator, XGATE: XGATE-Syntax. (line 25)
  20261. * line separator, XStormy16: XStormy16-Chars. (line 14)
  20262. * line separator, Z80: Z80-Chars. (line 13)
  20263. * line separator, Z8000: Z8000-Chars. (line 13)
  20264. * lines starting with '#': Comments. (line 33)
  20265. * link register, ARC: ARC-Regs. (line 35)
  20266. * linker: Object. (line 15)
  20267. * linker, and assembler: Secs Background. (line 10)
  20268. * 'linkonce' directive: Linkonce. (line 6)
  20269. * 'list' directive: List. (line 6)
  20270. * 'list' directive, TIC54X: TIC54X-Directives. (line 129)
  20271. * listing control, turning off: Nolist. (line 6)
  20272. * listing control, turning on: List. (line 6)
  20273. * listing control: new page: Eject. (line 6)
  20274. * listing control: paper size: Psize. (line 6)
  20275. * listing control: subtitle: Sbttl. (line 6)
  20276. * listing control: title line: Title. (line 6)
  20277. * listings, enabling: a. (line 6)
  20278. * 'literal' directive: Literal Directive. (line 6)
  20279. * literal pool entries, s390: s390 Literal Pool Entries.
  20280. (line 6)
  20281. * 'literal_position' directive: Literal Position Directive.
  20282. (line 6)
  20283. * 'literal_prefix' directive: Literal Prefix Directive.
  20284. (line 6)
  20285. * little endian output, MIPS: Overview. (line 809)
  20286. * little endian output, PJ: Overview. (line 716)
  20287. * little-endian output, MIPS: MIPS Options. (line 13)
  20288. * little-endian output, TIC6X: TIC6X Options. (line 46)
  20289. * LM32 line comment character: LM32-Chars. (line 6)
  20290. * LM32 line separator: LM32-Chars. (line 12)
  20291. * LM32 modifiers: LM32-Modifiers. (line 6)
  20292. * LM32 opcode summary: LM32 Opcodes. (line 6)
  20293. * LM32 options (none): LM32 Options. (line 6)
  20294. * LM32 register names: LM32-Regs. (line 6)
  20295. * LM32 support: LM32-Dependent. (line 6)
  20296. * 'ln' directive: Ln. (line 6)
  20297. * 'lo' directive, Nios II: Nios II Relocations.
  20298. (line 23)
  20299. * 'lo' pseudo-op, V850: V850 Opcodes. (line 22)
  20300. * 'loc' directive: Loc. (line 6)
  20301. * local common symbols: Lcomm. (line 6)
  20302. * 'local' directive: Local. (line 6)
  20303. * local labels: Symbol Names. (line 43)
  20304. * local symbol names: Symbol Names. (line 30)
  20305. * local symbols, retaining in output: L. (line 6)
  20306. * location counter: Dot. (line 6)
  20307. * location counter, advancing: Org. (line 6)
  20308. * location counter, Z80: Z80-Chars. (line 15)
  20309. * 'loc_mark_labels' directive: Loc_mark_labels. (line 6)
  20310. * logical file name: File. (line 13)
  20311. * logical line number: Line. (line 6)
  20312. * logical line numbers: Comments. (line 33)
  20313. * 'long' directive: Long. (line 6)
  20314. * 'long' directive, i386: i386-Float. (line 21)
  20315. * 'long' directive, TIC54X: TIC54X-Directives. (line 133)
  20316. * 'long' directive, x86-64: i386-Float. (line 21)
  20317. * 'longcall' pseudo-op, V850: V850 Opcodes. (line 122)
  20318. * 'longcalls' directive: Longcalls Directive.
  20319. (line 6)
  20320. * 'longjump' pseudo-op, V850: V850 Opcodes. (line 128)
  20321. * loop counter, ARC: ARC-Regs. (line 41)
  20322. * 'loop' directive, TIC54X: TIC54X-Directives. (line 141)
  20323. * 'LOOP' instructions, alignment: Xtensa Automatic Alignment.
  20324. (line 6)
  20325. * 'low' directive, M32R: M32R-Directives. (line 9)
  20326. * 'lp' register, V850: V850-Regs. (line 68)
  20327. * lval: Z8000 Directives. (line 27)
  20328. * LWP, i386: i386-LWP. (line 6)
  20329. * LWP, x86-64: i386-LWP. (line 6)
  20330. * M16C architecture option: M32C-Opts. (line 12)
  20331. * M32C architecture option: M32C-Opts. (line 9)
  20332. * M32C line comment character: M32C-Chars. (line 6)
  20333. * M32C line separator: M32C-Chars. (line 14)
  20334. * M32C modifiers: M32C-Modifiers. (line 6)
  20335. * M32C options: M32C-Opts. (line 6)
  20336. * M32C support: M32C-Dependent. (line 6)
  20337. * M32R architecture options: M32R-Opts. (line 9)
  20338. * M32R architecture options <1>: M32R-Opts. (line 17)
  20339. * M32R architecture options <2>: M32R-Opts. (line 21)
  20340. * M32R directives: M32R-Directives. (line 6)
  20341. * M32R options: M32R-Opts. (line 6)
  20342. * M32R support: M32R-Dependent. (line 6)
  20343. * M32R warnings: M32R-Warnings. (line 6)
  20344. * M680x0 addressing modes: M68K-Syntax. (line 21)
  20345. * M680x0 architecture options: M68K-Opts. (line 99)
  20346. * M680x0 branch improvement: M68K-Branch. (line 6)
  20347. * M680x0 directives: M68K-Directives. (line 6)
  20348. * M680x0 floating point: M68K-Float. (line 6)
  20349. * M680x0 immediate character: M68K-Chars. (line 13)
  20350. * M680x0 line comment character: M68K-Chars. (line 6)
  20351. * M680x0 line separator: M68K-Chars. (line 20)
  20352. * M680x0 opcodes: M68K-opcodes. (line 6)
  20353. * M680x0 options: M68K-Opts. (line 6)
  20354. * M680x0 pseudo-opcodes: M68K-Branch. (line 6)
  20355. * M680x0 size modifiers: M68K-Syntax. (line 8)
  20356. * M680x0 support: M68K-Dependent. (line 6)
  20357. * M680x0 syntax: M68K-Syntax. (line 8)
  20358. * M68HC11 addressing modes: M68HC11-Syntax. (line 29)
  20359. * M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6)
  20360. * M68HC11 assembler directive .far: M68HC11-Directives. (line 20)
  20361. * M68HC11 assembler directive .interrupt: M68HC11-Directives.
  20362. (line 26)
  20363. * M68HC11 assembler directive .mode: M68HC11-Directives. (line 16)
  20364. * M68HC11 assembler directive .relax: M68HC11-Directives. (line 10)
  20365. * M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31)
  20366. * M68HC11 assembler directives: M68HC11-Directives. (line 6)
  20367. * M68HC11 branch improvement: M68HC11-Branch. (line 6)
  20368. * M68HC11 floating point: M68HC11-Float. (line 6)
  20369. * M68HC11 line comment character: M68HC11-Syntax. (line 17)
  20370. * M68HC11 line separator: M68HC11-Syntax. (line 26)
  20371. * M68HC11 modifiers: M68HC11-Modifiers. (line 6)
  20372. * M68HC11 opcodes: M68HC11-opcodes. (line 6)
  20373. * M68HC11 options: M68HC11-Opts. (line 6)
  20374. * M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6)
  20375. * M68HC11 syntax: M68HC11-Syntax. (line 6)
  20376. * M68HC12 assembler directives: M68HC11-Directives. (line 6)
  20377. * 'mA6' command line option, ARC: ARC Options. (line 14)
  20378. * 'mA7' command line option, ARC: ARC Options. (line 39)
  20379. * machine dependencies: Machine Dependencies.
  20380. (line 6)
  20381. * machine directives, AArch64: AArch64 Directives. (line 6)
  20382. * machine directives, ARC: ARC Directives. (line 6)
  20383. * machine directives, ARM: ARM Directives. (line 6)
  20384. * machine directives, H8/300 (none): H8/300 Directives. (line 6)
  20385. * machine directives, i860: Directives-i860. (line 6)
  20386. * machine directives, i960: Directives-i960. (line 6)
  20387. * machine directives, MSP 430: MSP430 Directives. (line 6)
  20388. * machine directives, Nios II: Nios II Directives. (line 6)
  20389. * machine directives, SH: SH Directives. (line 6)
  20390. * machine directives, SH64: SH64 Directives. (line 9)
  20391. * machine directives, SPARC: Sparc-Directives. (line 6)
  20392. * machine directives, TIC54X: TIC54X-Directives. (line 6)
  20393. * machine directives, TIC6X: TIC6X Directives. (line 6)
  20394. * machine directives, TILE-Gx: TILE-Gx Directives. (line 6)
  20395. * machine directives, TILEPro: TILEPro Directives. (line 6)
  20396. * machine directives, V850: V850 Directives. (line 6)
  20397. * machine directives, VAX: VAX-directives. (line 6)
  20398. * machine directives, x86: i386-Directives. (line 6)
  20399. * machine directives, XStormy16: XStormy16 Directives.
  20400. (line 6)
  20401. * machine independent directives: Pseudo Ops. (line 6)
  20402. * machine instructions (not covered): Manual. (line 14)
  20403. * machine relocations, Nios II: Nios II Relocations.
  20404. (line 6)
  20405. * machine-independent syntax: Syntax. (line 6)
  20406. * 'macro' directive: Macro. (line 28)
  20407. * 'macro' directive, TIC54X: TIC54X-Directives. (line 151)
  20408. * macros: Macro. (line 6)
  20409. * macros, count executed: Macro. (line 142)
  20410. * Macros, MSP 430: MSP430-Macros. (line 6)
  20411. * macros, TIC54X: TIC54X-Macros. (line 6)
  20412. * make rules: MD. (line 6)
  20413. * manual, structure and purpose: Manual. (line 6)
  20414. * 'marc600' command line option, ARC: ARC Options. (line 14)
  20415. * 'mARC601' command line option, ARC: ARC Options. (line 27)
  20416. * 'mARC700' command line option, ARC: ARC Options. (line 39)
  20417. * 'march' command line option, Nios II: Nios II Options. (line 28)
  20418. * math builtins, TIC54X: TIC54X-Builtins. (line 6)
  20419. * Maximum number of continuation lines: listing. (line 34)
  20420. * 'mEM' command line option, ARC: ARC Options. (line 42)
  20421. * memory references, i386: i386-Memory. (line 6)
  20422. * memory references, x86-64: i386-Memory. (line 6)
  20423. * memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6)
  20424. * merging text and data sections: R. (line 6)
  20425. * messages from assembler: Errors. (line 6)
  20426. * Meta architectures: Meta Options. (line 6)
  20427. * Meta line comment character: Meta-Chars. (line 6)
  20428. * Meta line separator: Meta-Chars. (line 8)
  20429. * Meta options: Meta Options. (line 6)
  20430. * Meta registers: Meta-Regs. (line 6)
  20431. * Meta support: Meta-Dependent. (line 6)
  20432. * 'mHS' command line option, ARC: ARC Options. (line 64)
  20433. * MicroBlaze architectures: MicroBlaze-Dependent.
  20434. (line 6)
  20435. * MicroBlaze directives: MicroBlaze Directives.
  20436. (line 6)
  20437. * MicroBlaze line comment character: MicroBlaze-Chars. (line 6)
  20438. * MicroBlaze line separator: MicroBlaze-Chars. (line 14)
  20439. * MicroBlaze support: MicroBlaze-Dependent.
  20440. (line 12)
  20441. * minus, permitted arguments: Infix Ops. (line 50)
  20442. * MIPS 32-bit microMIPS instruction generation override: MIPS assembly options.
  20443. (line 18)
  20444. * MIPS architecture options: MIPS Options. (line 29)
  20445. * MIPS big-endian output: MIPS Options. (line 13)
  20446. * MIPS CPU override: MIPS ISA. (line 18)
  20447. * MIPS directives to override command line options: MIPS assembly options.
  20448. (line 6)
  20449. * MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides.
  20450. (line 21)
  20451. * MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides.
  20452. (line 26)
  20453. * MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides.
  20454. (line 31)
  20455. * MIPS endianness: Overview. (line 806)
  20456. * MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides.
  20457. (line 57)
  20458. * MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings.
  20459. (line 6)
  20460. * MIPS ISA: Overview. (line 812)
  20461. * MIPS ISA override: MIPS ISA. (line 6)
  20462. * MIPS line comment character: MIPS-Chars. (line 6)
  20463. * MIPS line separator: MIPS-Chars. (line 14)
  20464. * MIPS little-endian output: MIPS Options. (line 13)
  20465. * MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides.
  20466. (line 42)
  20467. * MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides.
  20468. (line 16)
  20469. * MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides.
  20470. (line 6)
  20471. * MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides.
  20472. (line 37)
  20473. * MIPS option stack: MIPS Option Stack. (line 6)
  20474. * MIPS processor: MIPS-Dependent. (line 6)
  20475. * MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides.
  20476. (line 47)
  20477. * MIT: M68K-Syntax. (line 6)
  20478. * 'mlib' directive, TIC54X: TIC54X-Directives. (line 157)
  20479. * 'mlist' directive, TIC54X: TIC54X-Directives. (line 162)
  20480. * MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137)
  20481. * MMIX assembler directive BYTE: MMIX-Pseudos. (line 101)
  20482. * MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137)
  20483. * MMIX assembler directive GREG: MMIX-Pseudos. (line 53)
  20484. * MMIX assembler directive IS: MMIX-Pseudos. (line 44)
  20485. * MMIX assembler directive LOC: MMIX-Pseudos. (line 7)
  20486. * MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29)
  20487. * MMIX assembler directive OCTA: MMIX-Pseudos. (line 113)
  20488. * MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125)
  20489. * MMIX assembler directive TETRA: MMIX-Pseudos. (line 113)
  20490. * MMIX assembler directive WYDE: MMIX-Pseudos. (line 113)
  20491. * MMIX assembler directives: MMIX-Pseudos. (line 6)
  20492. * MMIX line comment characters: MMIX-Chars. (line 6)
  20493. * MMIX options: MMIX-Opts. (line 6)
  20494. * MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137)
  20495. * MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101)
  20496. * MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137)
  20497. * MMIX pseudo-op GREG: MMIX-Pseudos. (line 53)
  20498. * MMIX pseudo-op IS: MMIX-Pseudos. (line 44)
  20499. * MMIX pseudo-op LOC: MMIX-Pseudos. (line 7)
  20500. * MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29)
  20501. * MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113)
  20502. * MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125)
  20503. * MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113)
  20504. * MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113)
  20505. * MMIX pseudo-ops: MMIX-Pseudos. (line 6)
  20506. * MMIX register names: MMIX-Regs. (line 6)
  20507. * MMIX support: MMIX-Dependent. (line 6)
  20508. * mmixal differences: MMIX-mmixal. (line 6)
  20509. * 'mmregs' directive, TIC54X: TIC54X-Directives. (line 167)
  20510. * 'mmsg' directive, TIC54X: TIC54X-Directives. (line 75)
  20511. * MMX, i386: i386-SIMD. (line 6)
  20512. * MMX, x86-64: i386-SIMD. (line 6)
  20513. * mnemonic compatibility, i386: i386-Mnemonics. (line 64)
  20514. * mnemonic suffixes, i386: i386-Variations. (line 28)
  20515. * mnemonic suffixes, x86-64: i386-Variations. (line 28)
  20516. * mnemonics for opcodes, VAX: VAX-opcodes. (line 6)
  20517. * mnemonics, AVR: AVR Opcodes. (line 6)
  20518. * mnemonics, D10V: D10V-Opcodes. (line 6)
  20519. * mnemonics, D30V: D30V-Opcodes. (line 6)
  20520. * mnemonics, H8/300: H8/300 Opcodes. (line 6)
  20521. * mnemonics, LM32: LM32 Opcodes. (line 6)
  20522. * mnemonics, SH: SH Opcodes. (line 6)
  20523. * mnemonics, SH64: SH64 Opcodes. (line 6)
  20524. * mnemonics, Z8000: Z8000 Opcodes. (line 6)
  20525. * 'mnolist' directive, TIC54X: TIC54X-Directives. (line 162)
  20526. * 'mnps400' command line option, ARC: ARC Options. (line 79)
  20527. * modifiers, M32C: M32C-Modifiers. (line 6)
  20528. * Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6)
  20529. * 'MOVI' instructions, relaxation: Xtensa Immediate Relaxation.
  20530. (line 12)
  20531. * MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations.
  20532. (line 6)
  20533. * MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21)
  20534. * MRI compatibility mode: M. (line 6)
  20535. * 'mri' directive: MRI. (line 6)
  20536. * MRI mode, temporarily: MRI. (line 6)
  20537. * MSP 430 floating point (IEEE): MSP430 Floating Point.
  20538. (line 6)
  20539. * MSP 430 identifiers: MSP430-Chars. (line 17)
  20540. * MSP 430 line comment character: MSP430-Chars. (line 6)
  20541. * MSP 430 line separator: MSP430-Chars. (line 14)
  20542. * MSP 430 machine directives: MSP430 Directives. (line 6)
  20543. * MSP 430 macros: MSP430-Macros. (line 6)
  20544. * MSP 430 opcodes: MSP430 Opcodes. (line 6)
  20545. * MSP 430 options (none): MSP430 Options. (line 6)
  20546. * MSP 430 profiling capability: MSP430 Profiling Capability.
  20547. (line 6)
  20548. * MSP 430 register names: MSP430-Regs. (line 6)
  20549. * MSP 430 support: MSP430-Dependent. (line 6)
  20550. * MSP430 Assembler Extensions: MSP430-Ext. (line 6)
  20551. * 'mul' instruction, i386: i386-Notes. (line 6)
  20552. * 'mul' instruction, x86-64: i386-Notes. (line 6)
  20553. * N32K support: NS32K-Dependent. (line 6)
  20554. * name: Z8000 Directives. (line 18)
  20555. * named section: Section. (line 6)
  20556. * named sections: Ld Sections. (line 8)
  20557. * names, symbol: Symbol Names. (line 6)
  20558. * naming object file: o. (line 6)
  20559. * NDS32 options: NDS32 Options. (line 6)
  20560. * NDS32 processor: NDS32-Dependent. (line 6)
  20561. * new page, in listings: Eject. (line 6)
  20562. * 'newblock' directive, TIC54X: TIC54X-Directives. (line 173)
  20563. * newline ('\n'): Strings. (line 21)
  20564. * newline, required at file end: Statements. (line 14)
  20565. * Nios II line comment character: Nios II Chars. (line 6)
  20566. * Nios II line separator character: Nios II Chars. (line 6)
  20567. * Nios II machine directives: Nios II Directives. (line 6)
  20568. * Nios II machine relocations: Nios II Relocations.
  20569. (line 6)
  20570. * Nios II opcodes: Nios II Opcodes. (line 6)
  20571. * Nios II options: Nios II Options. (line 6)
  20572. * Nios II support: NiosII-Dependent. (line 6)
  20573. * Nios support: NiosII-Dependent. (line 6)
  20574. * 'no-absolute-literals' directive: Absolute Literals Directive.
  20575. (line 6)
  20576. * 'no-longcalls' directive: Longcalls Directive.
  20577. (line 6)
  20578. * 'no-relax' command line option, Nios II: Nios II Options. (line 19)
  20579. * 'no-schedule' directive: Schedule Directive. (line 6)
  20580. * 'no-transform' directive: Transform Directive.
  20581. (line 6)
  20582. * 'nolist' directive: Nolist. (line 6)
  20583. * 'nolist' directive, TIC54X: TIC54X-Directives. (line 129)
  20584. * 'NOP' pseudo op, ARM: ARM Opcodes. (line 9)
  20585. * notes for Alpha: Alpha Notes. (line 6)
  20586. * NS32K line comment character: NS32K-Chars. (line 6)
  20587. * NS32K line separator: NS32K-Chars. (line 18)
  20588. * null-terminated strings: Asciz. (line 6)
  20589. * number constants: Numbers. (line 6)
  20590. * number of macros executed: Macro. (line 142)
  20591. * numbered subsections: Sub-Sections. (line 6)
  20592. * numbers, 16-bit: hword. (line 6)
  20593. * numeric values: Expressions. (line 6)
  20594. * 'nword' directive, SPARC: Sparc-Directives. (line 20)
  20595. * object attributes: Object Attributes. (line 6)
  20596. * object file: Object. (line 6)
  20597. * object file format: Object Formats. (line 6)
  20598. * object file name: o. (line 6)
  20599. * object file, after errors: Z. (line 6)
  20600. * obsolescent directives: Deprecated. (line 6)
  20601. * 'octa' directive: Octa. (line 6)
  20602. * octal character code ('\DDD'): Strings. (line 30)
  20603. * octal integers: Integers. (line 9)
  20604. * 'offset' directive: Offset. (line 6)
  20605. * 'offset' directive, V850: V850 Directives. (line 6)
  20606. * opcode mnemonics, VAX: VAX-opcodes. (line 6)
  20607. * opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6)
  20608. * opcode names, TILEPro: TILEPro Opcodes. (line 6)
  20609. * opcode names, Xtensa: Xtensa Opcodes. (line 6)
  20610. * opcode summary, AVR: AVR Opcodes. (line 6)
  20611. * opcode summary, D10V: D10V-Opcodes. (line 6)
  20612. * opcode summary, D30V: D30V-Opcodes. (line 6)
  20613. * opcode summary, H8/300: H8/300 Opcodes. (line 6)
  20614. * opcode summary, LM32: LM32 Opcodes. (line 6)
  20615. * opcode summary, SH: SH Opcodes. (line 6)
  20616. * opcode summary, SH64: SH64 Opcodes. (line 6)
  20617. * opcode summary, Z8000: Z8000 Opcodes. (line 6)
  20618. * opcodes for AArch64: AArch64 Opcodes. (line 6)
  20619. * opcodes for ARC: ARC Opcodes. (line 6)
  20620. * opcodes for ARM: ARM Opcodes. (line 6)
  20621. * opcodes for MSP 430: MSP430 Opcodes. (line 6)
  20622. * opcodes for Nios II: Nios II Opcodes. (line 6)
  20623. * opcodes for V850: V850 Opcodes. (line 6)
  20624. * opcodes, i860: Opcodes for i860. (line 6)
  20625. * opcodes, i960: Opcodes for i960. (line 6)
  20626. * opcodes, M680x0: M68K-opcodes. (line 6)
  20627. * opcodes, M68HC11: M68HC11-opcodes. (line 6)
  20628. * operand delimiters, i386: i386-Variations. (line 15)
  20629. * operand delimiters, x86-64: i386-Variations. (line 15)
  20630. * operand notation, VAX: VAX-operands. (line 6)
  20631. * operands in expressions: Arguments. (line 6)
  20632. * operator precedence: Infix Ops. (line 11)
  20633. * operators, in expressions: Operators. (line 6)
  20634. * operators, permitted arguments: Infix Ops. (line 6)
  20635. * optimization, D10V: Overview. (line 579)
  20636. * optimization, D30V: Overview. (line 584)
  20637. * optimizations: Xtensa Optimizations.
  20638. (line 6)
  20639. * 'option' directive, TIC54X: TIC54X-Directives. (line 177)
  20640. * option summary: Overview. (line 6)
  20641. * options for AArch64 (none): AArch64 Options. (line 6)
  20642. * options for Alpha: Alpha Options. (line 6)
  20643. * options for ARC: ARC Options. (line 6)
  20644. * options for ARM (none): ARM Options. (line 6)
  20645. * options for AVR (none): AVR Options. (line 6)
  20646. * options for Blackfin (none): Blackfin Options. (line 6)
  20647. * options for i386: i386-Options. (line 6)
  20648. * options for IA-64: IA-64 Options. (line 6)
  20649. * options for LM32 (none): LM32 Options. (line 6)
  20650. * options for Meta: Meta Options. (line 6)
  20651. * options for MSP430 (none): MSP430 Options. (line 6)
  20652. * options for NDS32: NDS32 Options. (line 6)
  20653. * options for Nios II: Nios II Options. (line 6)
  20654. * options for PDP-11: PDP-11-Options. (line 6)
  20655. * options for PowerPC: PowerPC-Opts. (line 6)
  20656. * options for s390: s390 Options. (line 6)
  20657. * options for SCORE: SCORE-Opts. (line 6)
  20658. * options for SPARC: Sparc-Opts. (line 6)
  20659. * options for TIC6X: TIC6X Options. (line 6)
  20660. * options for V850 (none): V850 Options. (line 6)
  20661. * options for VAX/VMS: VAX-Opts. (line 42)
  20662. * options for Visium: Visium Options. (line 6)
  20663. * options for x86-64: i386-Options. (line 6)
  20664. * options for Z80: Z80 Options. (line 6)
  20665. * options, all versions of assembler: Invoking. (line 6)
  20666. * options, command line: Command Line. (line 13)
  20667. * options, CRIS: CRIS-Opts. (line 6)
  20668. * options, D10V: D10V-Opts. (line 6)
  20669. * options, D30V: D30V-Opts. (line 6)
  20670. * options, Epiphany: Epiphany Options. (line 6)
  20671. * options, H8/300: H8/300 Options. (line 6)
  20672. * options, i960: Options-i960. (line 6)
  20673. * options, IP2K: IP2K-Opts. (line 6)
  20674. * options, M32C: M32C-Opts. (line 6)
  20675. * options, M32R: M32R-Opts. (line 6)
  20676. * options, M680x0: M68K-Opts. (line 6)
  20677. * options, M68HC11: M68HC11-Opts. (line 6)
  20678. * options, MMIX: MMIX-Opts. (line 6)
  20679. * options, PJ: PJ Options. (line 6)
  20680. * options, RL78: RL78-Opts. (line 6)
  20681. * options, RX: RX-Opts. (line 6)
  20682. * options, SH: SH Options. (line 6)
  20683. * options, SH64: SH64 Options. (line 6)
  20684. * options, TIC54X: TIC54X-Opts. (line 6)
  20685. * options, XGATE: XGATE-Opts. (line 6)
  20686. * options, Z8000: Z8000 Options. (line 6)
  20687. * 'org' directive: Org. (line 6)
  20688. * other attribute, of 'a.out' symbol: Symbol Other. (line 6)
  20689. * output file: Object. (line 6)
  20690. * output section padding: no-pad-sections. (line 6)
  20691. * 'p2align' directive: P2align. (line 6)
  20692. * 'p2alignl' directive: P2align. (line 28)
  20693. * 'p2alignw' directive: P2align. (line 28)
  20694. * padding the location counter: Align. (line 6)
  20695. * padding the location counter given a power of two: P2align.
  20696. (line 6)
  20697. * padding the location counter given number of bytes: Balign.
  20698. (line 6)
  20699. * page, in listings: Eject. (line 6)
  20700. * paper size, for listings: Psize. (line 6)
  20701. * paths for '.include': I. (line 6)
  20702. * patterns, writing in memory: Fill. (line 6)
  20703. * PDP-11 comments: PDP-11-Syntax. (line 16)
  20704. * PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13)
  20705. * PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10)
  20706. * PDP-11 instruction naming: PDP-11-Mnemonics. (line 6)
  20707. * PDP-11 line separator: PDP-11-Syntax. (line 19)
  20708. * PDP-11 support: PDP-11-Dependent. (line 6)
  20709. * PDP-11 syntax: PDP-11-Syntax. (line 6)
  20710. * PIC code generation for ARM: ARM Options. (line 188)
  20711. * PIC code generation for M32R: M32R-Opts. (line 42)
  20712. * PIC selection, MIPS: MIPS Options. (line 21)
  20713. * PJ endianness: Overview. (line 713)
  20714. * PJ line comment character: PJ-Chars. (line 6)
  20715. * PJ line separator: PJ-Chars. (line 14)
  20716. * PJ options: PJ Options. (line 6)
  20717. * PJ support: PJ-Dependent. (line 6)
  20718. * plus, permitted arguments: Infix Ops. (line 45)
  20719. * 'popsection' directive: PopSection. (line 6)
  20720. * Position-independent code, CRIS: CRIS-Opts. (line 27)
  20721. * Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6)
  20722. * PowerPC architectures: PowerPC-Opts. (line 6)
  20723. * PowerPC directives: PowerPC-Pseudo. (line 6)
  20724. * PowerPC line comment character: PowerPC-Chars. (line 6)
  20725. * PowerPC line separator: PowerPC-Chars. (line 18)
  20726. * PowerPC options: PowerPC-Opts. (line 6)
  20727. * PowerPC support: PPC-Dependent. (line 6)
  20728. * precedence of operators: Infix Ops. (line 11)
  20729. * precision, floating point: Flonums. (line 6)
  20730. * prefix operators: Prefix Ops. (line 6)
  20731. * prefixes, i386: i386-Prefixes. (line 6)
  20732. * preprocessing: Preprocessing. (line 6)
  20733. * preprocessing, turning on and off: Preprocessing. (line 26)
  20734. * 'previous' directive: Previous. (line 6)
  20735. * primary attributes, COFF symbols: COFF Symbols. (line 13)
  20736. * 'print' directive: Print. (line 6)
  20737. * 'proc' directive, SPARC: Sparc-Directives. (line 25)
  20738. * Processor Identification register, ARC: ARC-Regs. (line 51)
  20739. * 'profiler' directive, MSP 430: MSP430 Directives. (line 26)
  20740. * profiling capability for MSP 430: MSP430 Profiling Capability.
  20741. (line 6)
  20742. * Program Counter, ARC: ARC-Regs. (line 54)
  20743. * 'protected' directive: Protected. (line 6)
  20744. * pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50)
  20745. * pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12)
  20746. * pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18)
  20747. * pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137)
  20748. * pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101)
  20749. * pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137)
  20750. * pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53)
  20751. * pseudo-op IS, MMIX: MMIX-Pseudos. (line 44)
  20752. * pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7)
  20753. * pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29)
  20754. * pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113)
  20755. * pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125)
  20756. * pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113)
  20757. * pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113)
  20758. * pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6)
  20759. * pseudo-opcodes, M680x0: M68K-Branch. (line 6)
  20760. * pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6)
  20761. * pseudo-ops for branch, VAX: VAX-branch. (line 6)
  20762. * pseudo-ops, CRIS: CRIS-Pseudos. (line 6)
  20763. * pseudo-ops, machine independent: Pseudo Ops. (line 6)
  20764. * pseudo-ops, MMIX: MMIX-Pseudos. (line 6)
  20765. * 'psize' directive: Psize. (line 6)
  20766. * PSR bits: IA-64-Bits. (line 6)
  20767. * 'pstring' directive, TIC54X: TIC54X-Directives. (line 206)
  20768. * 'psw' register, V850: V850-Regs. (line 80)
  20769. * 'purgem' directive: Purgem. (line 6)
  20770. * purpose of GNU assembler: GNU Assembler. (line 12)
  20771. * 'pushsection' directive: PushSection. (line 6)
  20772. * 'quad' directive: Quad. (line 6)
  20773. * 'quad' directive, i386: i386-Float. (line 21)
  20774. * 'quad' directive, x86-64: i386-Float. (line 21)
  20775. * real-mode code, i386: i386-16bit. (line 6)
  20776. * 'ref' directive, TIC54X: TIC54X-Directives. (line 101)
  20777. * 'refsym' directive, MSP 430: MSP430 Directives. (line 30)
  20778. * 'register' directive, SPARC: Sparc-Directives. (line 29)
  20779. * register name prefix character, ARC: ARC-Chars. (line 7)
  20780. * register names, AArch64: AArch64-Regs. (line 6)
  20781. * register names, Alpha: Alpha-Regs. (line 6)
  20782. * register names, ARC: ARC-Regs. (line 6)
  20783. * register names, ARM: ARM-Regs. (line 6)
  20784. * register names, AVR: AVR-Regs. (line 6)
  20785. * register names, CRIS: CRIS-Regs. (line 6)
  20786. * register names, H8/300: H8/300-Regs. (line 6)
  20787. * register names, IA-64: IA-64-Regs. (line 6)
  20788. * register names, LM32: LM32-Regs. (line 6)
  20789. * register names, MMIX: MMIX-Regs. (line 6)
  20790. * register names, MSP 430: MSP430-Regs. (line 6)
  20791. * register names, Sparc: Sparc-Regs. (line 6)
  20792. * register names, TILE-Gx: TILE-Gx Registers. (line 6)
  20793. * register names, TILEPro: TILEPro Registers. (line 6)
  20794. * register names, V850: V850-Regs. (line 6)
  20795. * register names, VAX: VAX-operands. (line 17)
  20796. * register names, Visium: Visium Registers. (line 6)
  20797. * register names, Xtensa: Xtensa Registers. (line 6)
  20798. * register names, Z80: Z80-Regs. (line 6)
  20799. * register naming, s390: s390 Register. (line 6)
  20800. * register operands, i386: i386-Variations. (line 15)
  20801. * register operands, x86-64: i386-Variations. (line 15)
  20802. * registers, D10V: D10V-Regs. (line 6)
  20803. * registers, D30V: D30V-Regs. (line 6)
  20804. * registers, i386: i386-Regs. (line 6)
  20805. * registers, Meta: Meta-Regs. (line 6)
  20806. * registers, SH: SH-Regs. (line 6)
  20807. * registers, SH64: SH64-Regs. (line 6)
  20808. * registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6)
  20809. * registers, x86-64: i386-Regs. (line 6)
  20810. * registers, Z8000: Z8000-Regs. (line 6)
  20811. * 'relax-all' command line option, Nios II: Nios II Options. (line 13)
  20812. * 'relax-section' command line option, Nios II: Nios II Options.
  20813. (line 6)
  20814. * relaxation: Xtensa Relaxation. (line 6)
  20815. * relaxation of 'ADDI' instructions: Xtensa Immediate Relaxation.
  20816. (line 43)
  20817. * relaxation of branch instructions: Xtensa Branch Relaxation.
  20818. (line 6)
  20819. * relaxation of call instructions: Xtensa Call Relaxation.
  20820. (line 6)
  20821. * relaxation of immediate fields: Xtensa Immediate Relaxation.
  20822. (line 6)
  20823. * relaxation of jump instructions: Xtensa Jump Relaxation.
  20824. (line 6)
  20825. * relaxation of 'L16SI' instructions: Xtensa Immediate Relaxation.
  20826. (line 23)
  20827. * relaxation of 'L16UI' instructions: Xtensa Immediate Relaxation.
  20828. (line 23)
  20829. * relaxation of 'L32I' instructions: Xtensa Immediate Relaxation.
  20830. (line 23)
  20831. * relaxation of 'L8UI' instructions: Xtensa Immediate Relaxation.
  20832. (line 23)
  20833. * relaxation of 'MOVI' instructions: Xtensa Immediate Relaxation.
  20834. (line 12)
  20835. * 'reloc' directive: Reloc. (line 6)
  20836. * relocation: Sections. (line 6)
  20837. * relocation example: Ld Sections. (line 40)
  20838. * relocations, AArch64: AArch64-Relocations.
  20839. (line 6)
  20840. * relocations, Alpha: Alpha-Relocs. (line 6)
  20841. * relocations, Sparc: Sparc-Relocs. (line 6)
  20842. * repeat prefixes, i386: i386-Prefixes. (line 44)
  20843. * reporting bugs in assembler: Reporting Bugs. (line 6)
  20844. * 'rept' directive: Rept. (line 6)
  20845. * 'reserve' directive, SPARC: Sparc-Directives. (line 39)
  20846. * return instructions, i386: i386-Variations. (line 40)
  20847. * return instructions, x86-64: i386-Variations. (line 40)
  20848. * REX prefixes, i386: i386-Prefixes. (line 46)
  20849. * RISC-V support: RISC-V-Dependent. (line 6)
  20850. * RL78 assembler directives: RL78-Directives. (line 6)
  20851. * RL78 line comment character: RL78-Chars. (line 6)
  20852. * RL78 line separator: RL78-Chars. (line 14)
  20853. * RL78 modifiers: RL78-Modifiers. (line 6)
  20854. * RL78 options: RL78-Opts. (line 6)
  20855. * RL78 support: RL78-Dependent. (line 6)
  20856. * rsect: Z8000 Directives. (line 51)
  20857. * RX assembler directive .3byte: RX-Directives. (line 9)
  20858. * RX assembler directive .fetchalign: RX-Directives. (line 13)
  20859. * RX assembler directives: RX-Directives. (line 6)
  20860. * RX floating point: RX-Float. (line 6)
  20861. * RX line comment character: RX-Chars. (line 6)
  20862. * RX line separator: RX-Chars. (line 14)
  20863. * RX modifiers: RX-Modifiers. (line 6)
  20864. * RX options: RX-Opts. (line 6)
  20865. * RX support: RX-Dependent. (line 6)
  20866. * s390 floating point: s390 Floating Point.
  20867. (line 6)
  20868. * s390 instruction aliases: s390 Aliases. (line 6)
  20869. * s390 instruction formats: s390 Formats. (line 6)
  20870. * s390 instruction marker: s390 Instruction Marker.
  20871. (line 6)
  20872. * s390 instruction mnemonics: s390 Mnemonics. (line 6)
  20873. * s390 instruction operand modifier: s390 Operand Modifier.
  20874. (line 6)
  20875. * s390 instruction operands: s390 Operands. (line 6)
  20876. * s390 instruction syntax: s390 Syntax. (line 6)
  20877. * s390 line comment character: s390 Characters. (line 6)
  20878. * s390 line separator: s390 Characters. (line 13)
  20879. * s390 literal pool entries: s390 Literal Pool Entries.
  20880. (line 6)
  20881. * s390 options: s390 Options. (line 6)
  20882. * s390 register naming: s390 Register. (line 6)
  20883. * s390 support: S/390-Dependent. (line 6)
  20884. * Saved User Stack Pointer, ARC: ARC-Regs. (line 73)
  20885. * 'sblock' directive, TIC54X: TIC54X-Directives. (line 180)
  20886. * 'sbttl' directive: Sbttl. (line 6)
  20887. * 'schedule' directive: Schedule Directive. (line 6)
  20888. * 'scl' directive: Scl. (line 6)
  20889. * SCORE architectures: SCORE-Opts. (line 6)
  20890. * SCORE directives: SCORE-Pseudo. (line 6)
  20891. * SCORE line comment character: SCORE-Chars. (line 6)
  20892. * SCORE line separator: SCORE-Chars. (line 14)
  20893. * SCORE options: SCORE-Opts. (line 6)
  20894. * SCORE processor: SCORE-Dependent. (line 6)
  20895. * 'sdaoff' pseudo-op, V850: V850 Opcodes. (line 65)
  20896. * search path for '.include': I. (line 6)
  20897. * 'sect' directive, TIC54X: TIC54X-Directives. (line 186)
  20898. * 'section' directive (COFF version): Section. (line 16)
  20899. * 'section' directive (ELF version): Section. (line 67)
  20900. * 'section' directive, V850: V850 Directives. (line 9)
  20901. * section name substitution: Section. (line 71)
  20902. * section override prefixes, i386: i386-Prefixes. (line 23)
  20903. * Section Stack: PopSection. (line 6)
  20904. * Section Stack <1>: Previous. (line 6)
  20905. * Section Stack <2>: PushSection. (line 6)
  20906. * Section Stack <3>: Section. (line 62)
  20907. * Section Stack <4>: SubSection. (line 6)
  20908. * section-relative addressing: Secs Background. (line 65)
  20909. * sections: Sections. (line 6)
  20910. * sections in messages, internal: As Sections. (line 6)
  20911. * sections, i386: i386-Variations. (line 46)
  20912. * sections, named: Ld Sections. (line 8)
  20913. * sections, x86-64: i386-Variations. (line 46)
  20914. * 'seg' directive, SPARC: Sparc-Directives. (line 44)
  20915. * segm: Z8000 Directives. (line 10)
  20916. * 'set at' directive, Nios II: Nios II Directives. (line 35)
  20917. * 'set break' directive, Nios II: Nios II Directives. (line 43)
  20918. * 'set' directive: Set. (line 6)
  20919. * 'set' directive, Nios II: Nios II Directives. (line 57)
  20920. * 'set' directive, TIC54X: TIC54X-Directives. (line 189)
  20921. * 'set noat' directive, Nios II: Nios II Directives. (line 31)
  20922. * 'set nobreak' directive, Nios II: Nios II Directives. (line 39)
  20923. * 'set norelax' directive, Nios II: Nios II Directives. (line 46)
  20924. * 'set relaxall' directive, Nios II: Nios II Directives. (line 53)
  20925. * 'set relaxsection' directive, Nios II: Nios II Directives. (line 49)
  20926. * SH addressing modes: SH-Addressing. (line 6)
  20927. * SH floating point (IEEE): SH Floating Point. (line 6)
  20928. * SH line comment character: SH-Chars. (line 6)
  20929. * SH line separator: SH-Chars. (line 8)
  20930. * SH machine directives: SH Directives. (line 6)
  20931. * SH opcode summary: SH Opcodes. (line 6)
  20932. * SH options: SH Options. (line 6)
  20933. * SH registers: SH-Regs. (line 6)
  20934. * SH support: SH-Dependent. (line 6)
  20935. * SH64 ABI options: SH64 Options. (line 25)
  20936. * SH64 addressing modes: SH64-Addressing. (line 6)
  20937. * SH64 ISA options: SH64 Options. (line 6)
  20938. * SH64 line comment character: SH64-Chars. (line 6)
  20939. * SH64 line separator: SH64-Chars. (line 13)
  20940. * SH64 machine directives: SH64 Directives. (line 9)
  20941. * SH64 opcode summary: SH64 Opcodes. (line 6)
  20942. * SH64 options: SH64 Options. (line 6)
  20943. * SH64 registers: SH64-Regs. (line 6)
  20944. * SH64 support: SH64-Dependent. (line 6)
  20945. * 'shigh' directive, M32R: M32R-Directives. (line 26)
  20946. * 'short' directive: Short. (line 6)
  20947. * 'short' directive, TIC54X: TIC54X-Directives. (line 109)
  20948. * SIMD, i386: i386-SIMD. (line 6)
  20949. * SIMD, x86-64: i386-SIMD. (line 6)
  20950. * single character constant: Chars. (line 6)
  20951. * 'single' directive: Single. (line 6)
  20952. * 'single' directive, i386: i386-Float. (line 14)
  20953. * 'single' directive, x86-64: i386-Float. (line 14)
  20954. * single quote, Z80: Z80-Chars. (line 20)
  20955. * sixteen bit integers: hword. (line 6)
  20956. * sixteen byte integer: Octa. (line 6)
  20957. * 'size' directive (COFF version): Size. (line 11)
  20958. * 'size' directive (ELF version): Size. (line 19)
  20959. * size modifiers, D10V: D10V-Size. (line 6)
  20960. * size modifiers, D30V: D30V-Size. (line 6)
  20961. * size modifiers, M680x0: M68K-Syntax. (line 8)
  20962. * size prefixes, i386: i386-Prefixes. (line 27)
  20963. * size suffixes, H8/300: H8/300 Opcodes. (line 160)
  20964. * size, translations, Sparc: Sparc-Size-Translations.
  20965. (line 6)
  20966. * sizes operands, i386: i386-Variations. (line 28)
  20967. * sizes operands, x86-64: i386-Variations. (line 28)
  20968. * 'skip' directive: Skip. (line 6)
  20969. * 'skip' directive, M680x0: M68K-Directives. (line 19)
  20970. * 'skip' directive, SPARC: Sparc-Directives. (line 48)
  20971. * 'sleb128' directive: Sleb128. (line 6)
  20972. * small data, MIPS: MIPS Small Data. (line 6)
  20973. * SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides.
  20974. (line 11)
  20975. * SOM symbol attributes: SOM Symbols. (line 6)
  20976. * source program: Input Files. (line 6)
  20977. * source, destination operands; i386: i386-Variations. (line 21)
  20978. * source, destination operands; x86-64: i386-Variations. (line 21)
  20979. * sp register: Xtensa Registers. (line 6)
  20980. * 'sp' register, V850: V850-Regs. (line 12)
  20981. * 'space' directive: Space. (line 6)
  20982. * 'space' directive, TIC54X: TIC54X-Directives. (line 194)
  20983. * space used, maximum for assembly: statistics. (line 6)
  20984. * SPARC architectures: Sparc-Opts. (line 6)
  20985. * Sparc constants: Sparc-Constants. (line 6)
  20986. * SPARC data alignment: Sparc-Aligned-Data. (line 6)
  20987. * SPARC floating point (IEEE): Sparc-Float. (line 6)
  20988. * Sparc line comment character: Sparc-Chars. (line 6)
  20989. * Sparc line separator: Sparc-Chars. (line 14)
  20990. * SPARC machine directives: Sparc-Directives. (line 6)
  20991. * SPARC options: Sparc-Opts. (line 6)
  20992. * Sparc registers: Sparc-Regs. (line 6)
  20993. * Sparc relocations: Sparc-Relocs. (line 6)
  20994. * Sparc size translations: Sparc-Size-Translations.
  20995. (line 6)
  20996. * SPARC support: Sparc-Dependent. (line 6)
  20997. * SPARC syntax: Sparc-Aligned-Data. (line 21)
  20998. * special characters, M680x0: M68K-Chars. (line 6)
  20999. * special purpose registers, MSP 430: MSP430-Regs. (line 11)
  21000. * 'sslist' directive, TIC54X: TIC54X-Directives. (line 201)
  21001. * 'ssnolist' directive, TIC54X: TIC54X-Directives. (line 201)
  21002. * 'stabd' directive: Stab. (line 38)
  21003. * 'stabn' directive: Stab. (line 49)
  21004. * 'stabs' directive: Stab. (line 52)
  21005. * 'stabX' directives: Stab. (line 6)
  21006. * stack pointer, ARC: ARC-Regs. (line 20)
  21007. * standard assembler sections: Secs Background. (line 27)
  21008. * standard input, as input file: Command Line. (line 10)
  21009. * statement separator character: Statements. (line 6)
  21010. * statement separator, AArch64: AArch64-Chars. (line 10)
  21011. * statement separator, Alpha: Alpha-Chars. (line 11)
  21012. * statement separator, ARC: ARC-Chars. (line 27)
  21013. * statement separator, ARM: ARM-Chars. (line 14)
  21014. * statement separator, AVR: AVR-Chars. (line 14)
  21015. * statement separator, CR16: CR16-Chars. (line 12)
  21016. * statement separator, Epiphany: Epiphany-Chars. (line 14)
  21017. * statement separator, H8/300: H8/300-Chars. (line 8)
  21018. * statement separator, i386: i386-Chars. (line 18)
  21019. * statement separator, i860: i860-Chars. (line 14)
  21020. * statement separator, i960: i960-Chars. (line 14)
  21021. * statement separator, IA-64: IA-64-Chars. (line 8)
  21022. * statement separator, IP2K: IP2K-Chars. (line 14)
  21023. * statement separator, LM32: LM32-Chars. (line 12)
  21024. * statement separator, M32C: M32C-Chars. (line 14)
  21025. * statement separator, M68HC11: M68HC11-Syntax. (line 26)
  21026. * statement separator, Meta: Meta-Chars. (line 8)
  21027. * statement separator, MicroBlaze: MicroBlaze-Chars. (line 14)
  21028. * statement separator, MIPS: MIPS-Chars. (line 14)
  21029. * statement separator, MSP 430: MSP430-Chars. (line 14)
  21030. * statement separator, NS32K: NS32K-Chars. (line 18)
  21031. * statement separator, PJ: PJ-Chars. (line 14)
  21032. * statement separator, PowerPC: PowerPC-Chars. (line 18)
  21033. * statement separator, RL78: RL78-Chars. (line 14)
  21034. * statement separator, RX: RX-Chars. (line 14)
  21035. * statement separator, s390: s390 Characters. (line 13)
  21036. * statement separator, SCORE: SCORE-Chars. (line 14)
  21037. * statement separator, SH: SH-Chars. (line 8)
  21038. * statement separator, SH64: SH64-Chars. (line 13)
  21039. * statement separator, Sparc: Sparc-Chars. (line 14)
  21040. * statement separator, TIC54X: TIC54X-Chars. (line 17)
  21041. * statement separator, TIC6X: TIC6X Syntax. (line 13)
  21042. * statement separator, V850: V850-Chars. (line 13)
  21043. * statement separator, VAX: VAX-Chars. (line 14)
  21044. * statement separator, Visium: Visium Characters. (line 14)
  21045. * statement separator, XGATE: XGATE-Syntax. (line 25)
  21046. * statement separator, XStormy16: XStormy16-Chars. (line 14)
  21047. * statement separator, Z80: Z80-Chars. (line 13)
  21048. * statement separator, Z8000: Z8000-Chars. (line 13)
  21049. * statements, structure of: Statements. (line 6)
  21050. * statistics, about assembly: statistics. (line 6)
  21051. * Status register, ARC: ARC-Regs. (line 57)
  21052. * STATUS32 saved on exception, ARC: ARC-Regs. (line 82)
  21053. * stopping the assembly: Abort. (line 6)
  21054. * Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs.
  21055. (line 69)
  21056. * string constants: Strings. (line 6)
  21057. * 'string' directive: String. (line 8)
  21058. * 'string' directive on HPPA: HPPA Directives. (line 137)
  21059. * 'string' directive, TIC54X: TIC54X-Directives. (line 206)
  21060. * string literals: Ascii. (line 6)
  21061. * string, copying to object file: String. (line 8)
  21062. * 'string16' directive: String. (line 8)
  21063. * string16, copying to object file: String. (line 8)
  21064. * 'string32' directive: String. (line 8)
  21065. * string32, copying to object file: String. (line 8)
  21066. * 'string64' directive: String. (line 8)
  21067. * string64, copying to object file: String. (line 8)
  21068. * 'string8' directive: String. (line 8)
  21069. * string8, copying to object file: String. (line 8)
  21070. * 'struct' directive: Struct. (line 6)
  21071. * 'struct' directive, TIC54X: TIC54X-Directives. (line 214)
  21072. * structure debugging, COFF: Tag. (line 6)
  21073. * sub-instruction ordering, D10V: D10V-Chars. (line 14)
  21074. * sub-instruction ordering, D30V: D30V-Chars. (line 14)
  21075. * sub-instructions, D10V: D10V-Subs. (line 6)
  21076. * sub-instructions, D30V: D30V-Subs. (line 6)
  21077. * subexpressions: Arguments. (line 24)
  21078. * 'subsection' directive: SubSection. (line 6)
  21079. * subsym builtins, TIC54X: TIC54X-Macros. (line 16)
  21080. * subtitles for listings: Sbttl. (line 6)
  21081. * subtraction, permitted arguments: Infix Ops. (line 50)
  21082. * summary of options: Overview. (line 6)
  21083. * support: HPPA-Dependent. (line 6)
  21084. * supporting files, including: Include. (line 6)
  21085. * suppressing warnings: W. (line 11)
  21086. * sval: Z8000 Directives. (line 33)
  21087. * symbol attributes: Symbol Attributes. (line 6)
  21088. * symbol attributes, 'a.out': a.out Symbols. (line 6)
  21089. * symbol attributes, COFF: COFF Symbols. (line 6)
  21090. * symbol attributes, SOM: SOM Symbols. (line 6)
  21091. * symbol descriptor, COFF: Desc. (line 6)
  21092. * symbol modifiers: AVR-Modifiers. (line 12)
  21093. * symbol modifiers <1>: LM32-Modifiers. (line 12)
  21094. * symbol modifiers <2>: M32C-Modifiers. (line 11)
  21095. * symbol modifiers <3>: M68HC11-Modifiers. (line 12)
  21096. * symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6)
  21097. * symbol modifiers, TILEPro: TILEPro Modifiers. (line 6)
  21098. * symbol names: Symbol Names. (line 6)
  21099. * symbol names, '$' in: D10V-Chars. (line 46)
  21100. * symbol names, '$' in <1>: D30V-Chars. (line 70)
  21101. * symbol names, '$' in <2>: Meta-Chars. (line 10)
  21102. * symbol names, '$' in <3>: SH-Chars. (line 15)
  21103. * symbol names, '$' in <4>: SH64-Chars. (line 15)
  21104. * symbol names, local: Symbol Names. (line 30)
  21105. * symbol names, temporary: Symbol Names. (line 43)
  21106. * symbol prefix character, ARC: ARC-Chars. (line 20)
  21107. * symbol storage class (COFF): Scl. (line 6)
  21108. * symbol type: Symbol Type. (line 6)
  21109. * symbol type, COFF: Type. (line 11)
  21110. * symbol type, ELF: Type. (line 22)
  21111. * symbol value: Symbol Value. (line 6)
  21112. * symbol value, setting: Set. (line 6)
  21113. * symbol values, assigning: Setting Symbols. (line 6)
  21114. * symbol versioning: Symver. (line 6)
  21115. * symbol, common: Comm. (line 6)
  21116. * symbol, making visible to linker: Global. (line 6)
  21117. * symbolic debuggers, information for: Stab. (line 6)
  21118. * symbols: Symbols. (line 6)
  21119. * Symbols in position-independent code, CRIS: CRIS-Pic. (line 6)
  21120. * symbols with uppercase, VAX/VMS: VAX-Opts. (line 42)
  21121. * symbols, assigning values to: Equ. (line 6)
  21122. * Symbols, built-in, CRIS: CRIS-Symbols. (line 6)
  21123. * Symbols, CRIS, built-in: CRIS-Symbols. (line 6)
  21124. * symbols, local common: Lcomm. (line 6)
  21125. * 'symver' directive: Symver. (line 6)
  21126. * syntax compatibility, i386: i386-Variations. (line 6)
  21127. * syntax compatibility, x86-64: i386-Variations. (line 6)
  21128. * syntax, AVR: AVR-Modifiers. (line 6)
  21129. * syntax, Blackfin: Blackfin Syntax. (line 6)
  21130. * syntax, D10V: D10V-Syntax. (line 6)
  21131. * syntax, D30V: D30V-Syntax. (line 6)
  21132. * syntax, LM32: LM32-Modifiers. (line 6)
  21133. * syntax, M680x0: M68K-Syntax. (line 8)
  21134. * syntax, M68HC11: M68HC11-Syntax. (line 6)
  21135. * syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6)
  21136. * syntax, machine-independent: Syntax. (line 6)
  21137. * syntax, RL78: RL78-Modifiers. (line 6)
  21138. * syntax, RX: RX-Modifiers. (line 6)
  21139. * syntax, SPARC: Sparc-Aligned-Data. (line 20)
  21140. * syntax, TILE-Gx: TILE-Gx Syntax. (line 6)
  21141. * syntax, TILEPro: TILEPro Syntax. (line 6)
  21142. * syntax, XGATE: XGATE-Syntax. (line 6)
  21143. * syntax, Xtensa assembler: Xtensa Syntax. (line 6)
  21144. * 'sysproc' directive, i960: Directives-i960. (line 37)
  21145. * tab ('\t'): Strings. (line 27)
  21146. * 'tab' directive, TIC54X: TIC54X-Directives. (line 245)
  21147. * 'tag' directive: Tag. (line 6)
  21148. * 'tag' directive, TIC54X: TIC54X-Directives. (line 214)
  21149. * 'tag' directive, TIC54X <1>: TIC54X-Directives. (line 248)
  21150. * TBM, i386: i386-TBM. (line 6)
  21151. * TBM, x86-64: i386-TBM. (line 6)
  21152. * 'tdaoff' pseudo-op, V850: V850 Opcodes. (line 81)
  21153. * temporary symbol names: Symbol Names. (line 43)
  21154. * text and data sections, joining: R. (line 6)
  21155. * 'text' directive: Text. (line 6)
  21156. * text section: Ld Sections. (line 9)
  21157. * 'tfloat' directive, i386: i386-Float. (line 14)
  21158. * 'tfloat' directive, x86-64: i386-Float. (line 14)
  21159. * Thumb support: ARM-Dependent. (line 6)
  21160. * TIC54X builtin math functions: TIC54X-Builtins. (line 6)
  21161. * TIC54X line comment character: TIC54X-Chars. (line 6)
  21162. * TIC54X line separator: TIC54X-Chars. (line 17)
  21163. * TIC54X machine directives: TIC54X-Directives. (line 6)
  21164. * TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6)
  21165. * TIC54X options: TIC54X-Opts. (line 6)
  21166. * TIC54X subsym builtins: TIC54X-Macros. (line 16)
  21167. * TIC54X support: TIC54X-Dependent. (line 6)
  21168. * TIC54X-specific macros: TIC54X-Macros. (line 6)
  21169. * TIC6X big-endian output: TIC6X Options. (line 46)
  21170. * TIC6X line comment character: TIC6X Syntax. (line 6)
  21171. * TIC6X line separator: TIC6X Syntax. (line 13)
  21172. * TIC6X little-endian output: TIC6X Options. (line 46)
  21173. * TIC6X machine directives: TIC6X Directives. (line 6)
  21174. * TIC6X options: TIC6X Options. (line 6)
  21175. * TIC6X support: TIC6X-Dependent. (line 6)
  21176. * TILE-Gx machine directives: TILE-Gx Directives. (line 6)
  21177. * TILE-Gx modifiers: TILE-Gx Modifiers. (line 6)
  21178. * TILE-Gx opcode names: TILE-Gx Opcodes. (line 6)
  21179. * TILE-Gx register names: TILE-Gx Registers. (line 6)
  21180. * TILE-Gx support: TILE-Gx-Dependent. (line 6)
  21181. * TILE-Gx syntax: TILE-Gx Syntax. (line 6)
  21182. * TILEPro machine directives: TILEPro Directives. (line 6)
  21183. * TILEPro modifiers: TILEPro Modifiers. (line 6)
  21184. * TILEPro opcode names: TILEPro Opcodes. (line 6)
  21185. * TILEPro register names: TILEPro Registers. (line 6)
  21186. * TILEPro support: TILEPro-Dependent. (line 6)
  21187. * TILEPro syntax: TILEPro Syntax. (line 6)
  21188. * time, total for assembly: statistics. (line 6)
  21189. * 'title' directive: Title. (line 6)
  21190. * 'tls_gd' directive, Nios II: Nios II Relocations.
  21191. (line 38)
  21192. * 'tls_ie' directive, Nios II: Nios II Relocations.
  21193. (line 38)
  21194. * 'tls_ldm' directive, Nios II: Nios II Relocations.
  21195. (line 38)
  21196. * 'tls_ldo' directive, Nios II: Nios II Relocations.
  21197. (line 38)
  21198. * 'tls_le' directive, Nios II: Nios II Relocations.
  21199. (line 38)
  21200. * TMS320C6X support: TIC6X-Dependent. (line 6)
  21201. * 'tp' register, V850: V850-Regs. (line 16)
  21202. * 'transform' directive: Transform Directive.
  21203. (line 6)
  21204. * trusted compiler: f. (line 6)
  21205. * turning preprocessing on and off: Preprocessing. (line 26)
  21206. * 'type' directive (COFF version): Type. (line 11)
  21207. * 'type' directive (ELF version): Type. (line 22)
  21208. * type of a symbol: Symbol Type. (line 6)
  21209. * 'ualong' directive, SH: SH Directives. (line 6)
  21210. * 'uaquad' directive, SH: SH Directives. (line 6)
  21211. * 'uaword' directive, SH: SH Directives. (line 6)
  21212. * 'ubyte' directive, TIC54X: TIC54X-Directives. (line 34)
  21213. * 'uchar' directive, TIC54X: TIC54X-Directives. (line 34)
  21214. * 'uhalf' directive, TIC54X: TIC54X-Directives. (line 109)
  21215. * 'uint' directive, TIC54X: TIC54X-Directives. (line 109)
  21216. * 'uleb128' directive: Uleb128. (line 6)
  21217. * 'ulong' directive, TIC54X: TIC54X-Directives. (line 133)
  21218. * undefined section: Ld Sections. (line 36)
  21219. * 'union' directive, TIC54X: TIC54X-Directives. (line 248)
  21220. * unsegm: Z8000 Directives. (line 14)
  21221. * 'usect' directive, TIC54X: TIC54X-Directives. (line 260)
  21222. * 'ushort' directive, TIC54X: TIC54X-Directives. (line 109)
  21223. * 'uword' directive, TIC54X: TIC54X-Directives. (line 109)
  21224. * V850 command line options: V850 Options. (line 9)
  21225. * V850 floating point (IEEE): V850 Floating Point.
  21226. (line 6)
  21227. * V850 line comment character: V850-Chars. (line 6)
  21228. * V850 line separator: V850-Chars. (line 13)
  21229. * V850 machine directives: V850 Directives. (line 6)
  21230. * V850 opcodes: V850 Opcodes. (line 6)
  21231. * V850 options (none): V850 Options. (line 6)
  21232. * V850 register names: V850-Regs. (line 6)
  21233. * V850 support: V850-Dependent. (line 6)
  21234. * 'val' directive: Val. (line 6)
  21235. * value attribute, COFF: Val. (line 6)
  21236. * value of a symbol: Symbol Value. (line 6)
  21237. * 'var' directive, TIC54X: TIC54X-Directives. (line 270)
  21238. * VAX bitfields not supported: VAX-no. (line 6)
  21239. * VAX branch improvement: VAX-branch. (line 6)
  21240. * VAX command-line options ignored: VAX-Opts. (line 6)
  21241. * VAX displacement sizing character: VAX-operands. (line 12)
  21242. * VAX floating point: VAX-float. (line 6)
  21243. * VAX immediate character: VAX-operands. (line 6)
  21244. * VAX indirect character: VAX-operands. (line 9)
  21245. * VAX line comment character: VAX-Chars. (line 6)
  21246. * VAX line separator: VAX-Chars. (line 14)
  21247. * VAX machine directives: VAX-directives. (line 6)
  21248. * VAX opcode mnemonics: VAX-opcodes. (line 6)
  21249. * VAX operand notation: VAX-operands. (line 6)
  21250. * VAX register names: VAX-operands. (line 17)
  21251. * VAX support: Vax-Dependent. (line 6)
  21252. * Vax-11 C compatibility: VAX-Opts. (line 42)
  21253. * VAX/VMS options: VAX-Opts. (line 42)
  21254. * 'version' directive: Version. (line 6)
  21255. * 'version' directive, TIC54X: TIC54X-Directives. (line 274)
  21256. * version of assembler: v. (line 6)
  21257. * versions of symbols: Symver. (line 6)
  21258. * Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides.
  21259. (line 52)
  21260. * visibility: Hidden. (line 6)
  21261. * visibility <1>: Internal. (line 6)
  21262. * visibility <2>: Protected. (line 6)
  21263. * Visium line comment character: Visium Characters. (line 6)
  21264. * Visium line separator: Visium Characters. (line 14)
  21265. * Visium options: Visium Options. (line 6)
  21266. * Visium registers: Visium Registers. (line 6)
  21267. * Visium support: Visium-Dependent. (line 6)
  21268. * VMS (VAX) options: VAX-Opts. (line 42)
  21269. * 'vtable_entry' directive: VTableEntry. (line 6)
  21270. * 'vtable_inherit' directive: VTableInherit. (line 6)
  21271. * warning directive: Warning. (line 6)
  21272. * warning for altered difference tables: K. (line 6)
  21273. * warning messages: Errors. (line 6)
  21274. * warnings, causing error: W. (line 16)
  21275. * warnings, M32R: M32R-Warnings. (line 6)
  21276. * warnings, suppressing: W. (line 11)
  21277. * warnings, switching on: W. (line 19)
  21278. * 'weak' directive: Weak. (line 6)
  21279. * 'weakref' directive: Weakref. (line 6)
  21280. * whitespace: Whitespace. (line 6)
  21281. * whitespace, removed by preprocessor: Preprocessing. (line 7)
  21282. * wide floating point directives, VAX: VAX-directives. (line 9)
  21283. * 'width' directive, TIC54X: TIC54X-Directives. (line 125)
  21284. * Width of continuation lines of disassembly output: listing.
  21285. (line 21)
  21286. * Width of first line disassembly output: listing. (line 16)
  21287. * Width of source line output: listing. (line 28)
  21288. * 'wmsg' directive, TIC54X: TIC54X-Directives. (line 75)
  21289. * word aligned program counter, ARC: ARC-Regs. (line 44)
  21290. * 'word' directive: Word. (line 6)
  21291. * 'word' directive, H8/300: H8/300 Directives. (line 6)
  21292. * 'word' directive, i386: i386-Float. (line 21)
  21293. * 'word' directive, Nios II: Nios II Directives. (line 13)
  21294. * 'word' directive, SPARC: Sparc-Directives. (line 51)
  21295. * 'word' directive, TIC54X: TIC54X-Directives. (line 109)
  21296. * 'word' directive, x86-64: i386-Float. (line 21)
  21297. * writing patterns in memory: Fill. (line 6)
  21298. * wval: Z8000 Directives. (line 24)
  21299. * x86 machine directives: i386-Directives. (line 6)
  21300. * x86-64 arch directive: i386-Arch. (line 6)
  21301. * x86-64 att_syntax pseudo op: i386-Variations. (line 6)
  21302. * x86-64 conversion instructions: i386-Mnemonics. (line 39)
  21303. * x86-64 floating point: i386-Float. (line 6)
  21304. * x86-64 immediate operands: i386-Variations. (line 15)
  21305. * x86-64 instruction naming: i386-Mnemonics. (line 9)
  21306. * x86-64 intel_syntax pseudo op: i386-Variations. (line 6)
  21307. * x86-64 jump optimization: i386-Jumps. (line 6)
  21308. * x86-64 jump, call, return: i386-Variations. (line 40)
  21309. * x86-64 jump/call operands: i386-Variations. (line 15)
  21310. * x86-64 memory references: i386-Memory. (line 6)
  21311. * x86-64 options: i386-Options. (line 6)
  21312. * x86-64 register operands: i386-Variations. (line 15)
  21313. * x86-64 registers: i386-Regs. (line 6)
  21314. * x86-64 sections: i386-Variations. (line 46)
  21315. * x86-64 size suffixes: i386-Variations. (line 28)
  21316. * x86-64 source, destination operands: i386-Variations. (line 21)
  21317. * x86-64 support: i386-Dependent. (line 6)
  21318. * x86-64 syntax compatibility: i386-Variations. (line 6)
  21319. * 'xfloat' directive, TIC54X: TIC54X-Directives. (line 62)
  21320. * XGATE addressing modes: XGATE-Syntax. (line 28)
  21321. * XGATE assembler directives: XGATE-Directives. (line 6)
  21322. * XGATE floating point: XGATE-Float. (line 6)
  21323. * XGATE line comment character: XGATE-Syntax. (line 16)
  21324. * XGATE line separator: XGATE-Syntax. (line 25)
  21325. * XGATE opcodes: XGATE-opcodes. (line 6)
  21326. * XGATE options: XGATE-Opts. (line 6)
  21327. * XGATE support: XGATE-Dependent. (line 6)
  21328. * XGATE syntax: XGATE-Syntax. (line 6)
  21329. * 'xlong' directive, TIC54X: TIC54X-Directives. (line 133)
  21330. * XStormy16 comment character: XStormy16-Chars. (line 11)
  21331. * XStormy16 line comment character: XStormy16-Chars. (line 6)
  21332. * XStormy16 line separator: XStormy16-Chars. (line 14)
  21333. * XStormy16 machine directives: XStormy16 Directives.
  21334. (line 6)
  21335. * XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6)
  21336. * XStormy16 support: XSTORMY16-Dependent.
  21337. (line 6)
  21338. * Xtensa architecture: Xtensa-Dependent. (line 6)
  21339. * Xtensa assembler syntax: Xtensa Syntax. (line 6)
  21340. * Xtensa directives: Xtensa Directives. (line 6)
  21341. * Xtensa opcode names: Xtensa Opcodes. (line 6)
  21342. * Xtensa register names: Xtensa Registers. (line 6)
  21343. * 'xword' directive, SPARC: Sparc-Directives. (line 55)
  21344. * Z80 $: Z80-Chars. (line 15)
  21345. * Z80 ': Z80-Chars. (line 20)
  21346. * Z80 floating point: Z80 Floating Point. (line 6)
  21347. * Z80 line comment character: Z80-Chars. (line 6)
  21348. * Z80 line separator: Z80-Chars. (line 13)
  21349. * Z80 options: Z80 Options. (line 6)
  21350. * Z80 registers: Z80-Regs. (line 6)
  21351. * Z80 support: Z80-Dependent. (line 6)
  21352. * Z80 Syntax: Z80 Options. (line 40)
  21353. * Z80, case sensitivity: Z80-Case. (line 6)
  21354. * Z80, \: Z80-Chars. (line 18)
  21355. * Z80-only directives: Z80 Directives. (line 9)
  21356. * Z800 addressing modes: Z8000-Addressing. (line 6)
  21357. * Z8000 directives: Z8000 Directives. (line 6)
  21358. * Z8000 line comment character: Z8000-Chars. (line 6)
  21359. * Z8000 line separator: Z8000-Chars. (line 13)
  21360. * Z8000 opcode summary: Z8000 Opcodes. (line 6)
  21361. * Z8000 options: Z8000 Options. (line 6)
  21362. * Z8000 registers: Z8000-Regs. (line 6)
  21363. * Z8000 support: Z8000-Dependent. (line 6)
  21364. * 'zdaoff' pseudo-op, V850: V850 Opcodes. (line 98)
  21365. * 'zero' directive: Zero. (line 6)
  21366. * 'zero' register, V850: V850-Regs. (line 7)
  21367. * zero-terminated strings: Asciz. (line 6)
  21368. 
  21369. Tag Table:
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  21372. Node: Manual40090
  21373. Node: GNU Assembler41034
  21374. Node: Object Formats42205
  21375. Node: Command Line42657
  21376. Node: Input Files43743
  21377. Node: Object45724
  21378. Node: Errors46620
  21379. Node: Invoking48182
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  21653. Node: H8/300 Syntax362162
  21654. Node: H8/300-Chars362463
  21655. Node: H8/300-Regs362762
  21656. Node: H8/300-Addressing363681
  21657. Node: H8/300 Floating Point364705
  21658. Node: H8/300 Directives365032
  21659. Node: H8/300 Opcodes366160
  21660. Node: HPPA-Dependent374479
  21661. Node: HPPA Notes374914
  21662. Node: HPPA Options375672
  21663. Node: HPPA Syntax375867
  21664. Node: HPPA Floating Point377137
  21665. Node: HPPA Directives377343
  21666. Node: HPPA Opcodes386025
  21667. Node: ESA/390-Dependent386284
  21668. Node: ESA/390 Notes386744
  21669. Node: ESA/390 Options387535
  21670. Node: ESA/390 Syntax387745
  21671. Node: ESA/390 Floating Point389918
  21672. Node: ESA/390 Directives390197
  21673. Node: ESA/390 Opcodes393487
  21674. Node: i386-Dependent393749
  21675. Node: i386-Options395076
  21676. Node: i386-Directives403684
  21677. Node: i386-Syntax404421
  21678. Node: i386-Variations404726
  21679. Node: i386-Chars407263
  21680. Node: i386-Mnemonics407992
  21681. Node: i386-Regs411355
  21682. Node: i386-Prefixes414185
  21683. Node: i386-Memory416945
  21684. Node: i386-Jumps419884
  21685. Node: i386-Float421007
  21686. Node: i386-SIMD422837
  21687. Node: i386-LWP423946
  21688. Node: i386-BMI424780
  21689. Node: i386-TBM425158
  21690. Node: i386-16bit425688
  21691. Node: i386-Arch427759
  21692. Node: i386-Bugs430937
  21693. Node: i386-Notes431688
  21694. Node: i860-Dependent432547
  21695. Node: Notes-i860432987
  21696. Node: Options-i860433894
  21697. Node: Directives-i860435254
  21698. Node: Opcodes for i860436326
  21699. Node: Syntax of i860438515
  21700. Node: i860-Chars438699
  21701. Node: i960-Dependent439258
  21702. Node: Options-i960439705
  21703. Node: Floating Point-i960443591
  21704. Node: Directives-i960443859
  21705. Node: Opcodes for i960445893
  21706. Node: callj-i960446533
  21707. Node: Compare-and-branch-i960447023
  21708. Node: Syntax of i960448927
  21709. Node: i960-Chars449127
  21710. Node: IA-64-Dependent449670
  21711. Node: IA-64 Options449971
  21712. Node: IA-64 Syntax453122
  21713. Node: IA-64-Chars453528
  21714. Node: IA-64-Regs453758
  21715. Node: IA-64-Bits454684
  21716. Node: IA-64-Relocs455214
  21717. Node: IA-64 Opcodes455685
  21718. Node: IP2K-Dependent455957
  21719. Node: IP2K-Opts456229
  21720. Node: IP2K-Syntax456728
  21721. Node: IP2K-Chars456902
  21722. Node: LM32-Dependent457445
  21723. Node: LM32 Options457740
  21724. Node: LM32 Syntax458373
  21725. Node: LM32-Regs458669
  21726. Node: LM32-Modifiers459610
  21727. Node: LM32-Chars460990
  21728. Node: LM32 Opcodes461498
  21729. Node: M32C-Dependent461802
  21730. Node: M32C-Opts462308
  21731. Node: M32C-Syntax462727
  21732. Node: M32C-Modifiers462962
  21733. Node: M32C-Chars464754
  21734. Node: M32R-Dependent465320
  21735. Node: M32R-Opts465641
  21736. Node: M32R-Directives469803
  21737. Node: M32R-Warnings473777
  21738. Node: M68K-Dependent476782
  21739. Node: M68K-Opts477249
  21740. Node: M68K-Syntax484671
  21741. Node: M68K-Moto-Syntax486511
  21742. Node: M68K-Float489095
  21743. Node: M68K-Directives489615
  21744. Node: M68K-opcodes490942
  21745. Node: M68K-Branch491168
  21746. Node: M68K-Chars495363
  21747. Node: M68HC11-Dependent496226
  21748. Node: M68HC11-Opts496757
  21749. Node: M68HC11-Syntax501069
  21750. Node: M68HC11-Modifiers503863
  21751. Node: M68HC11-Directives505690
  21752. Node: M68HC11-Float507064
  21753. Node: M68HC11-opcodes507592
  21754. Node: M68HC11-Branch507774
  21755. Node: Meta-Dependent510224
  21756. Node: Meta Options510509
  21757. Node: Meta Syntax511171
  21758. Node: Meta-Chars511383
  21759. Node: Meta-Regs511683
  21760. Node: MicroBlaze-Dependent511959
  21761. Node: MicroBlaze Directives512646
  21762. Node: MicroBlaze Syntax514037
  21763. Node: MicroBlaze-Chars514269
  21764. Node: MIPS-Dependent514821
  21765. Node: MIPS Options516255
  21766. Node: MIPS Macros532944
  21767. Ref: MIPS Macros-Footnote-1535658
  21768. Node: MIPS Symbol Sizes535801
  21769. Node: MIPS Small Data537473
  21770. Node: MIPS ISA539637
  21771. Node: MIPS assembly options541421
  21772. Node: MIPS autoextend542554
  21773. Node: MIPS insn543288
  21774. Node: MIPS FP ABIs544569
  21775. Node: MIPS FP ABI History545021
  21776. Node: MIPS FP ABI Variants545781
  21777. Node: MIPS FP ABI Selection548334
  21778. Node: MIPS FP ABI Compatibility549397
  21779. Node: MIPS NaN Encodings550207
  21780. Node: MIPS Option Stack552170
  21781. Node: MIPS ASE Instruction Generation Overrides552955
  21782. Node: MIPS Floating-Point555968
  21783. Node: MIPS Syntax556874
  21784. Node: MIPS-Chars557136
  21785. Node: MMIX-Dependent557678
  21786. Node: MMIX-Opts558058
  21787. Node: MMIX-Expand561663
  21788. Node: MMIX-Syntax562975
  21789. Ref: mmixsite563331
  21790. Node: MMIX-Chars564173
  21791. Node: MMIX-Symbols565046
  21792. Node: MMIX-Regs567117
  21793. Node: MMIX-Pseudos568142
  21794. Ref: MMIX-loc568284
  21795. Ref: MMIX-local569365
  21796. Ref: MMIX-is569898
  21797. Ref: MMIX-greg570170
  21798. Ref: GREG-base571088
  21799. Ref: MMIX-byte572407
  21800. Ref: MMIX-constants572879
  21801. Ref: MMIX-prefix573521
  21802. Ref: MMIX-spec573896
  21803. Node: MMIX-mmixal574230
  21804. Node: MSP430-Dependent577725
  21805. Node: MSP430 Options578194
  21806. Node: MSP430 Syntax581374
  21807. Node: MSP430-Macros581690
  21808. Node: MSP430-Chars582420
  21809. Node: MSP430-Regs583135
  21810. Node: MSP430-Ext583696
  21811. Node: MSP430 Floating Point585515
  21812. Node: MSP430 Directives585739
  21813. Node: MSP430 Opcodes587054
  21814. Node: MSP430 Profiling Capability587449
  21815. Node: NDS32-Dependent589777
  21816. Node: NDS32 Options590386
  21817. Node: NDS32 Syntax592269
  21818. Node: NDS32-Chars592537
  21819. Node: NDS32-Regs593004
  21820. Node: NDS32-Ops593858
  21821. Node: NiosII-Dependent597455
  21822. Node: Nios II Options597874
  21823. Node: Nios II Syntax599106
  21824. Node: Nios II Chars599312
  21825. Node: Nios II Relocations599503
  21826. Node: Nios II Directives601074
  21827. Node: Nios II Opcodes602636
  21828. Node: NS32K-Dependent602911
  21829. Node: NS32K Syntax603138
  21830. Node: NS32K-Chars603287
  21831. Node: PDP-11-Dependent604027
  21832. Node: PDP-11-Options604417
  21833. Node: PDP-11-Pseudos609476
  21834. Node: PDP-11-Syntax609821
  21835. Node: PDP-11-Mnemonics610653
  21836. Node: PDP-11-Synthetic610955
  21837. Node: PJ-Dependent611173
  21838. Node: PJ Options611436
  21839. Node: PJ Syntax611731
  21840. Node: PJ-Chars611896
  21841. Node: PPC-Dependent612445
  21842. Node: PowerPC-Opts612778
  21843. Node: PowerPC-Pseudo616404
  21844. Node: PowerPC-Syntax617025
  21845. Node: PowerPC-Chars617215
  21846. Node: RL78-Dependent617966
  21847. Node: RL78-Opts618368
  21848. Node: RL78-Modifiers619202
  21849. Node: RL78-Directives619981
  21850. Node: RL78-Syntax620585
  21851. Node: RL78-Chars620781
  21852. Node: RISC-V-Dependent621337
  21853. Node: RISC-V-Opts621559
  21854. Node: RX-Dependent622208
  21855. Node: RX-Opts622641
  21856. Node: RX-Modifiers626884
  21857. Node: RX-Directives627987
  21858. Node: RX-Float628726
  21859. Node: RX-Syntax629361
  21860. Node: RX-Chars629540
  21861. Node: S/390-Dependent630092
  21862. Node: s390 Options630920
  21863. Node: s390 Characters633037
  21864. Node: s390 Syntax633558
  21865. Node: s390 Register634460
  21866. Node: s390 Mnemonics635276
  21867. Node: s390 Operands638298
  21868. Node: s390 Formats640928
  21869. Node: s390 Aliases648775
  21870. Node: s390 Operand Modifier652740
  21871. Node: s390 Instruction Marker656543
  21872. Node: s390 Literal Pool Entries657557
  21873. Node: s390 Directives659490
  21874. Node: s390 Floating Point664942
  21875. Node: SCORE-Dependent665390
  21876. Node: SCORE-Opts665692
  21877. Node: SCORE-Pseudo666979
  21878. Node: SCORE-Syntax669061
  21879. Node: SCORE-Chars669243
  21880. Node: SH-Dependent669801
  21881. Node: SH Options670212
  21882. Node: SH Syntax671263
  21883. Node: SH-Chars671536
  21884. Node: SH-Regs672079
  21885. Node: SH-Addressing672693
  21886. Node: SH Floating Point673601
  21887. Node: SH Directives674698
  21888. Node: SH Opcodes675099
  21889. Node: SH64-Dependent679420
  21890. Node: SH64 Options679782
  21891. Node: SH64 Syntax681573
  21892. Node: SH64-Chars681856
  21893. Node: SH64-Regs682405
  21894. Node: SH64-Addressing683501
  21895. Node: SH64 Directives684686
  21896. Node: SH64 Opcodes685670
  21897. Node: Sparc-Dependent686385
  21898. Node: Sparc-Opts686796
  21899. Node: Sparc-Aligned-Data692136
  21900. Node: Sparc-Syntax692968
  21901. Node: Sparc-Chars693542
  21902. Node: Sparc-Regs694105
  21903. Node: Sparc-Constants699953
  21904. Node: Sparc-Relocs704713
  21905. Node: Sparc-Size-Translations709831
  21906. Node: Sparc-Float711481
  21907. Node: Sparc-Directives711676
  21908. Node: TIC54X-Dependent713638
  21909. Node: TIC54X-Opts714401
  21910. Node: TIC54X-Block715442
  21911. Node: TIC54X-Env715802
  21912. Node: TIC54X-Constants716150
  21913. Node: TIC54X-Subsyms716547
  21914. Node: TIC54X-Locals718451
  21915. Node: TIC54X-Builtins719191
  21916. Node: TIC54X-Ext721605
  21917. Node: TIC54X-Directives722176
  21918. Node: TIC54X-Macros733084
  21919. Node: TIC54X-MMRegs735171
  21920. Node: TIC54X-Syntax735408
  21921. Node: TIC54X-Chars735598
  21922. Node: TIC6X-Dependent736289
  21923. Node: TIC6X Options736592
  21924. Node: TIC6X Syntax738591
  21925. Node: TIC6X Directives739694
  21926. Node: TILE-Gx-Dependent741979
  21927. Node: TILE-Gx Options742289
  21928. Node: TILE-Gx Syntax742638
  21929. Node: TILE-Gx Opcodes744874
  21930. Node: TILE-Gx Registers745162
  21931. Node: TILE-Gx Modifiers745933
  21932. Node: TILE-Gx Directives750931
  21933. Node: TILEPro-Dependent751834
  21934. Node: TILEPro Options752143
  21935. Node: TILEPro Syntax752327
  21936. Node: TILEPro Opcodes754563
  21937. Node: TILEPro Registers754854
  21938. Node: TILEPro Modifiers755624
  21939. Node: TILEPro Directives760412
  21940. Node: V850-Dependent761315
  21941. Node: V850 Options761711
  21942. Node: V850 Syntax765989
  21943. Node: V850-Chars766229
  21944. Node: V850-Regs766773
  21945. Node: V850 Floating Point768283
  21946. Node: V850 Directives768489
  21947. Node: V850 Opcodes770555
  21948. Node: Vax-Dependent776434
  21949. Node: VAX-Opts777018
  21950. Node: VAX-float780739
  21951. Node: VAX-directives781372
  21952. Node: VAX-opcodes782232
  21953. Node: VAX-branch782621
  21954. Node: VAX-operands785125
  21955. Node: VAX-no785888
  21956. Node: VAX-Syntax786144
  21957. Node: VAX-Chars786310
  21958. Node: Visium-Dependent786864
  21959. Node: Visium Options787171
  21960. Node: Visium Syntax787637
  21961. Node: Visium Characters787882
  21962. Node: Visium Registers788463
  21963. Node: Visium Opcodes788735
  21964. Node: XGATE-Dependent789161
  21965. Node: XGATE-Opts789583
  21966. Node: XGATE-Syntax790572
  21967. Node: XGATE-Directives792653
  21968. Node: XGATE-Float792892
  21969. Node: XGATE-opcodes793389
  21970. Node: XSTORMY16-Dependent793501
  21971. Node: XStormy16 Syntax793847
  21972. Node: XStormy16-Chars794037
  21973. Node: XStormy16 Directives794650
  21974. Node: XStormy16 Opcodes795304
  21975. Node: Xtensa-Dependent796359
  21976. Node: Xtensa Options797090
  21977. Node: Xtensa Syntax801357
  21978. Node: Xtensa Opcodes803501
  21979. Node: Xtensa Registers805294
  21980. Node: Xtensa Optimizations805927
  21981. Node: Density Instructions806379
  21982. Node: Xtensa Automatic Alignment807481
  21983. Node: Xtensa Relaxation809928
  21984. Node: Xtensa Branch Relaxation810893
  21985. Node: Xtensa Call Relaxation812265
  21986. Node: Xtensa Jump Relaxation814046
  21987. Node: Xtensa Immediate Relaxation816146
  21988. Node: Xtensa Directives818721
  21989. Node: Schedule Directive820429
  21990. Node: Longcalls Directive820769
  21991. Node: Transform Directive821313
  21992. Node: Literal Directive822055
  21993. Ref: Literal Directive-Footnote-1825594
  21994. Node: Literal Position Directive825736
  21995. Node: Literal Prefix Directive827435
  21996. Node: Absolute Literals Directive828333
  21997. Node: Z80-Dependent829640
  21998. Node: Z80 Options830028
  21999. Node: Z80 Syntax831447
  22000. Node: Z80-Chars832119
  22001. Node: Z80-Regs832970
  22002. Node: Z80-Case833322
  22003. Node: Z80 Floating Point833767
  22004. Node: Z80 Directives833961
  22005. Node: Z80 Opcodes835586
  22006. Node: Z8000-Dependent836932
  22007. Node: Z8000 Options837868
  22008. Node: Z8000 Syntax838085
  22009. Node: Z8000-Chars838375
  22010. Node: Z8000-Regs838857
  22011. Node: Z8000-Addressing839647
  22012. Node: Z8000 Directives840757
  22013. Node: Z8000 Opcodes842361
  22014. Node: Reporting Bugs852303
  22015. Node: Bug Criteria853029
  22016. Node: Bug Reporting853796
  22017. Node: Acknowledgements860440
  22018. Ref: Acknowledgements-Footnote-1865406
  22019. Node: GNU Free Documentation License865432
  22020. Node: AS Index890582
  22021. 
  22022. End Tag Table