Standard-Names.html 136 KB

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  68. <a name="Standard-Pattern-Names-For-Generation"></a>
  69. <h3 class="section">16.9 Standard Pattern Names For Generation</h3>
  70. <a name="index-standard-pattern-names"></a>
  71. <a name="index-pattern-names"></a>
  72. <a name="index-names_002c-pattern"></a>
  73. <p>Here is a table of the instruction names that are meaningful in the RTL
  74. generation pass of the compiler. Giving one of these names to an
  75. instruction pattern tells the RTL generation pass that it can use the
  76. pattern to accomplish a certain task.
  77. </p>
  78. <dl compact="compact">
  79. <dd><a name="index-movm-instruction-pattern"></a>
  80. </dd>
  81. <dt>&lsquo;<samp>mov<var>m</var></samp>&rsquo;</dt>
  82. <dd><p>Here <var>m</var> stands for a two-letter machine mode name, in lowercase.
  83. This instruction pattern moves data with that machine mode from operand
  84. 1 to operand 0. For example, &lsquo;<samp>movsi</samp>&rsquo; moves full-word data.
  85. </p>
  86. <p>If operand 0 is a <code>subreg</code> with mode <var>m</var> of a register whose
  87. own mode is wider than <var>m</var>, the effect of this instruction is
  88. to store the specified value in the part of the register that corresponds
  89. to mode <var>m</var>. Bits outside of <var>m</var>, but which are within the
  90. same target word as the <code>subreg</code> are undefined. Bits which are
  91. outside the target word are left unchanged.
  92. </p>
  93. <p>This class of patterns is special in several ways. First of all, each
  94. of these names up to and including full word size <em>must</em> be defined,
  95. because there is no other way to copy a datum from one place to another.
  96. If there are patterns accepting operands in larger modes,
  97. &lsquo;<samp>mov<var>m</var></samp>&rsquo; must be defined for integer modes of those sizes.
  98. </p>
  99. <p>Second, these patterns are not used solely in the RTL generation pass.
  100. Even the reload pass can generate move insns to copy values from stack
  101. slots into temporary registers. When it does so, one of the operands is
  102. a hard register and the other is an operand that can need to be reloaded
  103. into a register.
  104. </p>
  105. <a name="index-force_005freg"></a>
  106. <p>Therefore, when given such a pair of operands, the pattern must generate
  107. RTL which needs no reloading and needs no temporary registers&mdash;no
  108. registers other than the operands. For example, if you support the
  109. pattern with a <code>define_expand</code>, then in such a case the
  110. <code>define_expand</code> mustn&rsquo;t call <code>force_reg</code> or any other such
  111. function which might generate new pseudo registers.
  112. </p>
  113. <p>This requirement exists even for subword modes on a RISC machine where
  114. fetching those modes from memory normally requires several insns and
  115. some temporary registers.
  116. </p>
  117. <a name="index-change_005faddress"></a>
  118. <p>During reload a memory reference with an invalid address may be passed
  119. as an operand. Such an address will be replaced with a valid address
  120. later in the reload pass. In this case, nothing may be done with the
  121. address except to use it as it stands. If it is copied, it will not be
  122. replaced with a valid address. No attempt should be made to make such
  123. an address into a valid address and no routine (such as
  124. <code>change_address</code>) that will do so may be called. Note that
  125. <code>general_operand</code> will fail when applied to such an address.
  126. </p>
  127. <a name="index-reload_005fin_005fprogress"></a>
  128. <p>The global variable <code>reload_in_progress</code> (which must be explicitly
  129. declared if required) can be used to determine whether such special
  130. handling is required.
  131. </p>
  132. <p>The variety of operands that have reloads depends on the rest of the
  133. machine description, but typically on a RISC machine these can only be
  134. pseudo registers that did not get hard registers, while on other
  135. machines explicit memory references will get optional reloads.
  136. </p>
  137. <p>If a scratch register is required to move an object to or from memory,
  138. it can be allocated using <code>gen_reg_rtx</code> prior to life analysis.
  139. </p>
  140. <p>If there are cases which need scratch registers during or after reload,
  141. you must provide an appropriate secondary_reload target hook.
  142. </p>
  143. <a name="index-can_005fcreate_005fpseudo_005fp"></a>
  144. <p>The macro <code>can_create_pseudo_p</code> can be used to determine if it
  145. is unsafe to create new pseudo registers. If this variable is nonzero, then
  146. it is unsafe to call <code>gen_reg_rtx</code> to allocate a new pseudo.
  147. </p>
  148. <p>The constraints on a &lsquo;<samp>mov<var>m</var></samp>&rsquo; must permit moving any hard
  149. register to any other hard register provided that
  150. <code>HARD_REGNO_MODE_OK</code> permits mode <var>m</var> in both registers and
  151. <code>TARGET_REGISTER_MOVE_COST</code> applied to their classes returns a value
  152. of 2.
  153. </p>
  154. <p>It is obligatory to support floating point &lsquo;<samp>mov<var>m</var></samp>&rsquo;
  155. instructions into and out of any registers that can hold fixed point
  156. values, because unions and structures (which have modes <code>SImode</code> or
  157. <code>DImode</code>) can be in those registers and they may have floating
  158. point members.
  159. </p>
  160. <p>There may also be a need to support fixed point &lsquo;<samp>mov<var>m</var></samp>&rsquo;
  161. instructions in and out of floating point registers. Unfortunately, I
  162. have forgotten why this was so, and I don&rsquo;t know whether it is still
  163. true. If <code>HARD_REGNO_MODE_OK</code> rejects fixed point values in
  164. floating point registers, then the constraints of the fixed point
  165. &lsquo;<samp>mov<var>m</var></samp>&rsquo; instructions must be designed to avoid ever trying to
  166. reload into a floating point register.
  167. </p>
  168. <a name="index-reload_005fin-instruction-pattern"></a>
  169. <a name="index-reload_005fout-instruction-pattern"></a>
  170. </dd>
  171. <dt>&lsquo;<samp>reload_in<var>m</var></samp>&rsquo;</dt>
  172. <dt>&lsquo;<samp>reload_out<var>m</var></samp>&rsquo;</dt>
  173. <dd><p>These named patterns have been obsoleted by the target hook
  174. <code>secondary_reload</code>.
  175. </p>
  176. <p>Like &lsquo;<samp>mov<var>m</var></samp>&rsquo;, but used when a scratch register is required to
  177. move between operand 0 and operand 1. Operand 2 describes the scratch
  178. register. See the discussion of the <code>SECONDARY_RELOAD_CLASS</code>
  179. macro in see <a href="Register-Classes.html#Register-Classes">Register Classes</a>.
  180. </p>
  181. <p>There are special restrictions on the form of the <code>match_operand</code>s
  182. used in these patterns. First, only the predicate for the reload
  183. operand is examined, i.e., <code>reload_in</code> examines operand 1, but not
  184. the predicates for operand 0 or 2. Second, there may be only one
  185. alternative in the constraints. Third, only a single register class
  186. letter may be used for the constraint; subsequent constraint letters
  187. are ignored. As a special exception, an empty constraint string
  188. matches the <code>ALL_REGS</code> register class. This may relieve ports
  189. of the burden of defining an <code>ALL_REGS</code> constraint letter just
  190. for these patterns.
  191. </p>
  192. <a name="index-movstrictm-instruction-pattern"></a>
  193. </dd>
  194. <dt>&lsquo;<samp>movstrict<var>m</var></samp>&rsquo;</dt>
  195. <dd><p>Like &lsquo;<samp>mov<var>m</var></samp>&rsquo; except that if operand 0 is a <code>subreg</code>
  196. with mode <var>m</var> of a register whose natural mode is wider,
  197. the &lsquo;<samp>movstrict<var>m</var></samp>&rsquo; instruction is guaranteed not to alter
  198. any of the register except the part which belongs to mode <var>m</var>.
  199. </p>
  200. <a name="index-movmisalignm-instruction-pattern"></a>
  201. </dd>
  202. <dt>&lsquo;<samp>movmisalign<var>m</var></samp>&rsquo;</dt>
  203. <dd><p>This variant of a move pattern is designed to load or store a value
  204. from a memory address that is not naturally aligned for its mode.
  205. For a store, the memory will be in operand 0; for a load, the memory
  206. will be in operand 1. The other operand is guaranteed not to be a
  207. memory, so that it&rsquo;s easy to tell whether this is a load or store.
  208. </p>
  209. <p>This pattern is used by the autovectorizer, and when expanding a
  210. <code>MISALIGNED_INDIRECT_REF</code> expression.
  211. </p>
  212. <a name="index-load_005fmultiple-instruction-pattern"></a>
  213. </dd>
  214. <dt>&lsquo;<samp>load_multiple</samp>&rsquo;</dt>
  215. <dd><p>Load several consecutive memory locations into consecutive registers.
  216. Operand 0 is the first of the consecutive registers, operand 1
  217. is the first memory location, and operand 2 is a constant: the
  218. number of consecutive registers.
  219. </p>
  220. <p>Define this only if the target machine really has such an instruction;
  221. do not define this if the most efficient way of loading consecutive
  222. registers from memory is to do them one at a time.
  223. </p>
  224. <p>On some machines, there are restrictions as to which consecutive
  225. registers can be stored into memory, such as particular starting or
  226. ending register numbers or only a range of valid counts. For those
  227. machines, use a <code>define_expand</code> (see <a href="Expander-Definitions.html#Expander-Definitions">Expander Definitions</a>)
  228. and make the pattern fail if the restrictions are not met.
  229. </p>
  230. <p>Write the generated insn as a <code>parallel</code> with elements being a
  231. <code>set</code> of one register from the appropriate memory location (you may
  232. also need <code>use</code> or <code>clobber</code> elements). Use a
  233. <code>match_parallel</code> (see <a href="RTL-Template.html#RTL-Template">RTL Template</a>) to recognize the insn. See
  234. <samp>rs6000.md</samp> for examples of the use of this insn pattern.
  235. </p>
  236. <a name="index-store_005fmultiple-instruction-pattern"></a>
  237. </dd>
  238. <dt>&lsquo;<samp>store_multiple</samp>&rsquo;</dt>
  239. <dd><p>Similar to &lsquo;<samp>load_multiple</samp>&rsquo;, but store several consecutive registers
  240. into consecutive memory locations. Operand 0 is the first of the
  241. consecutive memory locations, operand 1 is the first register, and
  242. operand 2 is a constant: the number of consecutive registers.
  243. </p>
  244. <a name="index-vec_005fload_005flanesmn-instruction-pattern"></a>
  245. </dd>
  246. <dt>&lsquo;<samp>vec_load_lanes<var>m</var><var>n</var></samp>&rsquo;</dt>
  247. <dd><p>Perform an interleaved load of several vectors from memory operand 1
  248. into register operand 0. Both operands have mode <var>m</var>. The register
  249. operand is viewed as holding consecutive vectors of mode <var>n</var>,
  250. while the memory operand is a flat array that contains the same number
  251. of elements. The operation is equivalent to:
  252. </p>
  253. <div class="smallexample">
  254. <pre class="smallexample">int c = GET_MODE_SIZE (<var>m</var>) / GET_MODE_SIZE (<var>n</var>);
  255. for (j = 0; j &lt; GET_MODE_NUNITS (<var>n</var>); j++)
  256. for (i = 0; i &lt; c; i++)
  257. operand0[i][j] = operand1[j * c + i];
  258. </pre></div>
  259. <p>For example, &lsquo;<samp>vec_load_lanestiv4hi</samp>&rsquo; loads 8 16-bit values
  260. from memory into a register of mode &lsquo;<samp>TI</samp>&rsquo;. The register
  261. contains two consecutive vectors of mode &lsquo;<samp>V4HI</samp>&rsquo;.
  262. </p>
  263. <p>This pattern can only be used if:
  264. </p><div class="smallexample">
  265. <pre class="smallexample">TARGET_ARRAY_MODE_SUPPORTED_P (<var>n</var>, <var>c</var>)
  266. </pre></div>
  267. <p>is true. GCC assumes that, if a target supports this kind of
  268. instruction for some mode <var>n</var>, it also supports unaligned
  269. loads for vectors of mode <var>n</var>.
  270. </p>
  271. <p>This pattern is not allowed to <code>FAIL</code>.
  272. </p>
  273. <a name="index-vec_005fstore_005flanesmn-instruction-pattern"></a>
  274. </dd>
  275. <dt>&lsquo;<samp>vec_store_lanes<var>m</var><var>n</var></samp>&rsquo;</dt>
  276. <dd><p>Equivalent to &lsquo;<samp>vec_load_lanes<var>m</var><var>n</var></samp>&rsquo;, with the memory
  277. and register operands reversed. That is, the instruction is
  278. equivalent to:
  279. </p>
  280. <div class="smallexample">
  281. <pre class="smallexample">int c = GET_MODE_SIZE (<var>m</var>) / GET_MODE_SIZE (<var>n</var>);
  282. for (j = 0; j &lt; GET_MODE_NUNITS (<var>n</var>); j++)
  283. for (i = 0; i &lt; c; i++)
  284. operand0[j * c + i] = operand1[i][j];
  285. </pre></div>
  286. <p>for a memory operand 0 and register operand 1.
  287. </p>
  288. <p>This pattern is not allowed to <code>FAIL</code>.
  289. </p>
  290. <a name="index-vec_005fsetm-instruction-pattern"></a>
  291. </dd>
  292. <dt>&lsquo;<samp>vec_set<var>m</var></samp>&rsquo;</dt>
  293. <dd><p>Set given field in the vector value. Operand 0 is the vector to modify,
  294. operand 1 is new value of field and operand 2 specify the field index.
  295. </p>
  296. <a name="index-vec_005fextractm-instruction-pattern"></a>
  297. </dd>
  298. <dt>&lsquo;<samp>vec_extract<var>m</var></samp>&rsquo;</dt>
  299. <dd><p>Extract given field from the vector value. Operand 1 is the vector, operand 2
  300. specify field index and operand 0 place to store value into.
  301. </p>
  302. <a name="index-vec_005finitm-instruction-pattern"></a>
  303. </dd>
  304. <dt>&lsquo;<samp>vec_init<var>m</var></samp>&rsquo;</dt>
  305. <dd><p>Initialize the vector to given values. Operand 0 is the vector to initialize
  306. and operand 1 is parallel containing values for individual fields.
  307. </p>
  308. <a name="index-vec_005fcmpmn-instruction-pattern"></a>
  309. </dd>
  310. <dt>&lsquo;<samp>vec_cmp<var>m</var><var>n</var></samp>&rsquo;</dt>
  311. <dd><p>Output a vector comparison. Operand 0 of mode <var>n</var> is the destination for
  312. predicate in operand 1 which is a signed vector comparison with operands of
  313. mode <var>m</var> in operands 2 and 3. Predicate is computed by element-wise
  314. evaluation of the vector comparison with a truth value of all-ones and a false
  315. value of all-zeros.
  316. </p>
  317. <a name="index-vec_005fcmpumn-instruction-pattern"></a>
  318. </dd>
  319. <dt>&lsquo;<samp>vec_cmpu<var>m</var><var>n</var></samp>&rsquo;</dt>
  320. <dd><p>Similar to <code>vec_cmp<var>m</var><var>n</var></code> but perform unsigned vector comparison.
  321. </p>
  322. <a name="index-vec_005fcmpeqmn-instruction-pattern"></a>
  323. </dd>
  324. <dt>&lsquo;<samp>vec_cmpeq<var>m</var><var>n</var></samp>&rsquo;</dt>
  325. <dd><p>Similar to <code>vec_cmp<var>m</var><var>n</var></code> but perform equality or non-equality
  326. vector comparison only. If <code>vec_cmp<var>m</var><var>n</var></code>
  327. or <code>vec_cmpu<var>m</var><var>n</var></code> instruction pattern is supported,
  328. it will be preferred over <code>vec_cmpeq<var>m</var><var>n</var></code>, so there is
  329. no need to define this instruction pattern if the others are supported.
  330. </p>
  331. <a name="index-vcondmn-instruction-pattern"></a>
  332. </dd>
  333. <dt>&lsquo;<samp>vcond<var>m</var><var>n</var></samp>&rsquo;</dt>
  334. <dd><p>Output a conditional vector move. Operand 0 is the destination to
  335. receive a combination of operand 1 and operand 2, which are of mode <var>m</var>,
  336. dependent on the outcome of the predicate in operand 3 which is a signed
  337. vector comparison with operands of mode <var>n</var> in operands 4 and 5. The
  338. modes <var>m</var> and <var>n</var> should have the same size. Operand 0
  339. will be set to the value <var>op1</var> &amp; <var>msk</var> | <var>op2</var> &amp; ~<var>msk</var>
  340. where <var>msk</var> is computed by element-wise evaluation of the vector
  341. comparison with a truth value of all-ones and a false value of all-zeros.
  342. </p>
  343. <a name="index-vcondumn-instruction-pattern"></a>
  344. </dd>
  345. <dt>&lsquo;<samp>vcondu<var>m</var><var>n</var></samp>&rsquo;</dt>
  346. <dd><p>Similar to <code>vcond<var>m</var><var>n</var></code> but performs unsigned vector
  347. comparison.
  348. </p>
  349. <a name="index-vcondeqmn-instruction-pattern"></a>
  350. </dd>
  351. <dt>&lsquo;<samp>vcondeq<var>m</var><var>n</var></samp>&rsquo;</dt>
  352. <dd><p>Similar to <code>vcond<var>m</var><var>n</var></code> but performs equality or
  353. non-equality vector comparison only. If <code>vcond<var>m</var><var>n</var></code>
  354. or <code>vcondu<var>m</var><var>n</var></code> instruction pattern is supported,
  355. it will be preferred over <code>vcondeq<var>m</var><var>n</var></code>, so there is
  356. no need to define this instruction pattern if the others are supported.
  357. </p>
  358. <a name="index-vcond_005fmask_005fmn-instruction-pattern"></a>
  359. </dd>
  360. <dt>&lsquo;<samp>vcond_mask_<var>m</var><var>n</var></samp>&rsquo;</dt>
  361. <dd><p>Similar to <code>vcond<var>m</var><var>n</var></code> but operand 3 holds a pre-computed
  362. result of vector comparison.
  363. </p>
  364. <a name="index-maskloadmn-instruction-pattern"></a>
  365. </dd>
  366. <dt>&lsquo;<samp>maskload<var>m</var><var>n</var></samp>&rsquo;</dt>
  367. <dd><p>Perform a masked load of vector from memory operand 1 of mode <var>m</var>
  368. into register operand 0. Mask is provided in register operand 2 of
  369. mode <var>n</var>.
  370. </p>
  371. <p>This pattern is not allowed to <code>FAIL</code>.
  372. </p>
  373. <a name="index-maskstoremn-instruction-pattern"></a>
  374. </dd>
  375. <dt>&lsquo;<samp>maskstore<var>m</var><var>n</var></samp>&rsquo;</dt>
  376. <dd><p>Perform a masked store of vector from register operand 1 of mode <var>m</var>
  377. into memory operand 0. Mask is provided in register operand 2 of
  378. mode <var>n</var>.
  379. </p>
  380. <p>This pattern is not allowed to <code>FAIL</code>.
  381. </p>
  382. <a name="index-vec_005fpermm-instruction-pattern"></a>
  383. </dd>
  384. <dt>&lsquo;<samp>vec_perm<var>m</var></samp>&rsquo;</dt>
  385. <dd><p>Output a (variable) vector permutation. Operand 0 is the destination
  386. to receive elements from operand 1 and operand 2, which are of mode
  387. <var>m</var>. Operand 3 is the <em>selector</em>. It is an integral mode
  388. vector of the same width and number of elements as mode <var>m</var>.
  389. </p>
  390. <p>The input elements are numbered from 0 in operand 1 through
  391. <em>2*<var>N</var>-1</em> in operand 2. The elements of the selector must
  392. be computed modulo <em>2*<var>N</var></em>. Note that if
  393. <code>rtx_equal_p(operand1, operand2)</code>, this can be implemented
  394. with just operand 1 and selector elements modulo <var>N</var>.
  395. </p>
  396. <p>In order to make things easy for a number of targets, if there is no
  397. &lsquo;<samp>vec_perm</samp>&rsquo; pattern for mode <var>m</var>, but there is for mode <var>q</var>
  398. where <var>q</var> is a vector of <code>QImode</code> of the same width as <var>m</var>,
  399. the middle-end will lower the mode <var>m</var> <code>VEC_PERM_EXPR</code> to
  400. mode <var>q</var>.
  401. </p>
  402. <a name="index-vec_005fperm_005fconstm-instruction-pattern"></a>
  403. </dd>
  404. <dt>&lsquo;<samp>vec_perm_const<var>m</var></samp>&rsquo;</dt>
  405. <dd><p>Like &lsquo;<samp>vec_perm</samp>&rsquo; except that the permutation is a compile-time
  406. constant. That is, operand 3, the <em>selector</em>, is a <code>CONST_VECTOR</code>.
  407. </p>
  408. <p>Some targets cannot perform a permutation with a variable selector,
  409. but can efficiently perform a constant permutation. Further, the
  410. target hook <code>vec_perm_ok</code> is queried to determine if the
  411. specific constant permutation is available efficiently; the named
  412. pattern is never expanded without <code>vec_perm_ok</code> returning true.
  413. </p>
  414. <p>There is no need for a target to supply both &lsquo;<samp>vec_perm<var>m</var></samp>&rsquo;
  415. and &lsquo;<samp>vec_perm_const<var>m</var></samp>&rsquo; if the former can trivially implement
  416. the operation with, say, the vector constant loaded into a register.
  417. </p>
  418. <a name="index-pushm1-instruction-pattern"></a>
  419. </dd>
  420. <dt>&lsquo;<samp>push<var>m</var>1</samp>&rsquo;</dt>
  421. <dd><p>Output a push instruction. Operand 0 is value to push. Used only when
  422. <code>PUSH_ROUNDING</code> is defined. For historical reason, this pattern may be
  423. missing and in such case an <code>mov</code> expander is used instead, with a
  424. <code>MEM</code> expression forming the push operation. The <code>mov</code> expander
  425. method is deprecated.
  426. </p>
  427. <a name="index-addm3-instruction-pattern"></a>
  428. </dd>
  429. <dt>&lsquo;<samp>add<var>m</var>3</samp>&rsquo;</dt>
  430. <dd><p>Add operand 2 and operand 1, storing the result in operand 0. All operands
  431. must have mode <var>m</var>. This can be used even on two-address machines, by
  432. means of constraints requiring operands 1 and 0 to be the same location.
  433. </p>
  434. <a name="index-ssaddm3-instruction-pattern"></a>
  435. <a name="index-usaddm3-instruction-pattern"></a>
  436. <a name="index-subm3-instruction-pattern"></a>
  437. <a name="index-sssubm3-instruction-pattern"></a>
  438. <a name="index-ussubm3-instruction-pattern"></a>
  439. <a name="index-mulm3-instruction-pattern"></a>
  440. <a name="index-ssmulm3-instruction-pattern"></a>
  441. <a name="index-usmulm3-instruction-pattern"></a>
  442. <a name="index-divm3-instruction-pattern"></a>
  443. <a name="index-ssdivm3-instruction-pattern"></a>
  444. <a name="index-udivm3-instruction-pattern"></a>
  445. <a name="index-usdivm3-instruction-pattern"></a>
  446. <a name="index-modm3-instruction-pattern"></a>
  447. <a name="index-umodm3-instruction-pattern"></a>
  448. <a name="index-uminm3-instruction-pattern"></a>
  449. <a name="index-umaxm3-instruction-pattern"></a>
  450. <a name="index-andm3-instruction-pattern"></a>
  451. <a name="index-iorm3-instruction-pattern"></a>
  452. <a name="index-xorm3-instruction-pattern"></a>
  453. </dd>
  454. <dt>&lsquo;<samp>ssadd<var>m</var>3</samp>&rsquo;, &lsquo;<samp>usadd<var>m</var>3</samp>&rsquo;</dt>
  455. <dt>&lsquo;<samp>sub<var>m</var>3</samp>&rsquo;, &lsquo;<samp>sssub<var>m</var>3</samp>&rsquo;, &lsquo;<samp>ussub<var>m</var>3</samp>&rsquo;</dt>
  456. <dt>&lsquo;<samp>mul<var>m</var>3</samp>&rsquo;, &lsquo;<samp>ssmul<var>m</var>3</samp>&rsquo;, &lsquo;<samp>usmul<var>m</var>3</samp>&rsquo;</dt>
  457. <dt>&lsquo;<samp>div<var>m</var>3</samp>&rsquo;, &lsquo;<samp>ssdiv<var>m</var>3</samp>&rsquo;</dt>
  458. <dt>&lsquo;<samp>udiv<var>m</var>3</samp>&rsquo;, &lsquo;<samp>usdiv<var>m</var>3</samp>&rsquo;</dt>
  459. <dt>&lsquo;<samp>mod<var>m</var>3</samp>&rsquo;, &lsquo;<samp>umod<var>m</var>3</samp>&rsquo;</dt>
  460. <dt>&lsquo;<samp>umin<var>m</var>3</samp>&rsquo;, &lsquo;<samp>umax<var>m</var>3</samp>&rsquo;</dt>
  461. <dt>&lsquo;<samp>and<var>m</var>3</samp>&rsquo;, &lsquo;<samp>ior<var>m</var>3</samp>&rsquo;, &lsquo;<samp>xor<var>m</var>3</samp>&rsquo;</dt>
  462. <dd><p>Similar, for other arithmetic operations.
  463. </p>
  464. <a name="index-addvm4-instruction-pattern"></a>
  465. </dd>
  466. <dt>&lsquo;<samp>addv<var>m</var>4</samp>&rsquo;</dt>
  467. <dd><p>Like <code>add<var>m</var>3</code> but takes a <code>code_label</code> as operand 3 and
  468. emits code to jump to it if signed overflow occurs during the addition.
  469. This pattern is used to implement the built-in functions performing
  470. signed integer addition with overflow checking.
  471. </p>
  472. <a name="index-subvm4-instruction-pattern"></a>
  473. <a name="index-mulvm4-instruction-pattern"></a>
  474. </dd>
  475. <dt>&lsquo;<samp>subv<var>m</var>4</samp>&rsquo;, &lsquo;<samp>mulv<var>m</var>4</samp>&rsquo;</dt>
  476. <dd><p>Similar, for other signed arithmetic operations.
  477. </p>
  478. <a name="index-uaddvm4-instruction-pattern"></a>
  479. </dd>
  480. <dt>&lsquo;<samp>uaddv<var>m</var>4</samp>&rsquo;</dt>
  481. <dd><p>Like <code>addv<var>m</var>4</code> but for unsigned addition. That is to
  482. say, the operation is the same as signed addition but the jump
  483. is taken only on unsigned overflow.
  484. </p>
  485. <a name="index-usubvm4-instruction-pattern"></a>
  486. <a name="index-umulvm4-instruction-pattern"></a>
  487. </dd>
  488. <dt>&lsquo;<samp>usubv<var>m</var>4</samp>&rsquo;, &lsquo;<samp>umulv<var>m</var>4</samp>&rsquo;</dt>
  489. <dd><p>Similar, for other unsigned arithmetic operations.
  490. </p>
  491. <a name="index-addptrm3-instruction-pattern"></a>
  492. </dd>
  493. <dt>&lsquo;<samp>addptr<var>m</var>3</samp>&rsquo;</dt>
  494. <dd><p>Like <code>add<var>m</var>3</code> but is guaranteed to only be used for address
  495. calculations. The expanded code is not allowed to clobber the
  496. condition code. It only needs to be defined if <code>add<var>m</var>3</code>
  497. sets the condition code. If adds used for address calculations and
  498. normal adds are not compatible it is required to expand a distinct
  499. pattern (e.g. using an unspec). The pattern is used by LRA to emit
  500. address calculations. <code>add<var>m</var>3</code> is used if
  501. <code>addptr<var>m</var>3</code> is not defined.
  502. </p>
  503. <a name="index-fmam4-instruction-pattern"></a>
  504. </dd>
  505. <dt>&lsquo;<samp>fma<var>m</var>4</samp>&rsquo;</dt>
  506. <dd><p>Multiply operand 2 and operand 1, then add operand 3, storing the
  507. result in operand 0 without doing an intermediate rounding step. All
  508. operands must have mode <var>m</var>. This pattern is used to implement
  509. the <code>fma</code>, <code>fmaf</code>, and <code>fmal</code> builtin functions from
  510. the ISO C99 standard.
  511. </p>
  512. <a name="index-fmsm4-instruction-pattern"></a>
  513. </dd>
  514. <dt>&lsquo;<samp>fms<var>m</var>4</samp>&rsquo;</dt>
  515. <dd><p>Like <code>fma<var>m</var>4</code>, except operand 3 subtracted from the
  516. product instead of added to the product. This is represented
  517. in the rtl as
  518. </p>
  519. <div class="smallexample">
  520. <pre class="smallexample">(fma:<var>m</var> <var>op1</var> <var>op2</var> (neg:<var>m</var> <var>op3</var>))
  521. </pre></div>
  522. <a name="index-fnmam4-instruction-pattern"></a>
  523. </dd>
  524. <dt>&lsquo;<samp>fnma<var>m</var>4</samp>&rsquo;</dt>
  525. <dd><p>Like <code>fma<var>m</var>4</code> except that the intermediate product
  526. is negated before being added to operand 3. This is represented
  527. in the rtl as
  528. </p>
  529. <div class="smallexample">
  530. <pre class="smallexample">(fma:<var>m</var> (neg:<var>m</var> <var>op1</var>) <var>op2</var> <var>op3</var>)
  531. </pre></div>
  532. <a name="index-fnmsm4-instruction-pattern"></a>
  533. </dd>
  534. <dt>&lsquo;<samp>fnms<var>m</var>4</samp>&rsquo;</dt>
  535. <dd><p>Like <code>fms<var>m</var>4</code> except that the intermediate product
  536. is negated before subtracting operand 3. This is represented
  537. in the rtl as
  538. </p>
  539. <div class="smallexample">
  540. <pre class="smallexample">(fma:<var>m</var> (neg:<var>m</var> <var>op1</var>) <var>op2</var> (neg:<var>m</var> <var>op3</var>))
  541. </pre></div>
  542. <a name="index-minm3-instruction-pattern"></a>
  543. <a name="index-maxm3-instruction-pattern"></a>
  544. </dd>
  545. <dt>&lsquo;<samp>smin<var>m</var>3</samp>&rsquo;, &lsquo;<samp>smax<var>m</var>3</samp>&rsquo;</dt>
  546. <dd><p>Signed minimum and maximum operations. When used with floating point,
  547. if both operands are zeros, or if either operand is <code>NaN</code>, then
  548. it is unspecified which of the two operands is returned as the result.
  549. </p>
  550. <a name="index-fminm3-instruction-pattern"></a>
  551. <a name="index-fmaxm3-instruction-pattern"></a>
  552. </dd>
  553. <dt>&lsquo;<samp>fmin<var>m</var>3</samp>&rsquo;, &lsquo;<samp>fmax<var>m</var>3</samp>&rsquo;</dt>
  554. <dd><p>IEEE-conformant minimum and maximum operations. If one operand is a quiet
  555. <code>NaN</code>, then the other operand is returned. If both operands are quiet
  556. <code>NaN</code>, then a quiet <code>NaN</code> is returned. In the case when gcc supports
  557. signaling <code>NaN</code> (-fsignaling-nans) an invalid floating point exception is
  558. raised and a quiet <code>NaN</code> is returned.
  559. </p>
  560. <p>All operands have mode <var>m</var>, which is a scalar or vector
  561. floating-point mode. These patterns are not allowed to <code>FAIL</code>.
  562. </p>
  563. <a name="index-reduc_005fsmin_005fscal_005fm-instruction-pattern"></a>
  564. <a name="index-reduc_005fsmax_005fscal_005fm-instruction-pattern"></a>
  565. </dd>
  566. <dt>&lsquo;<samp>reduc_smin_scal_<var>m</var></samp>&rsquo;, &lsquo;<samp>reduc_smax_scal_<var>m</var></samp>&rsquo;</dt>
  567. <dd><p>Find the signed minimum/maximum of the elements of a vector. The vector is
  568. operand 1, and operand 0 is the scalar result, with mode equal to the mode of
  569. the elements of the input vector.
  570. </p>
  571. <a name="index-reduc_005fumin_005fscal_005fm-instruction-pattern"></a>
  572. <a name="index-reduc_005fumax_005fscal_005fm-instruction-pattern"></a>
  573. </dd>
  574. <dt>&lsquo;<samp>reduc_umin_scal_<var>m</var></samp>&rsquo;, &lsquo;<samp>reduc_umax_scal_<var>m</var></samp>&rsquo;</dt>
  575. <dd><p>Find the unsigned minimum/maximum of the elements of a vector. The vector is
  576. operand 1, and operand 0 is the scalar result, with mode equal to the mode of
  577. the elements of the input vector.
  578. </p>
  579. <a name="index-reduc_005fplus_005fscal_005fm-instruction-pattern"></a>
  580. </dd>
  581. <dt>&lsquo;<samp>reduc_plus_scal_<var>m</var></samp>&rsquo;</dt>
  582. <dd><p>Compute the sum of the elements of a vector. The vector is operand 1, and
  583. operand 0 is the scalar result, with mode equal to the mode of the elements of
  584. the input vector.
  585. </p>
  586. <a name="index-sdot_005fprodm-instruction-pattern"></a>
  587. </dd>
  588. <dt>&lsquo;<samp>sdot_prod<var>m</var></samp>&rsquo;</dt>
  589. <dd><a name="index-udot_005fprodm-instruction-pattern"></a>
  590. </dd>
  591. <dt>&lsquo;<samp>udot_prod<var>m</var></samp>&rsquo;</dt>
  592. <dd><p>Compute the sum of the products of two signed/unsigned elements.
  593. Operand 1 and operand 2 are of the same mode. Their product, which is of a
  594. wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
  595. wider than the mode of the product. The result is placed in operand 0, which
  596. is of the same mode as operand 3.
  597. </p>
  598. <a name="index-ssadm-instruction-pattern"></a>
  599. </dd>
  600. <dt>&lsquo;<samp>ssad<var>m</var></samp>&rsquo;</dt>
  601. <dd><a name="index-usadm-instruction-pattern"></a>
  602. </dd>
  603. <dt>&lsquo;<samp>usad<var>m</var></samp>&rsquo;</dt>
  604. <dd><p>Compute the sum of absolute differences of two signed/unsigned elements.
  605. Operand 1 and operand 2 are of the same mode. Their absolute difference, which
  606. is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
  607. equal or wider than the mode of the absolute difference. The result is placed
  608. in operand 0, which is of the same mode as operand 3.
  609. </p>
  610. <a name="index-widen_005fssumm3-instruction-pattern"></a>
  611. </dd>
  612. <dt>&lsquo;<samp>widen_ssum<var>m3</var></samp>&rsquo;</dt>
  613. <dd><a name="index-widen_005fusumm3-instruction-pattern"></a>
  614. </dd>
  615. <dt>&lsquo;<samp>widen_usum<var>m3</var></samp>&rsquo;</dt>
  616. <dd><p>Operands 0 and 2 are of the same mode, which is wider than the mode of
  617. operand 1. Add operand 1 to operand 2 and place the widened result in
  618. operand 0. (This is used express accumulation of elements into an accumulator
  619. of a wider mode.)
  620. </p>
  621. <a name="index-vec_005fshr_005fm-instruction-pattern"></a>
  622. </dd>
  623. <dt>&lsquo;<samp>vec_shr_<var>m</var></samp>&rsquo;</dt>
  624. <dd><p>Whole vector right shift in bits, i.e. towards element 0.
  625. Operand 1 is a vector to be shifted.
  626. Operand 2 is an integer shift amount in bits.
  627. Operand 0 is where the resulting shifted vector is stored.
  628. The output and input vectors should have the same modes.
  629. </p>
  630. <a name="index-vec_005fpack_005ftrunc_005fm-instruction-pattern"></a>
  631. </dd>
  632. <dt>&lsquo;<samp>vec_pack_trunc_<var>m</var></samp>&rsquo;</dt>
  633. <dd><p>Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
  634. are vectors of the same mode having N integral or floating point elements
  635. of size S. Operand 0 is the resulting vector in which 2*N elements of
  636. size N/2 are concatenated after narrowing them down using truncation.
  637. </p>
  638. <a name="index-vec_005fpack_005fssat_005fm-instruction-pattern"></a>
  639. <a name="index-vec_005fpack_005fusat_005fm-instruction-pattern"></a>
  640. </dd>
  641. <dt>&lsquo;<samp>vec_pack_ssat_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_pack_usat_<var>m</var></samp>&rsquo;</dt>
  642. <dd><p>Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
  643. are vectors of the same mode having N integral elements of size S.
  644. Operand 0 is the resulting vector in which the elements of the two input
  645. vectors are concatenated after narrowing them down using signed/unsigned
  646. saturating arithmetic.
  647. </p>
  648. <a name="index-vec_005fpack_005fsfix_005ftrunc_005fm-instruction-pattern"></a>
  649. <a name="index-vec_005fpack_005fufix_005ftrunc_005fm-instruction-pattern"></a>
  650. </dd>
  651. <dt>&lsquo;<samp>vec_pack_sfix_trunc_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_pack_ufix_trunc_<var>m</var></samp>&rsquo;</dt>
  652. <dd><p>Narrow, convert to signed/unsigned integral type and merge the elements
  653. of two vectors. Operands 1 and 2 are vectors of the same mode having N
  654. floating point elements of size S. Operand 0 is the resulting vector
  655. in which 2*N elements of size N/2 are concatenated.
  656. </p>
  657. <a name="index-vec_005funpacks_005fhi_005fm-instruction-pattern"></a>
  658. <a name="index-vec_005funpacks_005flo_005fm-instruction-pattern"></a>
  659. </dd>
  660. <dt>&lsquo;<samp>vec_unpacks_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_unpacks_lo_<var>m</var></samp>&rsquo;</dt>
  661. <dd><p>Extract and widen (promote) the high/low part of a vector of signed
  662. integral or floating point elements. The input vector (operand 1) has N
  663. elements of size S. Widen (promote) the high/low elements of the vector
  664. using signed or floating point extension and place the resulting N/2
  665. values of size 2*S in the output vector (operand 0).
  666. </p>
  667. <a name="index-vec_005funpacku_005fhi_005fm-instruction-pattern"></a>
  668. <a name="index-vec_005funpacku_005flo_005fm-instruction-pattern"></a>
  669. </dd>
  670. <dt>&lsquo;<samp>vec_unpacku_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_unpacku_lo_<var>m</var></samp>&rsquo;</dt>
  671. <dd><p>Extract and widen (promote) the high/low part of a vector of unsigned
  672. integral elements. The input vector (operand 1) has N elements of size S.
  673. Widen (promote) the high/low elements of the vector using zero extension and
  674. place the resulting N/2 values of size 2*S in the output vector (operand 0).
  675. </p>
  676. <a name="index-vec_005funpacks_005ffloat_005fhi_005fm-instruction-pattern"></a>
  677. <a name="index-vec_005funpacks_005ffloat_005flo_005fm-instruction-pattern"></a>
  678. <a name="index-vec_005funpacku_005ffloat_005fhi_005fm-instruction-pattern"></a>
  679. <a name="index-vec_005funpacku_005ffloat_005flo_005fm-instruction-pattern"></a>
  680. </dd>
  681. <dt>&lsquo;<samp>vec_unpacks_float_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_unpacks_float_lo_<var>m</var></samp>&rsquo;</dt>
  682. <dt>&lsquo;<samp>vec_unpacku_float_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_unpacku_float_lo_<var>m</var></samp>&rsquo;</dt>
  683. <dd><p>Extract, convert to floating point type and widen the high/low part of a
  684. vector of signed/unsigned integral elements. The input vector (operand 1)
  685. has N elements of size S. Convert the high/low elements of the vector using
  686. floating point conversion and place the resulting N/2 values of size 2*S in
  687. the output vector (operand 0).
  688. </p>
  689. <a name="index-vec_005fwiden_005fumult_005fhi_005fm-instruction-pattern"></a>
  690. <a name="index-vec_005fwiden_005fumult_005flo_005fm-instruction-pattern"></a>
  691. <a name="index-vec_005fwiden_005fsmult_005fhi_005fm-instruction-pattern"></a>
  692. <a name="index-vec_005fwiden_005fsmult_005flo_005fm-instruction-pattern"></a>
  693. <a name="index-vec_005fwiden_005fumult_005feven_005fm-instruction-pattern"></a>
  694. <a name="index-vec_005fwiden_005fumult_005fodd_005fm-instruction-pattern"></a>
  695. <a name="index-vec_005fwiden_005fsmult_005feven_005fm-instruction-pattern"></a>
  696. <a name="index-vec_005fwiden_005fsmult_005fodd_005fm-instruction-pattern"></a>
  697. </dd>
  698. <dt>&lsquo;<samp>vec_widen_umult_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_umult_lo_<var>m</var></samp>&rsquo;</dt>
  699. <dt>&lsquo;<samp>vec_widen_smult_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_smult_lo_<var>m</var></samp>&rsquo;</dt>
  700. <dt>&lsquo;<samp>vec_widen_umult_even_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_umult_odd_<var>m</var></samp>&rsquo;</dt>
  701. <dt>&lsquo;<samp>vec_widen_smult_even_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_smult_odd_<var>m</var></samp>&rsquo;</dt>
  702. <dd><p>Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
  703. are vectors with N signed/unsigned elements of size S. Multiply the high/low
  704. or even/odd elements of the two vectors, and put the N/2 products of size 2*S
  705. in the output vector (operand 0). A target shouldn&rsquo;t implement even/odd pattern
  706. pair if it is less efficient than lo/hi one.
  707. </p>
  708. <a name="index-vec_005fwiden_005fushiftl_005fhi_005fm-instruction-pattern"></a>
  709. <a name="index-vec_005fwiden_005fushiftl_005flo_005fm-instruction-pattern"></a>
  710. <a name="index-vec_005fwiden_005fsshiftl_005fhi_005fm-instruction-pattern"></a>
  711. <a name="index-vec_005fwiden_005fsshiftl_005flo_005fm-instruction-pattern"></a>
  712. </dd>
  713. <dt>&lsquo;<samp>vec_widen_ushiftl_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_ushiftl_lo_<var>m</var></samp>&rsquo;</dt>
  714. <dt>&lsquo;<samp>vec_widen_sshiftl_hi_<var>m</var></samp>&rsquo;, &lsquo;<samp>vec_widen_sshiftl_lo_<var>m</var></samp>&rsquo;</dt>
  715. <dd><p>Signed/Unsigned widening shift left. The first input (operand 1) is a vector
  716. with N signed/unsigned elements of size S. Operand 2 is a constant. Shift
  717. the high/low elements of operand 1, and put the N/2 results of size 2*S in the
  718. output vector (operand 0).
  719. </p>
  720. <a name="index-mulhisi3-instruction-pattern"></a>
  721. </dd>
  722. <dt>&lsquo;<samp>mulhisi3</samp>&rsquo;</dt>
  723. <dd><p>Multiply operands 1 and 2, which have mode <code>HImode</code>, and store
  724. a <code>SImode</code> product in operand 0.
  725. </p>
  726. <a name="index-mulqihi3-instruction-pattern"></a>
  727. <a name="index-mulsidi3-instruction-pattern"></a>
  728. </dd>
  729. <dt>&lsquo;<samp>mulqihi3</samp>&rsquo;, &lsquo;<samp>mulsidi3</samp>&rsquo;</dt>
  730. <dd><p>Similar widening-multiplication instructions of other widths.
  731. </p>
  732. <a name="index-umulqihi3-instruction-pattern"></a>
  733. <a name="index-umulhisi3-instruction-pattern"></a>
  734. <a name="index-umulsidi3-instruction-pattern"></a>
  735. </dd>
  736. <dt>&lsquo;<samp>umulqihi3</samp>&rsquo;, &lsquo;<samp>umulhisi3</samp>&rsquo;, &lsquo;<samp>umulsidi3</samp>&rsquo;</dt>
  737. <dd><p>Similar widening-multiplication instructions that do unsigned
  738. multiplication.
  739. </p>
  740. <a name="index-usmulqihi3-instruction-pattern"></a>
  741. <a name="index-usmulhisi3-instruction-pattern"></a>
  742. <a name="index-usmulsidi3-instruction-pattern"></a>
  743. </dd>
  744. <dt>&lsquo;<samp>usmulqihi3</samp>&rsquo;, &lsquo;<samp>usmulhisi3</samp>&rsquo;, &lsquo;<samp>usmulsidi3</samp>&rsquo;</dt>
  745. <dd><p>Similar widening-multiplication instructions that interpret the first
  746. operand as unsigned and the second operand as signed, then do a signed
  747. multiplication.
  748. </p>
  749. <a name="index-smulm3_005fhighpart-instruction-pattern"></a>
  750. </dd>
  751. <dt>&lsquo;<samp>smul<var>m</var>3_highpart</samp>&rsquo;</dt>
  752. <dd><p>Perform a signed multiplication of operands 1 and 2, which have mode
  753. <var>m</var>, and store the most significant half of the product in operand 0.
  754. The least significant half of the product is discarded.
  755. </p>
  756. <a name="index-umulm3_005fhighpart-instruction-pattern"></a>
  757. </dd>
  758. <dt>&lsquo;<samp>umul<var>m</var>3_highpart</samp>&rsquo;</dt>
  759. <dd><p>Similar, but the multiplication is unsigned.
  760. </p>
  761. <a name="index-maddmn4-instruction-pattern"></a>
  762. </dd>
  763. <dt>&lsquo;<samp>madd<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  764. <dd><p>Multiply operands 1 and 2, sign-extend them to mode <var>n</var>, add
  765. operand 3, and store the result in operand 0. Operands 1 and 2
  766. have mode <var>m</var> and operands 0 and 3 have mode <var>n</var>.
  767. Both modes must be integer or fixed-point modes and <var>n</var> must be twice
  768. the size of <var>m</var>.
  769. </p>
  770. <p>In other words, <code>madd<var>m</var><var>n</var>4</code> is like
  771. <code>mul<var>m</var><var>n</var>3</code> except that it also adds operand 3.
  772. </p>
  773. <p>These instructions are not allowed to <code>FAIL</code>.
  774. </p>
  775. <a name="index-umaddmn4-instruction-pattern"></a>
  776. </dd>
  777. <dt>&lsquo;<samp>umadd<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  778. <dd><p>Like <code>madd<var>m</var><var>n</var>4</code>, but zero-extend the multiplication
  779. operands instead of sign-extending them.
  780. </p>
  781. <a name="index-ssmaddmn4-instruction-pattern"></a>
  782. </dd>
  783. <dt>&lsquo;<samp>ssmadd<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  784. <dd><p>Like <code>madd<var>m</var><var>n</var>4</code>, but all involved operations must be
  785. signed-saturating.
  786. </p>
  787. <a name="index-usmaddmn4-instruction-pattern"></a>
  788. </dd>
  789. <dt>&lsquo;<samp>usmadd<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  790. <dd><p>Like <code>umadd<var>m</var><var>n</var>4</code>, but all involved operations must be
  791. unsigned-saturating.
  792. </p>
  793. <a name="index-msubmn4-instruction-pattern"></a>
  794. </dd>
  795. <dt>&lsquo;<samp>msub<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  796. <dd><p>Multiply operands 1 and 2, sign-extend them to mode <var>n</var>, subtract the
  797. result from operand 3, and store the result in operand 0. Operands 1 and 2
  798. have mode <var>m</var> and operands 0 and 3 have mode <var>n</var>.
  799. Both modes must be integer or fixed-point modes and <var>n</var> must be twice
  800. the size of <var>m</var>.
  801. </p>
  802. <p>In other words, <code>msub<var>m</var><var>n</var>4</code> is like
  803. <code>mul<var>m</var><var>n</var>3</code> except that it also subtracts the result
  804. from operand 3.
  805. </p>
  806. <p>These instructions are not allowed to <code>FAIL</code>.
  807. </p>
  808. <a name="index-umsubmn4-instruction-pattern"></a>
  809. </dd>
  810. <dt>&lsquo;<samp>umsub<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  811. <dd><p>Like <code>msub<var>m</var><var>n</var>4</code>, but zero-extend the multiplication
  812. operands instead of sign-extending them.
  813. </p>
  814. <a name="index-ssmsubmn4-instruction-pattern"></a>
  815. </dd>
  816. <dt>&lsquo;<samp>ssmsub<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  817. <dd><p>Like <code>msub<var>m</var><var>n</var>4</code>, but all involved operations must be
  818. signed-saturating.
  819. </p>
  820. <a name="index-usmsubmn4-instruction-pattern"></a>
  821. </dd>
  822. <dt>&lsquo;<samp>usmsub<var>m</var><var>n</var>4</samp>&rsquo;</dt>
  823. <dd><p>Like <code>umsub<var>m</var><var>n</var>4</code>, but all involved operations must be
  824. unsigned-saturating.
  825. </p>
  826. <a name="index-divmodm4-instruction-pattern"></a>
  827. </dd>
  828. <dt>&lsquo;<samp>divmod<var>m</var>4</samp>&rsquo;</dt>
  829. <dd><p>Signed division that produces both a quotient and a remainder.
  830. Operand 1 is divided by operand 2 to produce a quotient stored
  831. in operand 0 and a remainder stored in operand 3.
  832. </p>
  833. <p>For machines with an instruction that produces both a quotient and a
  834. remainder, provide a pattern for &lsquo;<samp>divmod<var>m</var>4</samp>&rsquo; but do not
  835. provide patterns for &lsquo;<samp>div<var>m</var>3</samp>&rsquo; and &lsquo;<samp>mod<var>m</var>3</samp>&rsquo;. This
  836. allows optimization in the relatively common case when both the quotient
  837. and remainder are computed.
  838. </p>
  839. <p>If an instruction that just produces a quotient or just a remainder
  840. exists and is more efficient than the instruction that produces both,
  841. write the output routine of &lsquo;<samp>divmod<var>m</var>4</samp>&rsquo; to call
  842. <code>find_reg_note</code> and look for a <code>REG_UNUSED</code> note on the
  843. quotient or remainder and generate the appropriate instruction.
  844. </p>
  845. <a name="index-udivmodm4-instruction-pattern"></a>
  846. </dd>
  847. <dt>&lsquo;<samp>udivmod<var>m</var>4</samp>&rsquo;</dt>
  848. <dd><p>Similar, but does unsigned division.
  849. </p>
  850. <a name="shift-patterns"></a><a name="index-ashlm3-instruction-pattern"></a>
  851. <a name="index-ssashlm3-instruction-pattern"></a>
  852. <a name="index-usashlm3-instruction-pattern"></a>
  853. </dd>
  854. <dt>&lsquo;<samp>ashl<var>m</var>3</samp>&rsquo;, &lsquo;<samp>ssashl<var>m</var>3</samp>&rsquo;, &lsquo;<samp>usashl<var>m</var>3</samp>&rsquo;</dt>
  855. <dd><p>Arithmetic-shift operand 1 left by a number of bits specified by operand
  856. 2, and store the result in operand 0. Here <var>m</var> is the mode of
  857. operand 0 and operand 1; operand 2&rsquo;s mode is specified by the
  858. instruction pattern, and the compiler will convert the operand to that
  859. mode before generating the instruction. The shift or rotate expander
  860. or instruction pattern should explicitly specify the mode of the operand 2,
  861. it should never be <code>VOIDmode</code>. The meaning of out-of-range shift
  862. counts can optionally be specified by <code>TARGET_SHIFT_TRUNCATION_MASK</code>.
  863. See <a href="Misc.html#TARGET_005fSHIFT_005fTRUNCATION_005fMASK">TARGET_SHIFT_TRUNCATION_MASK</a>. Operand 2 is always a scalar type.
  864. </p>
  865. <a name="index-ashrm3-instruction-pattern"></a>
  866. <a name="index-lshrm3-instruction-pattern"></a>
  867. <a name="index-rotlm3-instruction-pattern"></a>
  868. <a name="index-rotrm3-instruction-pattern"></a>
  869. </dd>
  870. <dt>&lsquo;<samp>ashr<var>m</var>3</samp>&rsquo;, &lsquo;<samp>lshr<var>m</var>3</samp>&rsquo;, &lsquo;<samp>rotl<var>m</var>3</samp>&rsquo;, &lsquo;<samp>rotr<var>m</var>3</samp>&rsquo;</dt>
  871. <dd><p>Other shift and rotate instructions, analogous to the
  872. <code>ashl<var>m</var>3</code> instructions. Operand 2 is always a scalar type.
  873. </p>
  874. <a name="index-vashlm3-instruction-pattern"></a>
  875. <a name="index-vashrm3-instruction-pattern"></a>
  876. <a name="index-vlshrm3-instruction-pattern"></a>
  877. <a name="index-vrotlm3-instruction-pattern"></a>
  878. <a name="index-vrotrm3-instruction-pattern"></a>
  879. </dd>
  880. <dt>&lsquo;<samp>vashl<var>m</var>3</samp>&rsquo;, &lsquo;<samp>vashr<var>m</var>3</samp>&rsquo;, &lsquo;<samp>vlshr<var>m</var>3</samp>&rsquo;, &lsquo;<samp>vrotl<var>m</var>3</samp>&rsquo;, &lsquo;<samp>vrotr<var>m</var>3</samp>&rsquo;</dt>
  881. <dd><p>Vector shift and rotate instructions that take vectors as operand 2
  882. instead of a scalar type.
  883. </p>
  884. <a name="index-bswapm2-instruction-pattern"></a>
  885. </dd>
  886. <dt>&lsquo;<samp>bswap<var>m</var>2</samp>&rsquo;</dt>
  887. <dd><p>Reverse the order of bytes of operand 1 and store the result in operand 0.
  888. </p>
  889. <a name="index-negm2-instruction-pattern"></a>
  890. <a name="index-ssnegm2-instruction-pattern"></a>
  891. <a name="index-usnegm2-instruction-pattern"></a>
  892. </dd>
  893. <dt>&lsquo;<samp>neg<var>m</var>2</samp>&rsquo;, &lsquo;<samp>ssneg<var>m</var>2</samp>&rsquo;, &lsquo;<samp>usneg<var>m</var>2</samp>&rsquo;</dt>
  894. <dd><p>Negate operand 1 and store the result in operand 0.
  895. </p>
  896. <a name="index-negvm3-instruction-pattern"></a>
  897. </dd>
  898. <dt>&lsquo;<samp>negv<var>m</var>3</samp>&rsquo;</dt>
  899. <dd><p>Like <code>neg<var>m</var>2</code> but takes a <code>code_label</code> as operand 2 and
  900. emits code to jump to it if signed overflow occurs during the negation.
  901. </p>
  902. <a name="index-absm2-instruction-pattern"></a>
  903. </dd>
  904. <dt>&lsquo;<samp>abs<var>m</var>2</samp>&rsquo;</dt>
  905. <dd><p>Store the absolute value of operand 1 into operand 0.
  906. </p>
  907. <a name="index-sqrtm2-instruction-pattern"></a>
  908. </dd>
  909. <dt>&lsquo;<samp>sqrt<var>m</var>2</samp>&rsquo;</dt>
  910. <dd><p>Store the square root of operand 1 into operand 0. Both operands have
  911. mode <var>m</var>, which is a scalar or vector floating-point mode.
  912. </p>
  913. <p>This pattern is not allowed to <code>FAIL</code>.
  914. </p>
  915. <a name="index-rsqrtm2-instruction-pattern"></a>
  916. </dd>
  917. <dt>&lsquo;<samp>rsqrt<var>m</var>2</samp>&rsquo;</dt>
  918. <dd><p>Store the reciprocal of the square root of operand 1 into operand 0.
  919. Both operands have mode <var>m</var>, which is a scalar or vector
  920. floating-point mode.
  921. </p>
  922. <p>On most architectures this pattern is only approximate, so either
  923. its C condition or the <code>TARGET_OPTAB_SUPPORTED_P</code> hook should
  924. check for the appropriate math flags. (Using the C condition is
  925. more direct, but using <code>TARGET_OPTAB_SUPPORTED_P</code> can be useful
  926. if a target-specific built-in also uses the &lsquo;<samp>rsqrt<var>m</var>2</samp>&rsquo;
  927. pattern.)
  928. </p>
  929. <p>This pattern is not allowed to <code>FAIL</code>.
  930. </p>
  931. <a name="index-fmodm3-instruction-pattern"></a>
  932. </dd>
  933. <dt>&lsquo;<samp>fmod<var>m</var>3</samp>&rsquo;</dt>
  934. <dd><p>Store the remainder of dividing operand 1 by operand 2 into
  935. operand 0, rounded towards zero to an integer. All operands have
  936. mode <var>m</var>, which is a scalar or vector floating-point mode.
  937. </p>
  938. <p>This pattern is not allowed to <code>FAIL</code>.
  939. </p>
  940. <a name="index-remainderm3-instruction-pattern"></a>
  941. </dd>
  942. <dt>&lsquo;<samp>remainder<var>m</var>3</samp>&rsquo;</dt>
  943. <dd><p>Store the remainder of dividing operand 1 by operand 2 into
  944. operand 0, rounded to the nearest integer. All operands have
  945. mode <var>m</var>, which is a scalar or vector floating-point mode.
  946. </p>
  947. <p>This pattern is not allowed to <code>FAIL</code>.
  948. </p>
  949. <a name="index-scalbm3-instruction-pattern"></a>
  950. </dd>
  951. <dt>&lsquo;<samp>scalb<var>m</var>3</samp>&rsquo;</dt>
  952. <dd><p>Raise <code>FLT_RADIX</code> to the power of operand 2, multiply it by
  953. operand 1, and store the result in operand 0. All operands have
  954. mode <var>m</var>, which is a scalar or vector floating-point mode.
  955. </p>
  956. <p>This pattern is not allowed to <code>FAIL</code>.
  957. </p>
  958. <a name="index-ldexpm3-instruction-pattern"></a>
  959. </dd>
  960. <dt>&lsquo;<samp>ldexp<var>m</var>3</samp>&rsquo;</dt>
  961. <dd><p>Raise 2 to the power of operand 2, multiply it by operand 1, and store
  962. the result in operand 0. Operands 0 and 1 have mode <var>m</var>, which is
  963. a scalar or vector floating-point mode. Operand 2&rsquo;s mode has
  964. the same number of elements as <var>m</var> and each element is wide
  965. enough to store an <code>int</code>. The integers are signed.
  966. </p>
  967. <p>This pattern is not allowed to <code>FAIL</code>.
  968. </p>
  969. <a name="index-cosm2-instruction-pattern"></a>
  970. </dd>
  971. <dt>&lsquo;<samp>cos<var>m</var>2</samp>&rsquo;</dt>
  972. <dd><p>Store the cosine of operand 1 into operand 0. Both operands have
  973. mode <var>m</var>, which is a scalar or vector floating-point mode.
  974. </p>
  975. <p>This pattern is not allowed to <code>FAIL</code>.
  976. </p>
  977. <a name="index-sinm2-instruction-pattern"></a>
  978. </dd>
  979. <dt>&lsquo;<samp>sin<var>m</var>2</samp>&rsquo;</dt>
  980. <dd><p>Store the sine of operand 1 into operand 0. Both operands have
  981. mode <var>m</var>, which is a scalar or vector floating-point mode.
  982. </p>
  983. <p>This pattern is not allowed to <code>FAIL</code>.
  984. </p>
  985. <a name="index-sincosm3-instruction-pattern"></a>
  986. </dd>
  987. <dt>&lsquo;<samp>sincos<var>m</var>3</samp>&rsquo;</dt>
  988. <dd><p>Store the cosine of operand 2 into operand 0 and the sine of
  989. operand 2 into operand 1. All operands have mode <var>m</var>,
  990. which is a scalar or vector floating-point mode.
  991. </p>
  992. <p>Targets that can calculate the sine and cosine simultaneously can
  993. implement this pattern as opposed to implementing individual
  994. <code>sin<var>m</var>2</code> and <code>cos<var>m</var>2</code> patterns. The <code>sin</code>
  995. and <code>cos</code> built-in functions will then be expanded to the
  996. <code>sincos<var>m</var>3</code> pattern, with one of the output values
  997. left unused.
  998. </p>
  999. <a name="index-tanm2-instruction-pattern"></a>
  1000. </dd>
  1001. <dt>&lsquo;<samp>tan<var>m</var>2</samp>&rsquo;</dt>
  1002. <dd><p>Store the tangent of operand 1 into operand 0. Both operands have
  1003. mode <var>m</var>, which is a scalar or vector floating-point mode.
  1004. </p>
  1005. <p>This pattern is not allowed to <code>FAIL</code>.
  1006. </p>
  1007. <a name="index-asinm2-instruction-pattern"></a>
  1008. </dd>
  1009. <dt>&lsquo;<samp>asin<var>m</var>2</samp>&rsquo;</dt>
  1010. <dd><p>Store the arc sine of operand 1 into operand 0. Both operands have
  1011. mode <var>m</var>, which is a scalar or vector floating-point mode.
  1012. </p>
  1013. <p>This pattern is not allowed to <code>FAIL</code>.
  1014. </p>
  1015. <a name="index-acosm2-instruction-pattern"></a>
  1016. </dd>
  1017. <dt>&lsquo;<samp>acos<var>m</var>2</samp>&rsquo;</dt>
  1018. <dd><p>Store the arc cosine of operand 1 into operand 0. Both operands have
  1019. mode <var>m</var>, which is a scalar or vector floating-point mode.
  1020. </p>
  1021. <p>This pattern is not allowed to <code>FAIL</code>.
  1022. </p>
  1023. <a name="index-atanm2-instruction-pattern"></a>
  1024. </dd>
  1025. <dt>&lsquo;<samp>atan<var>m</var>2</samp>&rsquo;</dt>
  1026. <dd><p>Store the arc tangent of operand 1 into operand 0. Both operands have
  1027. mode <var>m</var>, which is a scalar or vector floating-point mode.
  1028. </p>
  1029. <p>This pattern is not allowed to <code>FAIL</code>.
  1030. </p>
  1031. <a name="index-expm2-instruction-pattern"></a>
  1032. </dd>
  1033. <dt>&lsquo;<samp>exp<var>m</var>2</samp>&rsquo;</dt>
  1034. <dd><p>Raise e (the base of natural logarithms) to the power of operand 1
  1035. and store the result in operand 0. Both operands have mode <var>m</var>,
  1036. which is a scalar or vector floating-point mode.
  1037. </p>
  1038. <p>This pattern is not allowed to <code>FAIL</code>.
  1039. </p>
  1040. <a name="index-expm1m2-instruction-pattern"></a>
  1041. </dd>
  1042. <dt>&lsquo;<samp>expm1<var>m</var>2</samp>&rsquo;</dt>
  1043. <dd><p>Raise e (the base of natural logarithms) to the power of operand 1,
  1044. subtract 1, and store the result in operand 0. Both operands have
  1045. mode <var>m</var>, which is a scalar or vector floating-point mode.
  1046. </p>
  1047. <p>For inputs close to zero, the pattern is expected to be more
  1048. accurate than a separate <code>exp<var>m</var>2</code> and <code>sub<var>m</var>3</code>
  1049. would be.
  1050. </p>
  1051. <p>This pattern is not allowed to <code>FAIL</code>.
  1052. </p>
  1053. <a name="index-exp10m2-instruction-pattern"></a>
  1054. </dd>
  1055. <dt>&lsquo;<samp>exp10<var>m</var>2</samp>&rsquo;</dt>
  1056. <dd><p>Raise 10 to the power of operand 1 and store the result in operand 0.
  1057. Both operands have mode <var>m</var>, which is a scalar or vector
  1058. floating-point mode.
  1059. </p>
  1060. <p>This pattern is not allowed to <code>FAIL</code>.
  1061. </p>
  1062. <a name="index-exp2m2-instruction-pattern"></a>
  1063. </dd>
  1064. <dt>&lsquo;<samp>exp2<var>m</var>2</samp>&rsquo;</dt>
  1065. <dd><p>Raise 2 to the power of operand 1 and store the result in operand 0.
  1066. Both operands have mode <var>m</var>, which is a scalar or vector
  1067. floating-point mode.
  1068. </p>
  1069. <p>This pattern is not allowed to <code>FAIL</code>.
  1070. </p>
  1071. <a name="index-logm2-instruction-pattern"></a>
  1072. </dd>
  1073. <dt>&lsquo;<samp>log<var>m</var>2</samp>&rsquo;</dt>
  1074. <dd><p>Store the natural logarithm of operand 1 into operand 0. Both operands
  1075. have mode <var>m</var>, which is a scalar or vector floating-point mode.
  1076. </p>
  1077. <p>This pattern is not allowed to <code>FAIL</code>.
  1078. </p>
  1079. <a name="index-log1pm2-instruction-pattern"></a>
  1080. </dd>
  1081. <dt>&lsquo;<samp>log1p<var>m</var>2</samp>&rsquo;</dt>
  1082. <dd><p>Add 1 to operand 1, compute the natural logarithm, and store
  1083. the result in operand 0. Both operands have mode <var>m</var>, which is
  1084. a scalar or vector floating-point mode.
  1085. </p>
  1086. <p>For inputs close to zero, the pattern is expected to be more
  1087. accurate than a separate <code>add<var>m</var>3</code> and <code>log<var>m</var>2</code>
  1088. would be.
  1089. </p>
  1090. <p>This pattern is not allowed to <code>FAIL</code>.
  1091. </p>
  1092. <a name="index-log10m2-instruction-pattern"></a>
  1093. </dd>
  1094. <dt>&lsquo;<samp>log10<var>m</var>2</samp>&rsquo;</dt>
  1095. <dd><p>Store the base-10 logarithm of operand 1 into operand 0. Both operands
  1096. have mode <var>m</var>, which is a scalar or vector floating-point mode.
  1097. </p>
  1098. <p>This pattern is not allowed to <code>FAIL</code>.
  1099. </p>
  1100. <a name="index-log2m2-instruction-pattern"></a>
  1101. </dd>
  1102. <dt>&lsquo;<samp>log2<var>m</var>2</samp>&rsquo;</dt>
  1103. <dd><p>Store the base-2 logarithm of operand 1 into operand 0. Both operands
  1104. have mode <var>m</var>, which is a scalar or vector floating-point mode.
  1105. </p>
  1106. <p>This pattern is not allowed to <code>FAIL</code>.
  1107. </p>
  1108. <a name="index-logbm2-instruction-pattern"></a>
  1109. </dd>
  1110. <dt>&lsquo;<samp>logb<var>m</var>2</samp>&rsquo;</dt>
  1111. <dd><p>Store the base-<code>FLT_RADIX</code> logarithm of operand 1 into operand 0.
  1112. Both operands have mode <var>m</var>, which is a scalar or vector
  1113. floating-point mode.
  1114. </p>
  1115. <p>This pattern is not allowed to <code>FAIL</code>.
  1116. </p>
  1117. <a name="index-significandm2-instruction-pattern"></a>
  1118. </dd>
  1119. <dt>&lsquo;<samp>significand<var>m</var>2</samp>&rsquo;</dt>
  1120. <dd><p>Store the significand of floating-point operand 1 in operand 0.
  1121. Both operands have mode <var>m</var>, which is a scalar or vector
  1122. floating-point mode.
  1123. </p>
  1124. <p>This pattern is not allowed to <code>FAIL</code>.
  1125. </p>
  1126. <a name="index-powm3-instruction-pattern"></a>
  1127. </dd>
  1128. <dt>&lsquo;<samp>pow<var>m</var>3</samp>&rsquo;</dt>
  1129. <dd><p>Store the value of operand 1 raised to the exponent operand 2
  1130. into operand 0. All operands have mode <var>m</var>, which is a scalar
  1131. or vector floating-point mode.
  1132. </p>
  1133. <p>This pattern is not allowed to <code>FAIL</code>.
  1134. </p>
  1135. <a name="index-atan2m3-instruction-pattern"></a>
  1136. </dd>
  1137. <dt>&lsquo;<samp>atan2<var>m</var>3</samp>&rsquo;</dt>
  1138. <dd><p>Store the arc tangent (inverse tangent) of operand 1 divided by
  1139. operand 2 into operand 0, using the signs of both arguments to
  1140. determine the quadrant of the result. All operands have mode
  1141. <var>m</var>, which is a scalar or vector floating-point mode.
  1142. </p>
  1143. <p>This pattern is not allowed to <code>FAIL</code>.
  1144. </p>
  1145. <a name="index-floorm2-instruction-pattern"></a>
  1146. </dd>
  1147. <dt>&lsquo;<samp>floor<var>m</var>2</samp>&rsquo;</dt>
  1148. <dd><p>Store the largest integral value not greater than operand 1 in operand 0.
  1149. Both operands have mode <var>m</var>, which is a scalar or vector
  1150. floating-point mode. If <samp>-ffp-int-builtin-inexact</samp> is in
  1151. effect, the &ldquo;inexact&rdquo; exception may be raised for noninteger
  1152. operands; otherwise, it may not.
  1153. </p>
  1154. <p>This pattern is not allowed to <code>FAIL</code>.
  1155. </p>
  1156. <a name="index-btruncm2-instruction-pattern"></a>
  1157. </dd>
  1158. <dt>&lsquo;<samp>btrunc<var>m</var>2</samp>&rsquo;</dt>
  1159. <dd><p>Round operand 1 to an integer, towards zero, and store the result in
  1160. operand 0. Both operands have mode <var>m</var>, which is a scalar or
  1161. vector floating-point mode. If <samp>-ffp-int-builtin-inexact</samp> is
  1162. in effect, the &ldquo;inexact&rdquo; exception may be raised for noninteger
  1163. operands; otherwise, it may not.
  1164. </p>
  1165. <p>This pattern is not allowed to <code>FAIL</code>.
  1166. </p>
  1167. <a name="index-roundm2-instruction-pattern"></a>
  1168. </dd>
  1169. <dt>&lsquo;<samp>round<var>m</var>2</samp>&rsquo;</dt>
  1170. <dd><p>Round operand 1 to the nearest integer, rounding away from zero in the
  1171. event of a tie, and store the result in operand 0. Both operands have
  1172. mode <var>m</var>, which is a scalar or vector floating-point mode. If
  1173. <samp>-ffp-int-builtin-inexact</samp> is in effect, the &ldquo;inexact&rdquo;
  1174. exception may be raised for noninteger operands; otherwise, it may
  1175. not.
  1176. </p>
  1177. <p>This pattern is not allowed to <code>FAIL</code>.
  1178. </p>
  1179. <a name="index-ceilm2-instruction-pattern"></a>
  1180. </dd>
  1181. <dt>&lsquo;<samp>ceil<var>m</var>2</samp>&rsquo;</dt>
  1182. <dd><p>Store the smallest integral value not less than operand 1 in operand 0.
  1183. Both operands have mode <var>m</var>, which is a scalar or vector
  1184. floating-point mode. If <samp>-ffp-int-builtin-inexact</samp> is in
  1185. effect, the &ldquo;inexact&rdquo; exception may be raised for noninteger
  1186. operands; otherwise, it may not.
  1187. </p>
  1188. <p>This pattern is not allowed to <code>FAIL</code>.
  1189. </p>
  1190. <a name="index-nearbyintm2-instruction-pattern"></a>
  1191. </dd>
  1192. <dt>&lsquo;<samp>nearbyint<var>m</var>2</samp>&rsquo;</dt>
  1193. <dd><p>Round operand 1 to an integer, using the current rounding mode, and
  1194. store the result in operand 0. Do not raise an inexact condition when
  1195. the result is different from the argument. Both operands have mode
  1196. <var>m</var>, which is a scalar or vector floating-point mode.
  1197. </p>
  1198. <p>This pattern is not allowed to <code>FAIL</code>.
  1199. </p>
  1200. <a name="index-rintm2-instruction-pattern"></a>
  1201. </dd>
  1202. <dt>&lsquo;<samp>rint<var>m</var>2</samp>&rsquo;</dt>
  1203. <dd><p>Round operand 1 to an integer, using the current rounding mode, and
  1204. store the result in operand 0. Raise an inexact condition when
  1205. the result is different from the argument. Both operands have mode
  1206. <var>m</var>, which is a scalar or vector floating-point mode.
  1207. </p>
  1208. <p>This pattern is not allowed to <code>FAIL</code>.
  1209. </p>
  1210. <a name="index-lrintmn2"></a>
  1211. </dd>
  1212. <dt>&lsquo;<samp>lrint<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1213. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1214. point mode <var>n</var> as a signed number according to the current
  1215. rounding mode and store in operand 0 (which has mode <var>n</var>).
  1216. </p>
  1217. <a name="index-lroundmn2"></a>
  1218. </dd>
  1219. <dt>&lsquo;<samp>lround<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1220. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1221. point mode <var>n</var> as a signed number rounding to nearest and away
  1222. from zero and store in operand 0 (which has mode <var>n</var>).
  1223. </p>
  1224. <a name="index-lfloormn2"></a>
  1225. </dd>
  1226. <dt>&lsquo;<samp>lfloor<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1227. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1228. point mode <var>n</var> as a signed number rounding down and store in
  1229. operand 0 (which has mode <var>n</var>).
  1230. </p>
  1231. <a name="index-lceilmn2"></a>
  1232. </dd>
  1233. <dt>&lsquo;<samp>lceil<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1234. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1235. point mode <var>n</var> as a signed number rounding up and store in
  1236. operand 0 (which has mode <var>n</var>).
  1237. </p>
  1238. <a name="index-copysignm3-instruction-pattern"></a>
  1239. </dd>
  1240. <dt>&lsquo;<samp>copysign<var>m</var>3</samp>&rsquo;</dt>
  1241. <dd><p>Store a value with the magnitude of operand 1 and the sign of operand
  1242. 2 into operand 0. All operands have mode <var>m</var>, which is a scalar or
  1243. vector floating-point mode.
  1244. </p>
  1245. <p>This pattern is not allowed to <code>FAIL</code>.
  1246. </p>
  1247. <a name="index-ffsm2-instruction-pattern"></a>
  1248. </dd>
  1249. <dt>&lsquo;<samp>ffs<var>m</var>2</samp>&rsquo;</dt>
  1250. <dd><p>Store into operand 0 one plus the index of the least significant 1-bit
  1251. of operand 1. If operand 1 is zero, store zero.
  1252. </p>
  1253. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1254. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1255. integer mode is suitable for the target. The compiler will insert
  1256. conversion instructions as necessary (typically to convert the result
  1257. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1258. operands must have mode <var>m</var>.
  1259. </p>
  1260. <p>This pattern is not allowed to <code>FAIL</code>.
  1261. </p>
  1262. <a name="index-clrsbm2-instruction-pattern"></a>
  1263. </dd>
  1264. <dt>&lsquo;<samp>clrsb<var>m</var>2</samp>&rsquo;</dt>
  1265. <dd><p>Count leading redundant sign bits.
  1266. Store into operand 0 the number of redundant sign bits in operand 1, starting
  1267. at the most significant bit position.
  1268. A redundant sign bit is defined as any sign bit after the first. As such,
  1269. this count will be one less than the count of leading sign bits.
  1270. </p>
  1271. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1272. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1273. integer mode is suitable for the target. The compiler will insert
  1274. conversion instructions as necessary (typically to convert the result
  1275. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1276. operands must have mode <var>m</var>.
  1277. </p>
  1278. <p>This pattern is not allowed to <code>FAIL</code>.
  1279. </p>
  1280. <a name="index-clzm2-instruction-pattern"></a>
  1281. </dd>
  1282. <dt>&lsquo;<samp>clz<var>m</var>2</samp>&rsquo;</dt>
  1283. <dd><p>Store into operand 0 the number of leading 0-bits in operand 1, starting
  1284. at the most significant bit position. If operand 1 is 0, the
  1285. <code>CLZ_DEFINED_VALUE_AT_ZERO</code> (see <a href="Misc.html#Misc">Misc</a>) macro defines if
  1286. the result is undefined or has a useful value.
  1287. </p>
  1288. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1289. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1290. integer mode is suitable for the target. The compiler will insert
  1291. conversion instructions as necessary (typically to convert the result
  1292. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1293. operands must have mode <var>m</var>.
  1294. </p>
  1295. <p>This pattern is not allowed to <code>FAIL</code>.
  1296. </p>
  1297. <a name="index-ctzm2-instruction-pattern"></a>
  1298. </dd>
  1299. <dt>&lsquo;<samp>ctz<var>m</var>2</samp>&rsquo;</dt>
  1300. <dd><p>Store into operand 0 the number of trailing 0-bits in operand 1, starting
  1301. at the least significant bit position. If operand 1 is 0, the
  1302. <code>CTZ_DEFINED_VALUE_AT_ZERO</code> (see <a href="Misc.html#Misc">Misc</a>) macro defines if
  1303. the result is undefined or has a useful value.
  1304. </p>
  1305. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1306. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1307. integer mode is suitable for the target. The compiler will insert
  1308. conversion instructions as necessary (typically to convert the result
  1309. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1310. operands must have mode <var>m</var>.
  1311. </p>
  1312. <p>This pattern is not allowed to <code>FAIL</code>.
  1313. </p>
  1314. <a name="index-popcountm2-instruction-pattern"></a>
  1315. </dd>
  1316. <dt>&lsquo;<samp>popcount<var>m</var>2</samp>&rsquo;</dt>
  1317. <dd><p>Store into operand 0 the number of 1-bits in operand 1.
  1318. </p>
  1319. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1320. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1321. integer mode is suitable for the target. The compiler will insert
  1322. conversion instructions as necessary (typically to convert the result
  1323. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1324. operands must have mode <var>m</var>.
  1325. </p>
  1326. <p>This pattern is not allowed to <code>FAIL</code>.
  1327. </p>
  1328. <a name="index-paritym2-instruction-pattern"></a>
  1329. </dd>
  1330. <dt>&lsquo;<samp>parity<var>m</var>2</samp>&rsquo;</dt>
  1331. <dd><p>Store into operand 0 the parity of operand 1, i.e. the number of 1-bits
  1332. in operand 1 modulo 2.
  1333. </p>
  1334. <p><var>m</var> is either a scalar or vector integer mode. When it is a scalar,
  1335. operand 1 has mode <var>m</var> but operand 0 can have whatever scalar
  1336. integer mode is suitable for the target. The compiler will insert
  1337. conversion instructions as necessary (typically to convert the result
  1338. to the same width as <code>int</code>). When <var>m</var> is a vector, both
  1339. operands must have mode <var>m</var>.
  1340. </p>
  1341. <p>This pattern is not allowed to <code>FAIL</code>.
  1342. </p>
  1343. <a name="index-one_005fcmplm2-instruction-pattern"></a>
  1344. </dd>
  1345. <dt>&lsquo;<samp>one_cmpl<var>m</var>2</samp>&rsquo;</dt>
  1346. <dd><p>Store the bitwise-complement of operand 1 into operand 0.
  1347. </p>
  1348. <a name="index-movmemm-instruction-pattern"></a>
  1349. </dd>
  1350. <dt>&lsquo;<samp>movmem<var>m</var></samp>&rsquo;</dt>
  1351. <dd><p>Block move instruction. The destination and source blocks of memory
  1352. are the first two operands, and both are <code>mem:BLK</code>s with an
  1353. address in mode <code>Pmode</code>.
  1354. </p>
  1355. <p>The number of bytes to move is the third operand, in mode <var>m</var>.
  1356. Usually, you specify <code>Pmode</code> for <var>m</var>. However, if you can
  1357. generate better code knowing the range of valid lengths is smaller than
  1358. those representable in a full Pmode pointer, you should provide
  1359. a pattern with a
  1360. mode corresponding to the range of values you can handle efficiently
  1361. (e.g., <code>QImode</code> for values in the range 0&ndash;127; note we avoid numbers
  1362. that appear negative) and also a pattern with <code>Pmode</code>.
  1363. </p>
  1364. <p>The fourth operand is the known shared alignment of the source and
  1365. destination, in the form of a <code>const_int</code> rtx. Thus, if the
  1366. compiler knows that both source and destination are word-aligned,
  1367. it may provide the value 4 for this operand.
  1368. </p>
  1369. <p>Optional operands 5 and 6 specify expected alignment and size of block
  1370. respectively. The expected alignment differs from alignment in operand 4
  1371. in a way that the blocks are not required to be aligned according to it in
  1372. all cases. This expected alignment is also in bytes, just like operand 4.
  1373. Expected size, when unknown, is set to <code>(const_int -1)</code>.
  1374. </p>
  1375. <p>Descriptions of multiple <code>movmem<var>m</var></code> patterns can only be
  1376. beneficial if the patterns for smaller modes have fewer restrictions
  1377. on their first, second and fourth operands. Note that the mode <var>m</var>
  1378. in <code>movmem<var>m</var></code> does not impose any restriction on the mode of
  1379. individually moved data units in the block.
  1380. </p>
  1381. <p>These patterns need not give special consideration to the possibility
  1382. that the source and destination strings might overlap.
  1383. </p>
  1384. <a name="index-movstr-instruction-pattern"></a>
  1385. </dd>
  1386. <dt>&lsquo;<samp>movstr</samp>&rsquo;</dt>
  1387. <dd><p>String copy instruction, with <code>stpcpy</code> semantics. Operand 0 is
  1388. an output operand in mode <code>Pmode</code>. The addresses of the
  1389. destination and source strings are operands 1 and 2, and both are
  1390. <code>mem:BLK</code>s with addresses in mode <code>Pmode</code>. The execution of
  1391. the expansion of this pattern should store in operand 0 the address in
  1392. which the <code>NUL</code> terminator was stored in the destination string.
  1393. </p>
  1394. <p>This patern has also several optional operands that are same as in
  1395. <code>setmem</code>.
  1396. </p>
  1397. <a name="index-setmemm-instruction-pattern"></a>
  1398. </dd>
  1399. <dt>&lsquo;<samp>setmem<var>m</var></samp>&rsquo;</dt>
  1400. <dd><p>Block set instruction. The destination string is the first operand,
  1401. given as a <code>mem:BLK</code> whose address is in mode <code>Pmode</code>. The
  1402. number of bytes to set is the second operand, in mode <var>m</var>. The value to
  1403. initialize the memory with is the third operand. Targets that only support the
  1404. clearing of memory should reject any value that is not the constant 0. See
  1405. &lsquo;<samp>movmem<var>m</var></samp>&rsquo; for a discussion of the choice of mode.
  1406. </p>
  1407. <p>The fourth operand is the known alignment of the destination, in the form
  1408. of a <code>const_int</code> rtx. Thus, if the compiler knows that the
  1409. destination is word-aligned, it may provide the value 4 for this
  1410. operand.
  1411. </p>
  1412. <p>Optional operands 5 and 6 specify expected alignment and size of block
  1413. respectively. The expected alignment differs from alignment in operand 4
  1414. in a way that the blocks are not required to be aligned according to it in
  1415. all cases. This expected alignment is also in bytes, just like operand 4.
  1416. Expected size, when unknown, is set to <code>(const_int -1)</code>.
  1417. Operand 7 is the minimal size of the block and operand 8 is the
  1418. maximal size of the block (NULL if it can not be represented as CONST_INT).
  1419. Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
  1420. but it can be used for choosing proper code sequence for a given size).
  1421. </p>
  1422. <p>The use for multiple <code>setmem<var>m</var></code> is as for <code>movmem<var>m</var></code>.
  1423. </p>
  1424. <a name="index-cmpstrnm-instruction-pattern"></a>
  1425. </dd>
  1426. <dt>&lsquo;<samp>cmpstrn<var>m</var></samp>&rsquo;</dt>
  1427. <dd><p>String compare instruction, with five operands. Operand 0 is the output;
  1428. it has mode <var>m</var>. The remaining four operands are like the operands
  1429. of &lsquo;<samp>movmem<var>m</var></samp>&rsquo;. The two memory blocks specified are compared
  1430. byte by byte in lexicographic order starting at the beginning of each
  1431. string. The instruction is not allowed to prefetch more than one byte
  1432. at a time since either string may end in the first byte and reading past
  1433. that may access an invalid page or segment and cause a fault. The
  1434. comparison terminates early if the fetched bytes are different or if
  1435. they are equal to zero. The effect of the instruction is to store a
  1436. value in operand 0 whose sign indicates the result of the comparison.
  1437. </p>
  1438. <a name="index-cmpstrm-instruction-pattern"></a>
  1439. </dd>
  1440. <dt>&lsquo;<samp>cmpstr<var>m</var></samp>&rsquo;</dt>
  1441. <dd><p>String compare instruction, without known maximum length. Operand 0 is the
  1442. output; it has mode <var>m</var>. The second and third operand are the blocks of
  1443. memory to be compared; both are <code>mem:BLK</code> with an address in mode
  1444. <code>Pmode</code>.
  1445. </p>
  1446. <p>The fourth operand is the known shared alignment of the source and
  1447. destination, in the form of a <code>const_int</code> rtx. Thus, if the
  1448. compiler knows that both source and destination are word-aligned,
  1449. it may provide the value 4 for this operand.
  1450. </p>
  1451. <p>The two memory blocks specified are compared byte by byte in lexicographic
  1452. order starting at the beginning of each string. The instruction is not allowed
  1453. to prefetch more than one byte at a time since either string may end in the
  1454. first byte and reading past that may access an invalid page or segment and
  1455. cause a fault. The comparison will terminate when the fetched bytes
  1456. are different or if they are equal to zero. The effect of the
  1457. instruction is to store a value in operand 0 whose sign indicates the
  1458. result of the comparison.
  1459. </p>
  1460. <a name="index-cmpmemm-instruction-pattern"></a>
  1461. </dd>
  1462. <dt>&lsquo;<samp>cmpmem<var>m</var></samp>&rsquo;</dt>
  1463. <dd><p>Block compare instruction, with five operands like the operands
  1464. of &lsquo;<samp>cmpstr<var>m</var></samp>&rsquo;. The two memory blocks specified are compared
  1465. byte by byte in lexicographic order starting at the beginning of each
  1466. block. Unlike &lsquo;<samp>cmpstr<var>m</var></samp>&rsquo; the instruction can prefetch
  1467. any bytes in the two memory blocks. Also unlike &lsquo;<samp>cmpstr<var>m</var></samp>&rsquo;
  1468. the comparison will not stop if both bytes are zero. The effect of
  1469. the instruction is to store a value in operand 0 whose sign indicates
  1470. the result of the comparison.
  1471. </p>
  1472. <a name="index-strlenm-instruction-pattern"></a>
  1473. </dd>
  1474. <dt>&lsquo;<samp>strlen<var>m</var></samp>&rsquo;</dt>
  1475. <dd><p>Compute the length of a string, with three operands.
  1476. Operand 0 is the result (of mode <var>m</var>), operand 1 is
  1477. a <code>mem</code> referring to the first character of the string,
  1478. operand 2 is the character to search for (normally zero),
  1479. and operand 3 is a constant describing the known alignment
  1480. of the beginning of the string.
  1481. </p>
  1482. <a name="index-floatmn2-instruction-pattern"></a>
  1483. </dd>
  1484. <dt>&lsquo;<samp>float<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1485. <dd><p>Convert signed integer operand 1 (valid for fixed point mode <var>m</var>) to
  1486. floating point mode <var>n</var> and store in operand 0 (which has mode
  1487. <var>n</var>).
  1488. </p>
  1489. <a name="index-floatunsmn2-instruction-pattern"></a>
  1490. </dd>
  1491. <dt>&lsquo;<samp>floatuns<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1492. <dd><p>Convert unsigned integer operand 1 (valid for fixed point mode <var>m</var>)
  1493. to floating point mode <var>n</var> and store in operand 0 (which has mode
  1494. <var>n</var>).
  1495. </p>
  1496. <a name="index-fixmn2-instruction-pattern"></a>
  1497. </dd>
  1498. <dt>&lsquo;<samp>fix<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1499. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1500. point mode <var>n</var> as a signed number and store in operand 0 (which
  1501. has mode <var>n</var>). This instruction&rsquo;s result is defined only when
  1502. the value of operand 1 is an integer.
  1503. </p>
  1504. <p>If the machine description defines this pattern, it also needs to
  1505. define the <code>ftrunc</code> pattern.
  1506. </p>
  1507. <a name="index-fixunsmn2-instruction-pattern"></a>
  1508. </dd>
  1509. <dt>&lsquo;<samp>fixuns<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1510. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to fixed
  1511. point mode <var>n</var> as an unsigned number and store in operand 0 (which
  1512. has mode <var>n</var>). This instruction&rsquo;s result is defined only when the
  1513. value of operand 1 is an integer.
  1514. </p>
  1515. <a name="index-ftruncm2-instruction-pattern"></a>
  1516. </dd>
  1517. <dt>&lsquo;<samp>ftrunc<var>m</var>2</samp>&rsquo;</dt>
  1518. <dd><p>Convert operand 1 (valid for floating point mode <var>m</var>) to an
  1519. integer value, still represented in floating point mode <var>m</var>, and
  1520. store it in operand 0 (valid for floating point mode <var>m</var>).
  1521. </p>
  1522. <a name="index-fix_005ftruncmn2-instruction-pattern"></a>
  1523. </dd>
  1524. <dt>&lsquo;<samp>fix_trunc<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1525. <dd><p>Like &lsquo;<samp>fix<var>m</var><var>n</var>2</samp>&rsquo; but works for any floating point value
  1526. of mode <var>m</var> by converting the value to an integer.
  1527. </p>
  1528. <a name="index-fixuns_005ftruncmn2-instruction-pattern"></a>
  1529. </dd>
  1530. <dt>&lsquo;<samp>fixuns_trunc<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1531. <dd><p>Like &lsquo;<samp>fixuns<var>m</var><var>n</var>2</samp>&rsquo; but works for any floating point
  1532. value of mode <var>m</var> by converting the value to an integer.
  1533. </p>
  1534. <a name="index-truncmn2-instruction-pattern"></a>
  1535. </dd>
  1536. <dt>&lsquo;<samp>trunc<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1537. <dd><p>Truncate operand 1 (valid for mode <var>m</var>) to mode <var>n</var> and
  1538. store in operand 0 (which has mode <var>n</var>). Both modes must be fixed
  1539. point or both floating point.
  1540. </p>
  1541. <a name="index-extendmn2-instruction-pattern"></a>
  1542. </dd>
  1543. <dt>&lsquo;<samp>extend<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1544. <dd><p>Sign-extend operand 1 (valid for mode <var>m</var>) to mode <var>n</var> and
  1545. store in operand 0 (which has mode <var>n</var>). Both modes must be fixed
  1546. point or both floating point.
  1547. </p>
  1548. <a name="index-zero_005fextendmn2-instruction-pattern"></a>
  1549. </dd>
  1550. <dt>&lsquo;<samp>zero_extend<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1551. <dd><p>Zero-extend operand 1 (valid for mode <var>m</var>) to mode <var>n</var> and
  1552. store in operand 0 (which has mode <var>n</var>). Both modes must be fixed
  1553. point.
  1554. </p>
  1555. <a name="index-fractmn2-instruction-pattern"></a>
  1556. </dd>
  1557. <dt>&lsquo;<samp>fract<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1558. <dd><p>Convert operand 1 of mode <var>m</var> to mode <var>n</var> and store in
  1559. operand 0 (which has mode <var>n</var>). Mode <var>m</var> and mode <var>n</var>
  1560. could be fixed-point to fixed-point, signed integer to fixed-point,
  1561. fixed-point to signed integer, floating-point to fixed-point,
  1562. or fixed-point to floating-point.
  1563. When overflows or underflows happen, the results are undefined.
  1564. </p>
  1565. <a name="index-satfractmn2-instruction-pattern"></a>
  1566. </dd>
  1567. <dt>&lsquo;<samp>satfract<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1568. <dd><p>Convert operand 1 of mode <var>m</var> to mode <var>n</var> and store in
  1569. operand 0 (which has mode <var>n</var>). Mode <var>m</var> and mode <var>n</var>
  1570. could be fixed-point to fixed-point, signed integer to fixed-point,
  1571. or floating-point to fixed-point.
  1572. When overflows or underflows happen, the instruction saturates the
  1573. results to the maximum or the minimum.
  1574. </p>
  1575. <a name="index-fractunsmn2-instruction-pattern"></a>
  1576. </dd>
  1577. <dt>&lsquo;<samp>fractuns<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1578. <dd><p>Convert operand 1 of mode <var>m</var> to mode <var>n</var> and store in
  1579. operand 0 (which has mode <var>n</var>). Mode <var>m</var> and mode <var>n</var>
  1580. could be unsigned integer to fixed-point, or
  1581. fixed-point to unsigned integer.
  1582. When overflows or underflows happen, the results are undefined.
  1583. </p>
  1584. <a name="index-satfractunsmn2-instruction-pattern"></a>
  1585. </dd>
  1586. <dt>&lsquo;<samp>satfractuns<var>m</var><var>n</var>2</samp>&rsquo;</dt>
  1587. <dd><p>Convert unsigned integer operand 1 of mode <var>m</var> to fixed-point mode
  1588. <var>n</var> and store in operand 0 (which has mode <var>n</var>).
  1589. When overflows or underflows happen, the instruction saturates the
  1590. results to the maximum or the minimum.
  1591. </p>
  1592. <a name="index-extvm-instruction-pattern"></a>
  1593. </dd>
  1594. <dt>&lsquo;<samp>extv<var>m</var></samp>&rsquo;</dt>
  1595. <dd><p>Extract a bit-field from register operand 1, sign-extend it, and store
  1596. it in operand 0. Operand 2 specifies the width of the field in bits
  1597. and operand 3 the starting bit, which counts from the most significant
  1598. bit if &lsquo;<samp>BITS_BIG_ENDIAN</samp>&rsquo; is true and from the least significant bit
  1599. otherwise.
  1600. </p>
  1601. <p>Operands 0 and 1 both have mode <var>m</var>. Operands 2 and 3 have a
  1602. target-specific mode.
  1603. </p>
  1604. <a name="index-extvmisalignm-instruction-pattern"></a>
  1605. </dd>
  1606. <dt>&lsquo;<samp>extvmisalign<var>m</var></samp>&rsquo;</dt>
  1607. <dd><p>Extract a bit-field from memory operand 1, sign extend it, and store
  1608. it in operand 0. Operand 2 specifies the width in bits and operand 3
  1609. the starting bit. The starting bit is always somewhere in the first byte of
  1610. operand 1; it counts from the most significant bit if &lsquo;<samp>BITS_BIG_ENDIAN</samp>&rsquo;
  1611. is true and from the least significant bit otherwise.
  1612. </p>
  1613. <p>Operand 0 has mode <var>m</var> while operand 1 has <code>BLK</code> mode.
  1614. Operands 2 and 3 have a target-specific mode.
  1615. </p>
  1616. <p>The instruction must not read beyond the last byte of the bit-field.
  1617. </p>
  1618. <a name="index-extzvm-instruction-pattern"></a>
  1619. </dd>
  1620. <dt>&lsquo;<samp>extzv<var>m</var></samp>&rsquo;</dt>
  1621. <dd><p>Like &lsquo;<samp>extv<var>m</var></samp>&rsquo; except that the bit-field value is zero-extended.
  1622. </p>
  1623. <a name="index-extzvmisalignm-instruction-pattern"></a>
  1624. </dd>
  1625. <dt>&lsquo;<samp>extzvmisalign<var>m</var></samp>&rsquo;</dt>
  1626. <dd><p>Like &lsquo;<samp>extvmisalign<var>m</var></samp>&rsquo; except that the bit-field value is
  1627. zero-extended.
  1628. </p>
  1629. <a name="index-insvm-instruction-pattern"></a>
  1630. </dd>
  1631. <dt>&lsquo;<samp>insv<var>m</var></samp>&rsquo;</dt>
  1632. <dd><p>Insert operand 3 into a bit-field of register operand 0. Operand 1
  1633. specifies the width of the field in bits and operand 2 the starting bit,
  1634. which counts from the most significant bit if &lsquo;<samp>BITS_BIG_ENDIAN</samp>&rsquo;
  1635. is true and from the least significant bit otherwise.
  1636. </p>
  1637. <p>Operands 0 and 3 both have mode <var>m</var>. Operands 1 and 2 have a
  1638. target-specific mode.
  1639. </p>
  1640. <a name="index-insvmisalignm-instruction-pattern"></a>
  1641. </dd>
  1642. <dt>&lsquo;<samp>insvmisalign<var>m</var></samp>&rsquo;</dt>
  1643. <dd><p>Insert operand 3 into a bit-field of memory operand 0. Operand 1
  1644. specifies the width of the field in bits and operand 2 the starting bit.
  1645. The starting bit is always somewhere in the first byte of operand 0;
  1646. it counts from the most significant bit if &lsquo;<samp>BITS_BIG_ENDIAN</samp>&rsquo;
  1647. is true and from the least significant bit otherwise.
  1648. </p>
  1649. <p>Operand 3 has mode <var>m</var> while operand 0 has <code>BLK</code> mode.
  1650. Operands 1 and 2 have a target-specific mode.
  1651. </p>
  1652. <p>The instruction must not read or write beyond the last byte of the bit-field.
  1653. </p>
  1654. <a name="index-extv-instruction-pattern"></a>
  1655. </dd>
  1656. <dt>&lsquo;<samp>extv</samp>&rsquo;</dt>
  1657. <dd><p>Extract a bit-field from operand 1 (a register or memory operand), where
  1658. operand 2 specifies the width in bits and operand 3 the starting bit,
  1659. and store it in operand 0. Operand 0 must have mode <code>word_mode</code>.
  1660. Operand 1 may have mode <code>byte_mode</code> or <code>word_mode</code>; often
  1661. <code>word_mode</code> is allowed only for registers. Operands 2 and 3 must
  1662. be valid for <code>word_mode</code>.
  1663. </p>
  1664. <p>The RTL generation pass generates this instruction only with constants
  1665. for operands 2 and 3 and the constant is never zero for operand 2.
  1666. </p>
  1667. <p>The bit-field value is sign-extended to a full word integer
  1668. before it is stored in operand 0.
  1669. </p>
  1670. <p>This pattern is deprecated; please use &lsquo;<samp>extv<var>m</var></samp>&rsquo; and
  1671. <code>extvmisalign<var>m</var></code> instead.
  1672. </p>
  1673. <a name="index-extzv-instruction-pattern"></a>
  1674. </dd>
  1675. <dt>&lsquo;<samp>extzv</samp>&rsquo;</dt>
  1676. <dd><p>Like &lsquo;<samp>extv</samp>&rsquo; except that the bit-field value is zero-extended.
  1677. </p>
  1678. <p>This pattern is deprecated; please use &lsquo;<samp>extzv<var>m</var></samp>&rsquo; and
  1679. <code>extzvmisalign<var>m</var></code> instead.
  1680. </p>
  1681. <a name="index-insv-instruction-pattern"></a>
  1682. </dd>
  1683. <dt>&lsquo;<samp>insv</samp>&rsquo;</dt>
  1684. <dd><p>Store operand 3 (which must be valid for <code>word_mode</code>) into a
  1685. bit-field in operand 0, where operand 1 specifies the width in bits and
  1686. operand 2 the starting bit. Operand 0 may have mode <code>byte_mode</code> or
  1687. <code>word_mode</code>; often <code>word_mode</code> is allowed only for registers.
  1688. Operands 1 and 2 must be valid for <code>word_mode</code>.
  1689. </p>
  1690. <p>The RTL generation pass generates this instruction only with constants
  1691. for operands 1 and 2 and the constant is never zero for operand 1.
  1692. </p>
  1693. <p>This pattern is deprecated; please use &lsquo;<samp>insv<var>m</var></samp>&rsquo; and
  1694. <code>insvmisalign<var>m</var></code> instead.
  1695. </p>
  1696. <a name="index-movmodecc-instruction-pattern"></a>
  1697. </dd>
  1698. <dt>&lsquo;<samp>mov<var>mode</var>cc</samp>&rsquo;</dt>
  1699. <dd><p>Conditionally move operand 2 or operand 3 into operand 0 according to the
  1700. comparison in operand 1. If the comparison is true, operand 2 is moved
  1701. into operand 0, otherwise operand 3 is moved.
  1702. </p>
  1703. <p>The mode of the operands being compared need not be the same as the operands
  1704. being moved. Some machines, sparc64 for example, have instructions that
  1705. conditionally move an integer value based on the floating point condition
  1706. codes and vice versa.
  1707. </p>
  1708. <p>If the machine does not have conditional move instructions, do not
  1709. define these patterns.
  1710. </p>
  1711. <a name="index-addmodecc-instruction-pattern"></a>
  1712. </dd>
  1713. <dt>&lsquo;<samp>add<var>mode</var>cc</samp>&rsquo;</dt>
  1714. <dd><p>Similar to &lsquo;<samp>mov<var>mode</var>cc</samp>&rsquo; but for conditional addition. Conditionally
  1715. move operand 2 or (operands 2 + operand 3) into operand 0 according to the
  1716. comparison in operand 1. If the comparison is false, operand 2 is moved into
  1717. operand 0, otherwise (operand 2 + operand 3) is moved.
  1718. </p>
  1719. <a name="index-negmodecc-instruction-pattern"></a>
  1720. </dd>
  1721. <dt>&lsquo;<samp>neg<var>mode</var>cc</samp>&rsquo;</dt>
  1722. <dd><p>Similar to &lsquo;<samp>mov<var>mode</var>cc</samp>&rsquo; but for conditional negation. Conditionally
  1723. move the negation of operand 2 or the unchanged operand 3 into operand 0
  1724. according to the comparison in operand 1. If the comparison is true, the negation
  1725. of operand 2 is moved into operand 0, otherwise operand 3 is moved.
  1726. </p>
  1727. <a name="index-notmodecc-instruction-pattern"></a>
  1728. </dd>
  1729. <dt>&lsquo;<samp>not<var>mode</var>cc</samp>&rsquo;</dt>
  1730. <dd><p>Similar to &lsquo;<samp>neg<var>mode</var>cc</samp>&rsquo; but for conditional complement.
  1731. Conditionally move the bitwise complement of operand 2 or the unchanged
  1732. operand 3 into operand 0 according to the comparison in operand 1.
  1733. If the comparison is true, the complement of operand 2 is moved into
  1734. operand 0, otherwise operand 3 is moved.
  1735. </p>
  1736. <a name="index-cstoremode4-instruction-pattern"></a>
  1737. </dd>
  1738. <dt>&lsquo;<samp>cstore<var>mode</var>4</samp>&rsquo;</dt>
  1739. <dd><p>Store zero or nonzero in operand 0 according to whether a comparison
  1740. is true. Operand 1 is a comparison operator. Operand 2 and operand 3
  1741. are the first and second operand of the comparison, respectively.
  1742. You specify the mode that operand 0 must have when you write the
  1743. <code>match_operand</code> expression. The compiler automatically sees which
  1744. mode you have used and supplies an operand of that mode.
  1745. </p>
  1746. <p>The value stored for a true condition must have 1 as its low bit, or
  1747. else must be negative. Otherwise the instruction is not suitable and
  1748. you should omit it from the machine description. You describe to the
  1749. compiler exactly which value is stored by defining the macro
  1750. <code>STORE_FLAG_VALUE</code> (see <a href="Misc.html#Misc">Misc</a>). If a description cannot be
  1751. found that can be used for all the possible comparison operators, you
  1752. should pick one and use a <code>define_expand</code> to map all results
  1753. onto the one you chose.
  1754. </p>
  1755. <p>These operations may <code>FAIL</code>, but should do so only in relatively
  1756. uncommon cases; if they would <code>FAIL</code> for common cases involving
  1757. integer comparisons, it is best to restrict the predicates to not
  1758. allow these operands. Likewise if a given comparison operator will
  1759. always fail, independent of the operands (for floating-point modes, the
  1760. <code>ordered_comparison_operator</code> predicate is often useful in this case).
  1761. </p>
  1762. <p>If this pattern is omitted, the compiler will generate a conditional
  1763. branch&mdash;for example, it may copy a constant one to the target and branching
  1764. around an assignment of zero to the target&mdash;or a libcall. If the predicate
  1765. for operand 1 only rejects some operators, it will also try reordering the
  1766. operands and/or inverting the result value (e.g. by an exclusive OR).
  1767. These possibilities could be cheaper or equivalent to the instructions
  1768. used for the &lsquo;<samp>cstore<var>mode</var>4</samp>&rsquo; pattern followed by those required
  1769. to convert a positive result from <code>STORE_FLAG_VALUE</code> to 1; in this
  1770. case, you can and should make operand 1&rsquo;s predicate reject some operators
  1771. in the &lsquo;<samp>cstore<var>mode</var>4</samp>&rsquo; pattern, or remove the pattern altogether
  1772. from the machine description.
  1773. </p>
  1774. <a name="index-cbranchmode4-instruction-pattern"></a>
  1775. </dd>
  1776. <dt>&lsquo;<samp>cbranch<var>mode</var>4</samp>&rsquo;</dt>
  1777. <dd><p>Conditional branch instruction combined with a compare instruction.
  1778. Operand 0 is a comparison operator. Operand 1 and operand 2 are the
  1779. first and second operands of the comparison, respectively. Operand 3
  1780. is the <code>code_label</code> to jump to.
  1781. </p>
  1782. <a name="index-jump-instruction-pattern"></a>
  1783. </dd>
  1784. <dt>&lsquo;<samp>jump</samp>&rsquo;</dt>
  1785. <dd><p>A jump inside a function; an unconditional branch. Operand 0 is the
  1786. <code>code_label</code> to jump to. This pattern name is mandatory on all
  1787. machines.
  1788. </p>
  1789. <a name="index-call-instruction-pattern"></a>
  1790. </dd>
  1791. <dt>&lsquo;<samp>call</samp>&rsquo;</dt>
  1792. <dd><p>Subroutine call instruction returning no value. Operand 0 is the
  1793. function to call; operand 1 is the number of bytes of arguments pushed
  1794. as a <code>const_int</code>; operand 2 is the number of registers used as
  1795. operands.
  1796. </p>
  1797. <p>On most machines, operand 2 is not actually stored into the RTL
  1798. pattern. It is supplied for the sake of some RISC machines which need
  1799. to put this information into the assembler code; they can put it in
  1800. the RTL instead of operand 1.
  1801. </p>
  1802. <p>Operand 0 should be a <code>mem</code> RTX whose address is the address of the
  1803. function. Note, however, that this address can be a <code>symbol_ref</code>
  1804. expression even if it would not be a legitimate memory address on the
  1805. target machine. If it is also not a valid argument for a call
  1806. instruction, the pattern for this operation should be a
  1807. <code>define_expand</code> (see <a href="Expander-Definitions.html#Expander-Definitions">Expander Definitions</a>) that places the
  1808. address into a register and uses that register in the call instruction.
  1809. </p>
  1810. <a name="index-call_005fvalue-instruction-pattern"></a>
  1811. </dd>
  1812. <dt>&lsquo;<samp>call_value</samp>&rsquo;</dt>
  1813. <dd><p>Subroutine call instruction returning a value. Operand 0 is the hard
  1814. register in which the value is returned. There are three more
  1815. operands, the same as the three operands of the &lsquo;<samp>call</samp>&rsquo;
  1816. instruction (but with numbers increased by one).
  1817. </p>
  1818. <p>Subroutines that return <code>BLKmode</code> objects use the &lsquo;<samp>call</samp>&rsquo;
  1819. insn.
  1820. </p>
  1821. <a name="index-call_005fpop-instruction-pattern"></a>
  1822. <a name="index-call_005fvalue_005fpop-instruction-pattern"></a>
  1823. </dd>
  1824. <dt>&lsquo;<samp>call_pop</samp>&rsquo;, &lsquo;<samp>call_value_pop</samp>&rsquo;</dt>
  1825. <dd><p>Similar to &lsquo;<samp>call</samp>&rsquo; and &lsquo;<samp>call_value</samp>&rsquo;, except used if defined and
  1826. if <code>RETURN_POPS_ARGS</code> is nonzero. They should emit a <code>parallel</code>
  1827. that contains both the function call and a <code>set</code> to indicate the
  1828. adjustment made to the frame pointer.
  1829. </p>
  1830. <p>For machines where <code>RETURN_POPS_ARGS</code> can be nonzero, the use of these
  1831. patterns increases the number of functions for which the frame pointer
  1832. can be eliminated, if desired.
  1833. </p>
  1834. <a name="index-untyped_005fcall-instruction-pattern"></a>
  1835. </dd>
  1836. <dt>&lsquo;<samp>untyped_call</samp>&rsquo;</dt>
  1837. <dd><p>Subroutine call instruction returning a value of any type. Operand 0 is
  1838. the function to call; operand 1 is a memory location where the result of
  1839. calling the function is to be stored; operand 2 is a <code>parallel</code>
  1840. expression where each element is a <code>set</code> expression that indicates
  1841. the saving of a function return value into the result block.
  1842. </p>
  1843. <p>This instruction pattern should be defined to support
  1844. <code>__builtin_apply</code> on machines where special instructions are needed
  1845. to call a subroutine with arbitrary arguments or to save the value
  1846. returned. This instruction pattern is required on machines that have
  1847. multiple registers that can hold a return value
  1848. (i.e. <code>FUNCTION_VALUE_REGNO_P</code> is true for more than one register).
  1849. </p>
  1850. <a name="index-return-instruction-pattern"></a>
  1851. </dd>
  1852. <dt>&lsquo;<samp>return</samp>&rsquo;</dt>
  1853. <dd><p>Subroutine return instruction. This instruction pattern name should be
  1854. defined only if a single instruction can do all the work of returning
  1855. from a function.
  1856. </p>
  1857. <p>Like the &lsquo;<samp>mov<var>m</var></samp>&rsquo; patterns, this pattern is also used after the
  1858. RTL generation phase. In this case it is to support machines where
  1859. multiple instructions are usually needed to return from a function, but
  1860. some class of functions only requires one instruction to implement a
  1861. return. Normally, the applicable functions are those which do not need
  1862. to save any registers or allocate stack space.
  1863. </p>
  1864. <p>It is valid for this pattern to expand to an instruction using
  1865. <code>simple_return</code> if no epilogue is required.
  1866. </p>
  1867. <a name="index-simple_005freturn-instruction-pattern"></a>
  1868. </dd>
  1869. <dt>&lsquo;<samp>simple_return</samp>&rsquo;</dt>
  1870. <dd><p>Subroutine return instruction. This instruction pattern name should be
  1871. defined only if a single instruction can do all the work of returning
  1872. from a function on a path where no epilogue is required. This pattern
  1873. is very similar to the <code>return</code> instruction pattern, but it is emitted
  1874. only by the shrink-wrapping optimization on paths where the function
  1875. prologue has not been executed, and a function return should occur without
  1876. any of the effects of the epilogue. Additional uses may be introduced on
  1877. paths where both the prologue and the epilogue have executed.
  1878. </p>
  1879. <a name="index-reload_005fcompleted"></a>
  1880. <a name="index-leaf_005ffunction_005fp"></a>
  1881. <p>For such machines, the condition specified in this pattern should only
  1882. be true when <code>reload_completed</code> is nonzero and the function&rsquo;s
  1883. epilogue would only be a single instruction. For machines with register
  1884. windows, the routine <code>leaf_function_p</code> may be used to determine if
  1885. a register window push is required.
  1886. </p>
  1887. <p>Machines that have conditional return instructions should define patterns
  1888. such as
  1889. </p>
  1890. <div class="smallexample">
  1891. <pre class="smallexample">(define_insn &quot;&quot;
  1892. [(set (pc)
  1893. (if_then_else (match_operator
  1894. 0 &quot;comparison_operator&quot;
  1895. [(cc0) (const_int 0)])
  1896. (return)
  1897. (pc)))]
  1898. &quot;<var>condition</var>&quot;
  1899. &quot;&hellip;&quot;)
  1900. </pre></div>
  1901. <p>where <var>condition</var> would normally be the same condition specified on the
  1902. named &lsquo;<samp>return</samp>&rsquo; pattern.
  1903. </p>
  1904. <a name="index-untyped_005freturn-instruction-pattern"></a>
  1905. </dd>
  1906. <dt>&lsquo;<samp>untyped_return</samp>&rsquo;</dt>
  1907. <dd><p>Untyped subroutine return instruction. This instruction pattern should
  1908. be defined to support <code>__builtin_return</code> on machines where special
  1909. instructions are needed to return a value of any type.
  1910. </p>
  1911. <p>Operand 0 is a memory location where the result of calling a function
  1912. with <code>__builtin_apply</code> is stored; operand 1 is a <code>parallel</code>
  1913. expression where each element is a <code>set</code> expression that indicates
  1914. the restoring of a function return value from the result block.
  1915. </p>
  1916. <a name="index-nop-instruction-pattern"></a>
  1917. </dd>
  1918. <dt>&lsquo;<samp>nop</samp>&rsquo;</dt>
  1919. <dd><p>No-op instruction. This instruction pattern name should always be defined
  1920. to output a no-op in assembler code. <code>(const_int 0)</code> will do as an
  1921. RTL pattern.
  1922. </p>
  1923. <a name="index-indirect_005fjump-instruction-pattern"></a>
  1924. </dd>
  1925. <dt>&lsquo;<samp>indirect_jump</samp>&rsquo;</dt>
  1926. <dd><p>An instruction to jump to an address which is operand zero.
  1927. This pattern name is mandatory on all machines.
  1928. </p>
  1929. <a name="index-casesi-instruction-pattern"></a>
  1930. </dd>
  1931. <dt>&lsquo;<samp>casesi</samp>&rsquo;</dt>
  1932. <dd><p>Instruction to jump through a dispatch table, including bounds checking.
  1933. This instruction takes five operands:
  1934. </p>
  1935. <ol>
  1936. <li> The index to dispatch on, which has mode <code>SImode</code>.
  1937. </li><li> The lower bound for indices in the table, an integer constant.
  1938. </li><li> The total range of indices in the table&mdash;the largest index
  1939. minus the smallest one (both inclusive).
  1940. </li><li> A label that precedes the table itself.
  1941. </li><li> A label to jump to if the index has a value outside the bounds.
  1942. </li></ol>
  1943. <p>The table is an <code>addr_vec</code> or <code>addr_diff_vec</code> inside of a
  1944. <code>jump_table_data</code>. The number of elements in the table is one plus the
  1945. difference between the upper bound and the lower bound.
  1946. </p>
  1947. <a name="index-tablejump-instruction-pattern"></a>
  1948. </dd>
  1949. <dt>&lsquo;<samp>tablejump</samp>&rsquo;</dt>
  1950. <dd><p>Instruction to jump to a variable address. This is a low-level
  1951. capability which can be used to implement a dispatch table when there
  1952. is no &lsquo;<samp>casesi</samp>&rsquo; pattern.
  1953. </p>
  1954. <p>This pattern requires two operands: the address or offset, and a label
  1955. which should immediately precede the jump table. If the macro
  1956. <code>CASE_VECTOR_PC_RELATIVE</code> evaluates to a nonzero value then the first
  1957. operand is an offset which counts from the address of the table; otherwise,
  1958. it is an absolute address to jump to. In either case, the first operand has
  1959. mode <code>Pmode</code>.
  1960. </p>
  1961. <p>The &lsquo;<samp>tablejump</samp>&rsquo; insn is always the last insn before the jump
  1962. table it uses. Its assembler code normally has no need to use the
  1963. second operand, but you should incorporate it in the RTL pattern so
  1964. that the jump optimizer will not delete the table as unreachable code.
  1965. </p>
  1966. <a name="index-decrement_005fand_005fbranch_005funtil_005fzero-instruction-pattern"></a>
  1967. </dd>
  1968. <dt>&lsquo;<samp>decrement_and_branch_until_zero</samp>&rsquo;</dt>
  1969. <dd><p>Conditional branch instruction that decrements a register and
  1970. jumps if the register is nonzero. Operand 0 is the register to
  1971. decrement and test; operand 1 is the label to jump to if the
  1972. register is nonzero. See <a href="Looping-Patterns.html#Looping-Patterns">Looping Patterns</a>.
  1973. </p>
  1974. <p>This optional instruction pattern is only used by the combiner,
  1975. typically for loops reversed by the loop optimizer when strength
  1976. reduction is enabled.
  1977. </p>
  1978. <a name="index-doloop_005fend-instruction-pattern"></a>
  1979. </dd>
  1980. <dt>&lsquo;<samp>doloop_end</samp>&rsquo;</dt>
  1981. <dd><p>Conditional branch instruction that decrements a register and
  1982. jumps if the register is nonzero. Operand 0 is the register to
  1983. decrement and test; operand 1 is the label to jump to if the
  1984. register is nonzero.
  1985. See <a href="Looping-Patterns.html#Looping-Patterns">Looping Patterns</a>.
  1986. </p>
  1987. <p>This optional instruction pattern should be defined for machines with
  1988. low-overhead looping instructions as the loop optimizer will try to
  1989. modify suitable loops to utilize it. The target hook
  1990. <code>TARGET_CAN_USE_DOLOOP_P</code> controls the conditions under which
  1991. low-overhead loops can be used.
  1992. </p>
  1993. <a name="index-doloop_005fbegin-instruction-pattern"></a>
  1994. </dd>
  1995. <dt>&lsquo;<samp>doloop_begin</samp>&rsquo;</dt>
  1996. <dd><p>Companion instruction to <code>doloop_end</code> required for machines that
  1997. need to perform some initialization, such as loading a special counter
  1998. register. Operand 1 is the associated <code>doloop_end</code> pattern and
  1999. operand 0 is the register that it decrements.
  2000. </p>
  2001. <p>If initialization insns do not always need to be emitted, use a
  2002. <code>define_expand</code> (see <a href="Expander-Definitions.html#Expander-Definitions">Expander Definitions</a>) and make it fail.
  2003. </p>
  2004. <a name="index-canonicalize_005ffuncptr_005ffor_005fcompare-instruction-pattern"></a>
  2005. </dd>
  2006. <dt>&lsquo;<samp>canonicalize_funcptr_for_compare</samp>&rsquo;</dt>
  2007. <dd><p>Canonicalize the function pointer in operand 1 and store the result
  2008. into operand 0.
  2009. </p>
  2010. <p>Operand 0 is always a <code>reg</code> and has mode <code>Pmode</code>; operand 1
  2011. may be a <code>reg</code>, <code>mem</code>, <code>symbol_ref</code>, <code>const_int</code>, etc
  2012. and also has mode <code>Pmode</code>.
  2013. </p>
  2014. <p>Canonicalization of a function pointer usually involves computing
  2015. the address of the function which would be called if the function
  2016. pointer were used in an indirect call.
  2017. </p>
  2018. <p>Only define this pattern if function pointers on the target machine
  2019. can have different values but still call the same function when
  2020. used in an indirect call.
  2021. </p>
  2022. <a name="index-save_005fstack_005fblock-instruction-pattern"></a>
  2023. <a name="index-save_005fstack_005ffunction-instruction-pattern"></a>
  2024. <a name="index-save_005fstack_005fnonlocal-instruction-pattern"></a>
  2025. <a name="index-restore_005fstack_005fblock-instruction-pattern"></a>
  2026. <a name="index-restore_005fstack_005ffunction-instruction-pattern"></a>
  2027. <a name="index-restore_005fstack_005fnonlocal-instruction-pattern"></a>
  2028. </dd>
  2029. <dt>&lsquo;<samp>save_stack_block</samp>&rsquo;</dt>
  2030. <dt>&lsquo;<samp>save_stack_function</samp>&rsquo;</dt>
  2031. <dt>&lsquo;<samp>save_stack_nonlocal</samp>&rsquo;</dt>
  2032. <dt>&lsquo;<samp>restore_stack_block</samp>&rsquo;</dt>
  2033. <dt>&lsquo;<samp>restore_stack_function</samp>&rsquo;</dt>
  2034. <dt>&lsquo;<samp>restore_stack_nonlocal</samp>&rsquo;</dt>
  2035. <dd><p>Most machines save and restore the stack pointer by copying it to or
  2036. from an object of mode <code>Pmode</code>. Do not define these patterns on
  2037. such machines.
  2038. </p>
  2039. <p>Some machines require special handling for stack pointer saves and
  2040. restores. On those machines, define the patterns corresponding to the
  2041. non-standard cases by using a <code>define_expand</code> (see <a href="Expander-Definitions.html#Expander-Definitions">Expander Definitions</a>) that produces the required insns. The three types of
  2042. saves and restores are:
  2043. </p>
  2044. <ol>
  2045. <li> &lsquo;<samp>save_stack_block</samp>&rsquo; saves the stack pointer at the start of a block
  2046. that allocates a variable-sized object, and &lsquo;<samp>restore_stack_block</samp>&rsquo;
  2047. restores the stack pointer when the block is exited.
  2048. </li><li> &lsquo;<samp>save_stack_function</samp>&rsquo; and &lsquo;<samp>restore_stack_function</samp>&rsquo; do a
  2049. similar job for the outermost block of a function and are used when the
  2050. function allocates variable-sized objects or calls <code>alloca</code>. Only
  2051. the epilogue uses the restored stack pointer, allowing a simpler save or
  2052. restore sequence on some machines.
  2053. </li><li> &lsquo;<samp>save_stack_nonlocal</samp>&rsquo; is used in functions that contain labels
  2054. branched to by nested functions. It saves the stack pointer in such a
  2055. way that the inner function can use &lsquo;<samp>restore_stack_nonlocal</samp>&rsquo; to
  2056. restore the stack pointer. The compiler generates code to restore the
  2057. frame and argument pointer registers, but some machines require saving
  2058. and restoring additional data such as register window information or
  2059. stack backchains. Place insns in these patterns to save and restore any
  2060. such required data.
  2061. </li></ol>
  2062. <p>When saving the stack pointer, operand 0 is the save area and operand 1
  2063. is the stack pointer. The mode used to allocate the save area defaults
  2064. to <code>Pmode</code> but you can override that choice by defining the
  2065. <code>STACK_SAVEAREA_MODE</code> macro (see <a href="Storage-Layout.html#Storage-Layout">Storage Layout</a>). You must
  2066. specify an integral mode, or <code>VOIDmode</code> if no save area is needed
  2067. for a particular type of save (either because no save is needed or
  2068. because a machine-specific save area can be used). Operand 0 is the
  2069. stack pointer and operand 1 is the save area for restore operations. If
  2070. &lsquo;<samp>save_stack_block</samp>&rsquo; is defined, operand 0 must not be
  2071. <code>VOIDmode</code> since these saves can be arbitrarily nested.
  2072. </p>
  2073. <p>A save area is a <code>mem</code> that is at a constant offset from
  2074. <code>virtual_stack_vars_rtx</code> when the stack pointer is saved for use by
  2075. nonlocal gotos and a <code>reg</code> in the other two cases.
  2076. </p>
  2077. <a name="index-allocate_005fstack-instruction-pattern"></a>
  2078. </dd>
  2079. <dt>&lsquo;<samp>allocate_stack</samp>&rsquo;</dt>
  2080. <dd><p>Subtract (or add if <code>STACK_GROWS_DOWNWARD</code> is undefined) operand 1 from
  2081. the stack pointer to create space for dynamically allocated data.
  2082. </p>
  2083. <p>Store the resultant pointer to this space into operand 0. If you
  2084. are allocating space from the main stack, do this by emitting a
  2085. move insn to copy <code>virtual_stack_dynamic_rtx</code> to operand 0.
  2086. If you are allocating the space elsewhere, generate code to copy the
  2087. location of the space to operand 0. In the latter case, you must
  2088. ensure this space gets freed when the corresponding space on the main
  2089. stack is free.
  2090. </p>
  2091. <p>Do not define this pattern if all that must be done is the subtraction.
  2092. Some machines require other operations such as stack probes or
  2093. maintaining the back chain. Define this pattern to emit those
  2094. operations in addition to updating the stack pointer.
  2095. </p>
  2096. <a name="index-check_005fstack-instruction-pattern"></a>
  2097. </dd>
  2098. <dt>&lsquo;<samp>check_stack</samp>&rsquo;</dt>
  2099. <dd><p>If stack checking (see <a href="Stack-Checking.html#Stack-Checking">Stack Checking</a>) cannot be done on your system by
  2100. probing the stack, define this pattern to perform the needed check and signal
  2101. an error if the stack has overflowed. The single operand is the address in
  2102. the stack farthest from the current stack pointer that you need to validate.
  2103. Normally, on platforms where this pattern is needed, you would obtain the
  2104. stack limit from a global or thread-specific variable or register.
  2105. </p>
  2106. <a name="index-probe_005fstack_005faddress-instruction-pattern"></a>
  2107. </dd>
  2108. <dt>&lsquo;<samp>probe_stack_address</samp>&rsquo;</dt>
  2109. <dd><p>If stack checking (see <a href="Stack-Checking.html#Stack-Checking">Stack Checking</a>) can be done on your system by
  2110. probing the stack but without the need to actually access it, define this
  2111. pattern and signal an error if the stack has overflowed. The single operand
  2112. is the memory address in the stack that needs to be probed.
  2113. </p>
  2114. <a name="index-probe_005fstack-instruction-pattern"></a>
  2115. </dd>
  2116. <dt>&lsquo;<samp>probe_stack</samp>&rsquo;</dt>
  2117. <dd><p>If stack checking (see <a href="Stack-Checking.html#Stack-Checking">Stack Checking</a>) can be done on your system by
  2118. probing the stack but doing it with a &ldquo;store zero&rdquo; instruction is not valid
  2119. or optimal, define this pattern to do the probing differently and signal an
  2120. error if the stack has overflowed. The single operand is the memory reference
  2121. in the stack that needs to be probed.
  2122. </p>
  2123. <a name="index-nonlocal_005fgoto-instruction-pattern"></a>
  2124. </dd>
  2125. <dt>&lsquo;<samp>nonlocal_goto</samp>&rsquo;</dt>
  2126. <dd><p>Emit code to generate a non-local goto, e.g., a jump from one function
  2127. to a label in an outer function. This pattern has four arguments,
  2128. each representing a value to be used in the jump. The first
  2129. argument is to be loaded into the frame pointer, the second is
  2130. the address to branch to (code to dispatch to the actual label),
  2131. the third is the address of a location where the stack is saved,
  2132. and the last is the address of the label, to be placed in the
  2133. location for the incoming static chain.
  2134. </p>
  2135. <p>On most machines you need not define this pattern, since GCC will
  2136. already generate the correct code, which is to load the frame pointer
  2137. and static chain, restore the stack (using the
  2138. &lsquo;<samp>restore_stack_nonlocal</samp>&rsquo; pattern, if defined), and jump indirectly
  2139. to the dispatcher. You need only define this pattern if this code will
  2140. not work on your machine.
  2141. </p>
  2142. <a name="index-nonlocal_005fgoto_005freceiver-instruction-pattern"></a>
  2143. </dd>
  2144. <dt>&lsquo;<samp>nonlocal_goto_receiver</samp>&rsquo;</dt>
  2145. <dd><p>This pattern, if defined, contains code needed at the target of a
  2146. nonlocal goto after the code already generated by GCC. You will not
  2147. normally need to define this pattern. A typical reason why you might
  2148. need this pattern is if some value, such as a pointer to a global table,
  2149. must be restored when the frame pointer is restored. Note that a nonlocal
  2150. goto only occurs within a unit-of-translation, so a global table pointer
  2151. that is shared by all functions of a given module need not be restored.
  2152. There are no arguments.
  2153. </p>
  2154. <a name="index-exception_005freceiver-instruction-pattern"></a>
  2155. </dd>
  2156. <dt>&lsquo;<samp>exception_receiver</samp>&rsquo;</dt>
  2157. <dd><p>This pattern, if defined, contains code needed at the site of an
  2158. exception handler that isn&rsquo;t needed at the site of a nonlocal goto. You
  2159. will not normally need to define this pattern. A typical reason why you
  2160. might need this pattern is if some value, such as a pointer to a global
  2161. table, must be restored after control flow is branched to the handler of
  2162. an exception. There are no arguments.
  2163. </p>
  2164. <a name="index-builtin_005fsetjmp_005fsetup-instruction-pattern"></a>
  2165. </dd>
  2166. <dt>&lsquo;<samp>builtin_setjmp_setup</samp>&rsquo;</dt>
  2167. <dd><p>This pattern, if defined, contains additional code needed to initialize
  2168. the <code>jmp_buf</code>. You will not normally need to define this pattern.
  2169. A typical reason why you might need this pattern is if some value, such
  2170. as a pointer to a global table, must be restored. Though it is
  2171. preferred that the pointer value be recalculated if possible (given the
  2172. address of a label for instance). The single argument is a pointer to
  2173. the <code>jmp_buf</code>. Note that the buffer is five words long and that
  2174. the first three are normally used by the generic mechanism.
  2175. </p>
  2176. <a name="index-builtin_005fsetjmp_005freceiver-instruction-pattern"></a>
  2177. </dd>
  2178. <dt>&lsquo;<samp>builtin_setjmp_receiver</samp>&rsquo;</dt>
  2179. <dd><p>This pattern, if defined, contains code needed at the site of a
  2180. built-in setjmp that isn&rsquo;t needed at the site of a nonlocal goto. You
  2181. will not normally need to define this pattern. A typical reason why you
  2182. might need this pattern is if some value, such as a pointer to a global
  2183. table, must be restored. It takes one argument, which is the label
  2184. to which builtin_longjmp transferred control; this pattern may be emitted
  2185. at a small offset from that label.
  2186. </p>
  2187. <a name="index-builtin_005flongjmp-instruction-pattern"></a>
  2188. </dd>
  2189. <dt>&lsquo;<samp>builtin_longjmp</samp>&rsquo;</dt>
  2190. <dd><p>This pattern, if defined, performs the entire action of the longjmp.
  2191. You will not normally need to define this pattern unless you also define
  2192. <code>builtin_setjmp_setup</code>. The single argument is a pointer to the
  2193. <code>jmp_buf</code>.
  2194. </p>
  2195. <a name="index-eh_005freturn-instruction-pattern"></a>
  2196. </dd>
  2197. <dt>&lsquo;<samp>eh_return</samp>&rsquo;</dt>
  2198. <dd><p>This pattern, if defined, affects the way <code>__builtin_eh_return</code>,
  2199. and thence the call frame exception handling library routines, are
  2200. built. It is intended to handle non-trivial actions needed along
  2201. the abnormal return path.
  2202. </p>
  2203. <p>The address of the exception handler to which the function should return
  2204. is passed as operand to this pattern. It will normally need to copied by
  2205. the pattern to some special register or memory location.
  2206. If the pattern needs to determine the location of the target call
  2207. frame in order to do so, it may use <code>EH_RETURN_STACKADJ_RTX</code>,
  2208. if defined; it will have already been assigned.
  2209. </p>
  2210. <p>If this pattern is not defined, the default action will be to simply
  2211. copy the return address to <code>EH_RETURN_HANDLER_RTX</code>. Either
  2212. that macro or this pattern needs to be defined if call frame exception
  2213. handling is to be used.
  2214. </p>
  2215. <a name="index-prologue-instruction-pattern"></a>
  2216. <a name="prologue-instruction-pattern"></a></dd>
  2217. <dt>&lsquo;<samp>prologue</samp>&rsquo;</dt>
  2218. <dd><p>This pattern, if defined, emits RTL for entry to a function. The function
  2219. entry is responsible for setting up the stack frame, initializing the frame
  2220. pointer register, saving callee saved registers, etc.
  2221. </p>
  2222. <p>Using a prologue pattern is generally preferred over defining
  2223. <code>TARGET_ASM_FUNCTION_PROLOGUE</code> to emit assembly code for the prologue.
  2224. </p>
  2225. <p>The <code>prologue</code> pattern is particularly useful for targets which perform
  2226. instruction scheduling.
  2227. </p>
  2228. <a name="index-window_005fsave-instruction-pattern"></a>
  2229. <a name="window_005fsave-instruction-pattern"></a></dd>
  2230. <dt>&lsquo;<samp>window_save</samp>&rsquo;</dt>
  2231. <dd><p>This pattern, if defined, emits RTL for a register window save. It should
  2232. be defined if the target machine has register windows but the window events
  2233. are decoupled from calls to subroutines. The canonical example is the SPARC
  2234. architecture.
  2235. </p>
  2236. <a name="index-epilogue-instruction-pattern"></a>
  2237. <a name="epilogue-instruction-pattern"></a></dd>
  2238. <dt>&lsquo;<samp>epilogue</samp>&rsquo;</dt>
  2239. <dd><p>This pattern emits RTL for exit from a function. The function
  2240. exit is responsible for deallocating the stack frame, restoring callee saved
  2241. registers and emitting the return instruction.
  2242. </p>
  2243. <p>Using an epilogue pattern is generally preferred over defining
  2244. <code>TARGET_ASM_FUNCTION_EPILOGUE</code> to emit assembly code for the epilogue.
  2245. </p>
  2246. <p>The <code>epilogue</code> pattern is particularly useful for targets which perform
  2247. instruction scheduling or which have delay slots for their return instruction.
  2248. </p>
  2249. <a name="index-sibcall_005fepilogue-instruction-pattern"></a>
  2250. </dd>
  2251. <dt>&lsquo;<samp>sibcall_epilogue</samp>&rsquo;</dt>
  2252. <dd><p>This pattern, if defined, emits RTL for exit from a function without the final
  2253. branch back to the calling function. This pattern will be emitted before any
  2254. sibling call (aka tail call) sites.
  2255. </p>
  2256. <p>The <code>sibcall_epilogue</code> pattern must not clobber any arguments used for
  2257. parameter passing or any stack slots for arguments passed to the current
  2258. function.
  2259. </p>
  2260. <a name="index-trap-instruction-pattern"></a>
  2261. </dd>
  2262. <dt>&lsquo;<samp>trap</samp>&rsquo;</dt>
  2263. <dd><p>This pattern, if defined, signals an error, typically by causing some
  2264. kind of signal to be raised.
  2265. </p>
  2266. <a name="index-ctrapMM4-instruction-pattern"></a>
  2267. </dd>
  2268. <dt>&lsquo;<samp>ctrap<var>MM</var>4</samp>&rsquo;</dt>
  2269. <dd><p>Conditional trap instruction. Operand 0 is a piece of RTL which
  2270. performs a comparison, and operands 1 and 2 are the arms of the
  2271. comparison. Operand 3 is the trap code, an integer.
  2272. </p>
  2273. <p>A typical <code>ctrap</code> pattern looks like
  2274. </p>
  2275. <div class="smallexample">
  2276. <pre class="smallexample">(define_insn &quot;ctrapsi4&quot;
  2277. [(trap_if (match_operator 0 &quot;trap_operator&quot;
  2278. [(match_operand 1 &quot;register_operand&quot;)
  2279. (match_operand 2 &quot;immediate_operand&quot;)])
  2280. (match_operand 3 &quot;const_int_operand&quot; &quot;i&quot;))]
  2281. &quot;&quot;
  2282. &quot;&hellip;&quot;)
  2283. </pre></div>
  2284. <a name="index-prefetch-instruction-pattern"></a>
  2285. </dd>
  2286. <dt>&lsquo;<samp>prefetch</samp>&rsquo;</dt>
  2287. <dd><p>This pattern, if defined, emits code for a non-faulting data prefetch
  2288. instruction. Operand 0 is the address of the memory to prefetch. Operand 1
  2289. is a constant 1 if the prefetch is preparing for a write to the memory
  2290. address, or a constant 0 otherwise. Operand 2 is the expected degree of
  2291. temporal locality of the data and is a value between 0 and 3, inclusive; 0
  2292. means that the data has no temporal locality, so it need not be left in the
  2293. cache after the access; 3 means that the data has a high degree of temporal
  2294. locality and should be left in all levels of cache possible; 1 and 2 mean,
  2295. respectively, a low or moderate degree of temporal locality.
  2296. </p>
  2297. <p>Targets that do not support write prefetches or locality hints can ignore
  2298. the values of operands 1 and 2.
  2299. </p>
  2300. <a name="index-blockage-instruction-pattern"></a>
  2301. </dd>
  2302. <dt>&lsquo;<samp>blockage</samp>&rsquo;</dt>
  2303. <dd><p>This pattern defines a pseudo insn that prevents the instruction
  2304. scheduler and other passes from moving instructions and using register
  2305. equivalences across the boundary defined by the blockage insn.
  2306. This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
  2307. </p>
  2308. <a name="index-memory_005fbarrier-instruction-pattern"></a>
  2309. </dd>
  2310. <dt>&lsquo;<samp>memory_barrier</samp>&rsquo;</dt>
  2311. <dd><p>If the target memory model is not fully synchronous, then this pattern
  2312. should be defined to an instruction that orders both loads and stores
  2313. before the instruction with respect to loads and stores after the instruction.
  2314. This pattern has no operands.
  2315. </p>
  2316. <a name="index-sync_005fcompare_005fand_005fswapmode-instruction-pattern"></a>
  2317. </dd>
  2318. <dt>&lsquo;<samp>sync_compare_and_swap<var>mode</var></samp>&rsquo;</dt>
  2319. <dd><p>This pattern, if defined, emits code for an atomic compare-and-swap
  2320. operation. Operand 1 is the memory on which the atomic operation is
  2321. performed. Operand 2 is the &ldquo;old&rdquo; value to be compared against the
  2322. current contents of the memory location. Operand 3 is the &ldquo;new&rdquo; value
  2323. to store in the memory if the compare succeeds. Operand 0 is the result
  2324. of the operation; it should contain the contents of the memory
  2325. before the operation. If the compare succeeds, this should obviously be
  2326. a copy of operand 2.
  2327. </p>
  2328. <p>This pattern must show that both operand 0 and operand 1 are modified.
  2329. </p>
  2330. <p>This pattern must issue any memory barrier instructions such that all
  2331. memory operations before the atomic operation occur before the atomic
  2332. operation and all memory operations after the atomic operation occur
  2333. after the atomic operation.
  2334. </p>
  2335. <p>For targets where the success or failure of the compare-and-swap
  2336. operation is available via the status flags, it is possible to
  2337. avoid a separate compare operation and issue the subsequent
  2338. branch or store-flag operation immediately after the compare-and-swap.
  2339. To this end, GCC will look for a <code>MODE_CC</code> set in the
  2340. output of <code>sync_compare_and_swap<var>mode</var></code>; if the machine
  2341. description includes such a set, the target should also define special
  2342. <code>cbranchcc4</code> and/or <code>cstorecc4</code> instructions. GCC will then
  2343. be able to take the destination of the <code>MODE_CC</code> set and pass it
  2344. to the <code>cbranchcc4</code> or <code>cstorecc4</code> pattern as the first
  2345. operand of the comparison (the second will be <code>(const_int 0)</code>).
  2346. </p>
  2347. <p>For targets where the operating system may provide support for this
  2348. operation via library calls, the <code>sync_compare_and_swap_optab</code>
  2349. may be initialized to a function with the same interface as the
  2350. <code>__sync_val_compare_and_swap_<var>n</var></code> built-in. If the entire
  2351. set of <var>__sync</var> builtins are supported via library calls, the
  2352. target can initialize all of the optabs at once with
  2353. <code>init_sync_libfuncs</code>.
  2354. For the purposes of C++11 <code>std::atomic::is_lock_free</code>, it is
  2355. assumed that these library calls do <em>not</em> use any kind of
  2356. interruptable locking.
  2357. </p>
  2358. <a name="index-sync_005faddmode-instruction-pattern"></a>
  2359. <a name="index-sync_005fsubmode-instruction-pattern"></a>
  2360. <a name="index-sync_005fiormode-instruction-pattern"></a>
  2361. <a name="index-sync_005fandmode-instruction-pattern"></a>
  2362. <a name="index-sync_005fxormode-instruction-pattern"></a>
  2363. <a name="index-sync_005fnandmode-instruction-pattern"></a>
  2364. </dd>
  2365. <dt>&lsquo;<samp>sync_add<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_sub<var>mode</var></samp>&rsquo;</dt>
  2366. <dt>&lsquo;<samp>sync_ior<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_and<var>mode</var></samp>&rsquo;</dt>
  2367. <dt>&lsquo;<samp>sync_xor<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_nand<var>mode</var></samp>&rsquo;</dt>
  2368. <dd><p>These patterns emit code for an atomic operation on memory.
  2369. Operand 0 is the memory on which the atomic operation is performed.
  2370. Operand 1 is the second operand to the binary operator.
  2371. </p>
  2372. <p>This pattern must issue any memory barrier instructions such that all
  2373. memory operations before the atomic operation occur before the atomic
  2374. operation and all memory operations after the atomic operation occur
  2375. after the atomic operation.
  2376. </p>
  2377. <p>If these patterns are not defined, the operation will be constructed
  2378. from a compare-and-swap operation, if defined.
  2379. </p>
  2380. <a name="index-sync_005fold_005faddmode-instruction-pattern"></a>
  2381. <a name="index-sync_005fold_005fsubmode-instruction-pattern"></a>
  2382. <a name="index-sync_005fold_005fiormode-instruction-pattern"></a>
  2383. <a name="index-sync_005fold_005fandmode-instruction-pattern"></a>
  2384. <a name="index-sync_005fold_005fxormode-instruction-pattern"></a>
  2385. <a name="index-sync_005fold_005fnandmode-instruction-pattern"></a>
  2386. </dd>
  2387. <dt>&lsquo;<samp>sync_old_add<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_old_sub<var>mode</var></samp>&rsquo;</dt>
  2388. <dt>&lsquo;<samp>sync_old_ior<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_old_and<var>mode</var></samp>&rsquo;</dt>
  2389. <dt>&lsquo;<samp>sync_old_xor<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_old_nand<var>mode</var></samp>&rsquo;</dt>
  2390. <dd><p>These patterns emit code for an atomic operation on memory,
  2391. and return the value that the memory contained before the operation.
  2392. Operand 0 is the result value, operand 1 is the memory on which the
  2393. atomic operation is performed, and operand 2 is the second operand
  2394. to the binary operator.
  2395. </p>
  2396. <p>This pattern must issue any memory barrier instructions such that all
  2397. memory operations before the atomic operation occur before the atomic
  2398. operation and all memory operations after the atomic operation occur
  2399. after the atomic operation.
  2400. </p>
  2401. <p>If these patterns are not defined, the operation will be constructed
  2402. from a compare-and-swap operation, if defined.
  2403. </p>
  2404. <a name="index-sync_005fnew_005faddmode-instruction-pattern"></a>
  2405. <a name="index-sync_005fnew_005fsubmode-instruction-pattern"></a>
  2406. <a name="index-sync_005fnew_005fiormode-instruction-pattern"></a>
  2407. <a name="index-sync_005fnew_005fandmode-instruction-pattern"></a>
  2408. <a name="index-sync_005fnew_005fxormode-instruction-pattern"></a>
  2409. <a name="index-sync_005fnew_005fnandmode-instruction-pattern"></a>
  2410. </dd>
  2411. <dt>&lsquo;<samp>sync_new_add<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_new_sub<var>mode</var></samp>&rsquo;</dt>
  2412. <dt>&lsquo;<samp>sync_new_ior<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_new_and<var>mode</var></samp>&rsquo;</dt>
  2413. <dt>&lsquo;<samp>sync_new_xor<var>mode</var></samp>&rsquo;, &lsquo;<samp>sync_new_nand<var>mode</var></samp>&rsquo;</dt>
  2414. <dd><p>These patterns are like their <code>sync_old_<var>op</var></code> counterparts,
  2415. except that they return the value that exists in the memory location
  2416. after the operation, rather than before the operation.
  2417. </p>
  2418. <a name="index-sync_005flock_005ftest_005fand_005fsetmode-instruction-pattern"></a>
  2419. </dd>
  2420. <dt>&lsquo;<samp>sync_lock_test_and_set<var>mode</var></samp>&rsquo;</dt>
  2421. <dd><p>This pattern takes two forms, based on the capabilities of the target.
  2422. In either case, operand 0 is the result of the operand, operand 1 is
  2423. the memory on which the atomic operation is performed, and operand 2
  2424. is the value to set in the lock.
  2425. </p>
  2426. <p>In the ideal case, this operation is an atomic exchange operation, in
  2427. which the previous value in memory operand is copied into the result
  2428. operand, and the value operand is stored in the memory operand.
  2429. </p>
  2430. <p>For less capable targets, any value operand that is not the constant 1
  2431. should be rejected with <code>FAIL</code>. In this case the target may use
  2432. an atomic test-and-set bit operation. The result operand should contain
  2433. 1 if the bit was previously set and 0 if the bit was previously clear.
  2434. The true contents of the memory operand are implementation defined.
  2435. </p>
  2436. <p>This pattern must issue any memory barrier instructions such that the
  2437. pattern as a whole acts as an acquire barrier, that is all memory
  2438. operations after the pattern do not occur until the lock is acquired.
  2439. </p>
  2440. <p>If this pattern is not defined, the operation will be constructed from
  2441. a compare-and-swap operation, if defined.
  2442. </p>
  2443. <a name="index-sync_005flock_005freleasemode-instruction-pattern"></a>
  2444. </dd>
  2445. <dt>&lsquo;<samp>sync_lock_release<var>mode</var></samp>&rsquo;</dt>
  2446. <dd><p>This pattern, if defined, releases a lock set by
  2447. <code>sync_lock_test_and_set<var>mode</var></code>. Operand 0 is the memory
  2448. that contains the lock; operand 1 is the value to store in the lock.
  2449. </p>
  2450. <p>If the target doesn&rsquo;t implement full semantics for
  2451. <code>sync_lock_test_and_set<var>mode</var></code>, any value operand which is not
  2452. the constant 0 should be rejected with <code>FAIL</code>, and the true contents
  2453. of the memory operand are implementation defined.
  2454. </p>
  2455. <p>This pattern must issue any memory barrier instructions such that the
  2456. pattern as a whole acts as a release barrier, that is the lock is
  2457. released only after all previous memory operations have completed.
  2458. </p>
  2459. <p>If this pattern is not defined, then a <code>memory_barrier</code> pattern
  2460. will be emitted, followed by a store of the value to the memory operand.
  2461. </p>
  2462. <a name="index-atomic_005fcompare_005fand_005fswapmode-instruction-pattern"></a>
  2463. </dd>
  2464. <dt>&lsquo;<samp>atomic_compare_and_swap<var>mode</var></samp>&rsquo;</dt>
  2465. <dd><p>This pattern, if defined, emits code for an atomic compare-and-swap
  2466. operation with memory model semantics. Operand 2 is the memory on which
  2467. the atomic operation is performed. Operand 0 is an output operand which
  2468. is set to true or false based on whether the operation succeeded. Operand
  2469. 1 is an output operand which is set to the contents of the memory before
  2470. the operation was attempted. Operand 3 is the value that is expected to
  2471. be in memory. Operand 4 is the value to put in memory if the expected
  2472. value is found there. Operand 5 is set to 1 if this compare and swap is to
  2473. be treated as a weak operation. Operand 6 is the memory model to be used
  2474. if the operation is a success. Operand 7 is the memory model to be used
  2475. if the operation fails.
  2476. </p>
  2477. <p>If memory referred to in operand 2 contains the value in operand 3, then
  2478. operand 4 is stored in memory pointed to by operand 2 and fencing based on
  2479. the memory model in operand 6 is issued.
  2480. </p>
  2481. <p>If memory referred to in operand 2 does not contain the value in operand 3,
  2482. then fencing based on the memory model in operand 7 is issued.
  2483. </p>
  2484. <p>If a target does not support weak compare-and-swap operations, or the port
  2485. elects not to implement weak operations, the argument in operand 5 can be
  2486. ignored. Note a strong implementation must be provided.
  2487. </p>
  2488. <p>If this pattern is not provided, the <code>__atomic_compare_exchange</code>
  2489. built-in functions will utilize the legacy <code>sync_compare_and_swap</code>
  2490. pattern with an <code>__ATOMIC_SEQ_CST</code> memory model.
  2491. </p>
  2492. <a name="index-atomic_005floadmode-instruction-pattern"></a>
  2493. </dd>
  2494. <dt>&lsquo;<samp>atomic_load<var>mode</var></samp>&rsquo;</dt>
  2495. <dd><p>This pattern implements an atomic load operation with memory model
  2496. semantics. Operand 1 is the memory address being loaded from. Operand 0
  2497. is the result of the load. Operand 2 is the memory model to be used for
  2498. the load operation.
  2499. </p>
  2500. <p>If not present, the <code>__atomic_load</code> built-in function will either
  2501. resort to a normal load with memory barriers, or a compare-and-swap
  2502. operation if a normal load would not be atomic.
  2503. </p>
  2504. <a name="index-atomic_005fstoremode-instruction-pattern"></a>
  2505. </dd>
  2506. <dt>&lsquo;<samp>atomic_store<var>mode</var></samp>&rsquo;</dt>
  2507. <dd><p>This pattern implements an atomic store operation with memory model
  2508. semantics. Operand 0 is the memory address being stored to. Operand 1
  2509. is the value to be written. Operand 2 is the memory model to be used for
  2510. the operation.
  2511. </p>
  2512. <p>If not present, the <code>__atomic_store</code> built-in function will attempt to
  2513. perform a normal store and surround it with any required memory fences. If
  2514. the store would not be atomic, then an <code>__atomic_exchange</code> is
  2515. attempted with the result being ignored.
  2516. </p>
  2517. <a name="index-atomic_005fexchangemode-instruction-pattern"></a>
  2518. </dd>
  2519. <dt>&lsquo;<samp>atomic_exchange<var>mode</var></samp>&rsquo;</dt>
  2520. <dd><p>This pattern implements an atomic exchange operation with memory model
  2521. semantics. Operand 1 is the memory location the operation is performed on.
  2522. Operand 0 is an output operand which is set to the original value contained
  2523. in the memory pointed to by operand 1. Operand 2 is the value to be
  2524. stored. Operand 3 is the memory model to be used.
  2525. </p>
  2526. <p>If this pattern is not present, the built-in function
  2527. <code>__atomic_exchange</code> will attempt to preform the operation with a
  2528. compare and swap loop.
  2529. </p>
  2530. <a name="index-atomic_005faddmode-instruction-pattern"></a>
  2531. <a name="index-atomic_005fsubmode-instruction-pattern"></a>
  2532. <a name="index-atomic_005formode-instruction-pattern"></a>
  2533. <a name="index-atomic_005fandmode-instruction-pattern"></a>
  2534. <a name="index-atomic_005fxormode-instruction-pattern"></a>
  2535. <a name="index-atomic_005fnandmode-instruction-pattern"></a>
  2536. </dd>
  2537. <dt>&lsquo;<samp>atomic_add<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_sub<var>mode</var></samp>&rsquo;</dt>
  2538. <dt>&lsquo;<samp>atomic_or<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_and<var>mode</var></samp>&rsquo;</dt>
  2539. <dt>&lsquo;<samp>atomic_xor<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_nand<var>mode</var></samp>&rsquo;</dt>
  2540. <dd><p>These patterns emit code for an atomic operation on memory with memory
  2541. model semantics. Operand 0 is the memory on which the atomic operation is
  2542. performed. Operand 1 is the second operand to the binary operator.
  2543. Operand 2 is the memory model to be used by the operation.
  2544. </p>
  2545. <p>If these patterns are not defined, attempts will be made to use legacy
  2546. <code>sync</code> patterns, or equivalent patterns which return a result. If
  2547. none of these are available a compare-and-swap loop will be used.
  2548. </p>
  2549. <a name="index-atomic_005ffetch_005faddmode-instruction-pattern"></a>
  2550. <a name="index-atomic_005ffetch_005fsubmode-instruction-pattern"></a>
  2551. <a name="index-atomic_005ffetch_005formode-instruction-pattern"></a>
  2552. <a name="index-atomic_005ffetch_005fandmode-instruction-pattern"></a>
  2553. <a name="index-atomic_005ffetch_005fxormode-instruction-pattern"></a>
  2554. <a name="index-atomic_005ffetch_005fnandmode-instruction-pattern"></a>
  2555. </dd>
  2556. <dt>&lsquo;<samp>atomic_fetch_add<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_fetch_sub<var>mode</var></samp>&rsquo;</dt>
  2557. <dt>&lsquo;<samp>atomic_fetch_or<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_fetch_and<var>mode</var></samp>&rsquo;</dt>
  2558. <dt>&lsquo;<samp>atomic_fetch_xor<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_fetch_nand<var>mode</var></samp>&rsquo;</dt>
  2559. <dd><p>These patterns emit code for an atomic operation on memory with memory
  2560. model semantics, and return the original value. Operand 0 is an output
  2561. operand which contains the value of the memory location before the
  2562. operation was performed. Operand 1 is the memory on which the atomic
  2563. operation is performed. Operand 2 is the second operand to the binary
  2564. operator. Operand 3 is the memory model to be used by the operation.
  2565. </p>
  2566. <p>If these patterns are not defined, attempts will be made to use legacy
  2567. <code>sync</code> patterns. If none of these are available a compare-and-swap
  2568. loop will be used.
  2569. </p>
  2570. <a name="index-atomic_005fadd_005ffetchmode-instruction-pattern"></a>
  2571. <a name="index-atomic_005fsub_005ffetchmode-instruction-pattern"></a>
  2572. <a name="index-atomic_005for_005ffetchmode-instruction-pattern"></a>
  2573. <a name="index-atomic_005fand_005ffetchmode-instruction-pattern"></a>
  2574. <a name="index-atomic_005fxor_005ffetchmode-instruction-pattern"></a>
  2575. <a name="index-atomic_005fnand_005ffetchmode-instruction-pattern"></a>
  2576. </dd>
  2577. <dt>&lsquo;<samp>atomic_add_fetch<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_sub_fetch<var>mode</var></samp>&rsquo;</dt>
  2578. <dt>&lsquo;<samp>atomic_or_fetch<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_and_fetch<var>mode</var></samp>&rsquo;</dt>
  2579. <dt>&lsquo;<samp>atomic_xor_fetch<var>mode</var></samp>&rsquo;, &lsquo;<samp>atomic_nand_fetch<var>mode</var></samp>&rsquo;</dt>
  2580. <dd><p>These patterns emit code for an atomic operation on memory with memory
  2581. model semantics and return the result after the operation is performed.
  2582. Operand 0 is an output operand which contains the value after the
  2583. operation. Operand 1 is the memory on which the atomic operation is
  2584. performed. Operand 2 is the second operand to the binary operator.
  2585. Operand 3 is the memory model to be used by the operation.
  2586. </p>
  2587. <p>If these patterns are not defined, attempts will be made to use legacy
  2588. <code>sync</code> patterns, or equivalent patterns which return the result before
  2589. the operation followed by the arithmetic operation required to produce the
  2590. result. If none of these are available a compare-and-swap loop will be
  2591. used.
  2592. </p>
  2593. <a name="index-atomic_005ftest_005fand_005fset-instruction-pattern"></a>
  2594. </dd>
  2595. <dt>&lsquo;<samp>atomic_test_and_set</samp>&rsquo;</dt>
  2596. <dd><p>This pattern emits code for <code>__builtin_atomic_test_and_set</code>.
  2597. Operand 0 is an output operand which is set to true if the previous
  2598. previous contents of the byte was &quot;set&quot;, and false otherwise. Operand 1
  2599. is the <code>QImode</code> memory to be modified. Operand 2 is the memory
  2600. model to be used.
  2601. </p>
  2602. <p>The specific value that defines &quot;set&quot; is implementation defined, and
  2603. is normally based on what is performed by the native atomic test and set
  2604. instruction.
  2605. </p>
  2606. <a name="index-atomic_005fbit_005ftest_005fand_005fsetmode-instruction-pattern"></a>
  2607. <a name="index-atomic_005fbit_005ftest_005fand_005fcomplementmode-instruction-pattern"></a>
  2608. <a name="index-atomic_005fbit_005ftest_005fand_005fresetmode-instruction-pattern"></a>
  2609. </dd>
  2610. <dt>&lsquo;<samp>atomic_bit_test_and_set<var>mode</var></samp>&rsquo;</dt>
  2611. <dt>&lsquo;<samp>atomic_bit_test_and_complement<var>mode</var></samp>&rsquo;</dt>
  2612. <dt>&lsquo;<samp>atomic_bit_test_and_reset<var>mode</var></samp>&rsquo;</dt>
  2613. <dd><p>These patterns emit code for an atomic bitwise operation on memory with memory
  2614. model semantics, and return the original value of the specified bit.
  2615. Operand 0 is an output operand which contains the value of the specified bit
  2616. from the memory location before the operation was performed. Operand 1 is the
  2617. memory on which the atomic operation is performed. Operand 2 is the bit within
  2618. the operand, starting with least significant bit. Operand 3 is the memory model
  2619. to be used by the operation. Operand 4 is a flag - it is <code>const1_rtx</code>
  2620. if operand 0 should contain the original value of the specified bit in the
  2621. least significant bit of the operand, and <code>const0_rtx</code> if the bit should
  2622. be in its original position in the operand.
  2623. <code>atomic_bit_test_and_set<var>mode</var></code> atomically sets the specified bit after
  2624. remembering its original value, <code>atomic_bit_test_and_complement<var>mode</var></code>
  2625. inverts the specified bit and <code>atomic_bit_test_and_reset<var>mode</var></code> clears
  2626. the specified bit.
  2627. </p>
  2628. <p>If these patterns are not defined, attempts will be made to use
  2629. <code>atomic_fetch_or<var>mode</var></code>, <code>atomic_fetch_xor<var>mode</var></code> or
  2630. <code>atomic_fetch_and<var>mode</var></code> instruction patterns, or their <code>sync</code>
  2631. counterparts. If none of these are available a compare-and-swap
  2632. loop will be used.
  2633. </p>
  2634. <a name="index-mem_005fthread_005ffencemode-instruction-pattern"></a>
  2635. </dd>
  2636. <dt>&lsquo;<samp>mem_thread_fence<var>mode</var></samp>&rsquo;</dt>
  2637. <dd><p>This pattern emits code required to implement a thread fence with
  2638. memory model semantics. Operand 0 is the memory model to be used.
  2639. </p>
  2640. <p>If this pattern is not specified, all memory models except
  2641. <code>__ATOMIC_RELAXED</code> will result in issuing a <code>sync_synchronize</code>
  2642. barrier pattern.
  2643. </p>
  2644. <a name="index-mem_005fsignal_005ffencemode-instruction-pattern"></a>
  2645. </dd>
  2646. <dt>&lsquo;<samp>mem_signal_fence<var>mode</var></samp>&rsquo;</dt>
  2647. <dd><p>This pattern emits code required to implement a signal fence with
  2648. memory model semantics. Operand 0 is the memory model to be used.
  2649. </p>
  2650. <p>This pattern should impact the compiler optimizers the same way that
  2651. mem_signal_fence does, but it does not need to issue any barrier
  2652. instructions.
  2653. </p>
  2654. <p>If this pattern is not specified, all memory models except
  2655. <code>__ATOMIC_RELAXED</code> will result in issuing a <code>sync_synchronize</code>
  2656. barrier pattern.
  2657. </p>
  2658. <a name="index-get_005fthread_005fpointermode-instruction-pattern"></a>
  2659. <a name="index-set_005fthread_005fpointermode-instruction-pattern"></a>
  2660. </dd>
  2661. <dt>&lsquo;<samp>get_thread_pointer<var>mode</var></samp>&rsquo;</dt>
  2662. <dt>&lsquo;<samp>set_thread_pointer<var>mode</var></samp>&rsquo;</dt>
  2663. <dd><p>These patterns emit code that reads/sets the TLS thread pointer. Currently,
  2664. these are only needed if the target needs to support the
  2665. <code>__builtin_thread_pointer</code> and <code>__builtin_set_thread_pointer</code>
  2666. builtins.
  2667. </p>
  2668. <p>The get/set patterns have a single output/input operand respectively,
  2669. with <var>mode</var> intended to be <code>Pmode</code>.
  2670. </p>
  2671. <a name="index-stack_005fprotect_005fset-instruction-pattern"></a>
  2672. </dd>
  2673. <dt>&lsquo;<samp>stack_protect_set</samp>&rsquo;</dt>
  2674. <dd><p>This pattern, if defined, moves a <code>ptr_mode</code> value from the memory
  2675. in operand 1 to the memory in operand 0 without leaving the value in
  2676. a register afterward. This is to avoid leaking the value some place
  2677. that an attacker might use to rewrite the stack guard slot after
  2678. having clobbered it.
  2679. </p>
  2680. <p>If this pattern is not defined, then a plain move pattern is generated.
  2681. </p>
  2682. <a name="index-stack_005fprotect_005ftest-instruction-pattern"></a>
  2683. </dd>
  2684. <dt>&lsquo;<samp>stack_protect_test</samp>&rsquo;</dt>
  2685. <dd><p>This pattern, if defined, compares a <code>ptr_mode</code> value from the
  2686. memory in operand 1 with the memory in operand 0 without leaving the
  2687. value in a register afterward and branches to operand 2 if the values
  2688. were equal.
  2689. </p>
  2690. <p>If this pattern is not defined, then a plain compare pattern and
  2691. conditional branch pattern is used.
  2692. </p>
  2693. <a name="index-clear_005fcache-instruction-pattern"></a>
  2694. </dd>
  2695. <dt>&lsquo;<samp>clear_cache</samp>&rsquo;</dt>
  2696. <dd><p>This pattern, if defined, flushes the instruction cache for a region of
  2697. memory. The region is bounded to by the Pmode pointers in operand 0
  2698. inclusive and operand 1 exclusive.
  2699. </p>
  2700. <p>If this pattern is not defined, a call to the library function
  2701. <code>__clear_cache</code> is used.
  2702. </p>
  2703. </dd>
  2704. </dl>
  2705. <hr>
  2706. <div class="header">
  2707. <p>
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