Incdec.html 8.3 KB

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  62. <a name="Incdec"></a>
  63. <div class="header">
  64. <p>
  65. Next: <a href="Assembler.html#Assembler" accesskey="n" rel="next">Assembler</a>, Previous: <a href="Side-Effects.html#Side-Effects" accesskey="p" rel="prev">Side Effects</a>, Up: <a href="RTL.html#RTL" accesskey="u" rel="up">RTL</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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  68. <a name="Embedded-Side_002dEffects-on-Addresses"></a>
  69. <h3 class="section">13.16 Embedded Side-Effects on Addresses</h3>
  70. <a name="index-RTL-preincrement"></a>
  71. <a name="index-RTL-postincrement"></a>
  72. <a name="index-RTL-predecrement"></a>
  73. <a name="index-RTL-postdecrement"></a>
  74. <p>Six special side-effect expression codes appear as memory addresses.
  75. </p>
  76. <dl compact="compact">
  77. <dd><a name="index-pre_005fdec"></a>
  78. </dd>
  79. <dt><code>(pre_dec:<var>m</var> <var>x</var>)</code></dt>
  80. <dd><p>Represents the side effect of decrementing <var>x</var> by a standard
  81. amount and represents also the value that <var>x</var> has after being
  82. decremented. <var>x</var> must be a <code>reg</code> or <code>mem</code>, but most
  83. machines allow only a <code>reg</code>. <var>m</var> must be the machine mode
  84. for pointers on the machine in use. The amount <var>x</var> is decremented
  85. by is the length in bytes of the machine mode of the containing memory
  86. reference of which this expression serves as the address. Here is an
  87. example of its use:
  88. </p>
  89. <div class="smallexample">
  90. <pre class="smallexample">(mem:DF (pre_dec:SI (reg:SI 39)))
  91. </pre></div>
  92. <p>This says to decrement pseudo register 39 by the length of a <code>DFmode</code>
  93. value and use the result to address a <code>DFmode</code> value.
  94. </p>
  95. <a name="index-pre_005finc"></a>
  96. </dd>
  97. <dt><code>(pre_inc:<var>m</var> <var>x</var>)</code></dt>
  98. <dd><p>Similar, but specifies incrementing <var>x</var> instead of decrementing it.
  99. </p>
  100. <a name="index-post_005fdec"></a>
  101. </dd>
  102. <dt><code>(post_dec:<var>m</var> <var>x</var>)</code></dt>
  103. <dd><p>Represents the same side effect as <code>pre_dec</code> but a different
  104. value. The value represented here is the value <var>x</var> has <i>before</i>
  105. being decremented.
  106. </p>
  107. <a name="index-post_005finc"></a>
  108. </dd>
  109. <dt><code>(post_inc:<var>m</var> <var>x</var>)</code></dt>
  110. <dd><p>Similar, but specifies incrementing <var>x</var> instead of decrementing it.
  111. </p>
  112. <a name="index-post_005fmodify"></a>
  113. </dd>
  114. <dt><code>(post_modify:<var>m</var> <var>x</var> <var>y</var>)</code></dt>
  115. <dd>
  116. <p>Represents the side effect of setting <var>x</var> to <var>y</var> and
  117. represents <var>x</var> before <var>x</var> is modified. <var>x</var> must be a
  118. <code>reg</code> or <code>mem</code>, but most machines allow only a <code>reg</code>.
  119. <var>m</var> must be the machine mode for pointers on the machine in use.
  120. </p>
  121. <p>The expression <var>y</var> must be one of three forms:
  122. <code>(plus:<var>m</var> <var>x</var> <var>z</var>)</code>,
  123. <code>(minus:<var>m</var> <var>x</var> <var>z</var>)</code>, or
  124. <code>(plus:<var>m</var> <var>x</var> <var>i</var>)</code>,
  125. where <var>z</var> is an index register and <var>i</var> is a constant.
  126. </p>
  127. <p>Here is an example of its use:
  128. </p>
  129. <div class="smallexample">
  130. <pre class="smallexample">(mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42)
  131. (reg:SI 48))))
  132. </pre></div>
  133. <p>This says to modify pseudo register 42 by adding the contents of pseudo
  134. register 48 to it, after the use of what ever 42 points to.
  135. </p>
  136. <a name="index-pre_005fmodify"></a>
  137. </dd>
  138. <dt><code>(pre_modify:<var>m</var> <var>x</var> <var>expr</var>)</code></dt>
  139. <dd><p>Similar except side effects happen before the use.
  140. </p></dd>
  141. </dl>
  142. <p>These embedded side effect expressions must be used with care. Instruction
  143. patterns may not use them. Until the &lsquo;<samp>flow</samp>&rsquo; pass of the compiler,
  144. they may occur only to represent pushes onto the stack. The &lsquo;<samp>flow</samp>&rsquo;
  145. pass finds cases where registers are incremented or decremented in one
  146. instruction and used as an address shortly before or after; these cases are
  147. then transformed to use pre- or post-increment or -decrement.
  148. </p>
  149. <p>If a register used as the operand of these expressions is used in
  150. another address in an insn, the original value of the register is used.
  151. Uses of the register outside of an address are not permitted within the
  152. same insn as a use in an embedded side effect expression because such
  153. insns behave differently on different machines and hence must be treated
  154. as ambiguous and disallowed.
  155. </p>
  156. <p>An instruction that can be represented with an embedded side effect
  157. could also be represented using <code>parallel</code> containing an additional
  158. <code>set</code> to describe how the address register is altered. This is not
  159. done because machines that allow these operations at all typically
  160. allow them wherever a memory address is called for. Describing them as
  161. additional parallel stores would require doubling the number of entries
  162. in the machine description.
  163. </p>
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