huangmeng
/
Embedded_AI


			
							123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201
							<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<!-- Copyright (C) 1988-2017 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with the
Invariant Sections being "Funding Free Software", the Front-Cover
Texts being (a) (see below), and with the Back-Cover Texts being (b)
(see below).  A copy of the license is included in the section entitled
"GNU Free Documentation License".

(a) The FSF's Front-Cover Text is:

A GNU Manual

(b) The FSF's Back-Cover Text is:

You have freedom to copy and modify this GNU Manual, like GNU
     software.  Copies published by the Free Software Foundation raise
     funds for GNU development. -->
<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
<head>
<title>Using the GNU Compiler Collection (GCC): RISC-V Options</title>

<meta name="description" content="Using the GNU Compiler Collection (GCC): RISC-V Options">
<meta name="keywords" content="Using the GNU Compiler Collection (GCC): RISC-V Options">
<meta name="resource-type" content="document">
<meta name="distribution" content="global">
<meta name="Generator" content="makeinfo">
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
<link href="index.html#Top" rel="start" title="Top">
<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
<link href="RL78-Options.html#RL78-Options" rel="next" title="RL78 Options">
<link href="PowerPC-Options.html#PowerPC-Options" rel="prev" title="PowerPC Options">
<style type="text/css">
<!--
a.summary-letter {text-decoration: none}
blockquote.smallquotation {font-size: smaller}
div.display {margin-left: 3.2em}
div.example {margin-left: 3.2em}
div.indentedblock {margin-left: 3.2em}
div.lisp {margin-left: 3.2em}
div.smalldisplay {margin-left: 3.2em}
div.smallexample {margin-left: 3.2em}
div.smallindentedblock {margin-left: 3.2em; font-size: smaller}
div.smalllisp {margin-left: 3.2em}
kbd {font-style:oblique}
pre.display {font-family: inherit}
pre.format {font-family: inherit}
pre.menu-comment {font-family: serif}
pre.menu-preformatted {font-family: serif}
pre.smalldisplay {font-family: inherit; font-size: smaller}
pre.smallexample {font-size: smaller}
pre.smallformat {font-family: inherit; font-size: smaller}
pre.smalllisp {font-size: smaller}
span.nocodebreak {white-space:nowrap}
span.nolinebreak {white-space:nowrap}
span.roman {font-family:serif; font-weight:normal}
span.sansserif {font-family:sans-serif; font-weight:normal}
ul.no-bullet {list-style: none}
-->
</style>


</head>

<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
<a name="RISC_002dV-Options"></a>
<div class="header">
<p>
Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PowerPC-Options.html#PowerPC-Options" accesskey="p" rel="prev">PowerPC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="RISC_002dV-Options-1"></a>
<h4 class="subsection">3.18.37 RISC-V Options</h4>
<a name="index-RISC_002dV-Options"></a>

<p>These command-line options are defined for RISC-V targets:
</p>
<dl compact="compact">
<dt><code>-mbranch-cost=<var>n</var></code></dt>
<dd><a name="index-mbranch_002dcost-3"></a>
<p>Set the cost of branches to roughly <var>n</var> instructions.
</p>
</dd>
<dt><code>-mplt</code></dt>
<dt><code>-mno-plt</code></dt>
<dd><a name="index-plt"></a>
<p>When generating PIC code, do or don&rsquo;t allow the use of PLTs. Ignored for
non-PIC.  The default is <samp>-mplt</samp>.
</p>
</dd>
<dt><code>-mabi=<var>ABI-string</var></code></dt>
<dd><a name="index-mabi-2"></a>
<p>Specify integer and floating-point calling convention.  <var>ABI-string</var>
contains two parts: the size of integer types and the registers used for
floating-point types.  For example &lsquo;<samp>-march=rv64ifd -mabi=lp64d</samp>&rsquo; means that
&lsquo;<samp>long</samp>&rsquo; and pointers are 64-bit (implicitly defining &lsquo;<samp>int</samp>&rsquo; to be
32-bit), and that floating-point values up to 64 bits wide are passed in F
registers.  Contrast this with &lsquo;<samp>-march=rv64ifd -mabi=lp64f</samp>&rsquo;, which still
allows the compiler to generate code that uses the F and D extensions but only
allows floating-point values up to 32 bits long to be passed in registers; or
&lsquo;<samp>-march=rv64ifd -mabi=lp64</samp>&rsquo;, in which no floating-point arguments will be
passed in registers.
</p>
<p>The default for this argument is system dependent, users who want a specific
calling convention should specify one explicitly.  The valid calling
conventions are: &lsquo;<samp>ilp32</samp>&rsquo;, &lsquo;<samp>ilp32f</samp>&rsquo;, &lsquo;<samp>ilp32d</samp>&rsquo;, &lsquo;<samp>lp64</samp>&rsquo;,
&lsquo;<samp>lp64f</samp>&rsquo;, and &lsquo;<samp>lp64d</samp>&rsquo;.  Some calling conventions are impossible to
implement on some ISAs: for example, &lsquo;<samp>-march=rv32if -mabi=ilp32d</samp>&rsquo; is
invalid because the ABI requires 64-bit values be passed in F registers, but F
registers are only 32 bits wide.
</p>
</dd>
<dt><code>-mfdiv</code></dt>
<dt><code>-mno-fdiv</code></dt>
<dd><a name="index-mfdiv"></a>
<p>Do or don&rsquo;t use hardware floating-point divide and square root instructions.
This requires the F or D extensions for floating-point registers.  The default
is to use them if the specified architecture has these instructions.
</p>
</dd>
<dt><code>-mdiv</code></dt>
<dt><code>-mno-div</code></dt>
<dd><a name="index-mdiv-3"></a>
<p>Do or don&rsquo;t use hardware instructions for integer division.  This requires the
M extension.  The default is to use them if the specified architecture has
these instructions.
</p>
</dd>
<dt><code>-march=<var>ISA-string</var></code></dt>
<dd><a name="index-march-10"></a>
<p>Generate code for given RISC-V ISA (e.g.&nbsp;&lsquo;<samp>rv64im</samp>&rsquo;).  ISA strings must be
lower-case.  Examples include &lsquo;<samp>rv64i</samp>&rsquo;, &lsquo;<samp>rv32g</samp>&rsquo;, and &lsquo;<samp>rv32imaf</samp>&rsquo;.
</p>
</dd>
<dt><code>-mtune=<var>processor-string</var></code></dt>
<dd><a name="index-mtune-10"></a>
<p>Optimize the output for the given processor, specified by microarchitecture
name.
</p>
</dd>
<dt><code>-msmall-data-limit=<var>n</var></code></dt>
<dd><a name="index-msmall_002ddata_002dlimit"></a>
<p>Put global and static data smaller than <var>n</var> bytes into a special section
(on some targets).
</p>
</dd>
<dt><code>-msave-restore</code></dt>
<dt><code>-mno-save-restore</code></dt>
<dd><a name="index-msave_002drestore"></a>
<p>Do or don&rsquo;t use smaller but slower prologue and epilogue code that uses
library function calls.  The default is to use fast inline prologues and
epilogues.
</p>
</dd>
<dt><code>-mstrict-align</code></dt>
<dt><code>-mno-strict-align</code></dt>
<dd><a name="index-mstrict_002dalign-2"></a>
<p>Do not or do generate unaligned memory accesses.  The default is set depending
on whether the processor we are optimizing for supports fast unaligned access
or not.
</p>
</dd>
<dt><code>-mcmodel=medlow</code></dt>
<dd><a name="index-mcmodel_003dmedlow"></a>
<p>Generate code for the medium-low code model. The program and its statically
defined symbols must lie within a single 2 GiB address range and must lie
between absolute addresses -2 GiB and +2 GiB. Programs can be
statically or dynamically linked. This is the default code model.
</p>
</dd>
<dt><code>-mcmodel=medany</code></dt>
<dd><a name="index-mcmodel_003dmedany"></a>
<p>Generate code for the medium-any code model. The program and its statically
defined symbols must be within any single 2 GiB address range. Programs can be
statically or dynamically linked.
</p>
</dd>
<dt><code>-mexplicit-relocs</code></dt>
<dt><code>-mno-exlicit-relocs</code></dt>
<dd><p>Use or do not use assembler relocation operators when dealing with symbolic
addresses.  The alternative is to use assembler macros instead, which may
limit optimization.
</p>
</dd>
</dl>

<hr>
<div class="header">
<p>
Next: <a href="RL78-Options.html#RL78-Options" accesskey="n" rel="next">RL78 Options</a>, Previous: <a href="PowerPC-Options.html#PowerPC-Options" accesskey="p" rel="prev">PowerPC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
</div>


</body>
</html>