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<title>Using the GNU Compiler Collection (GCC): PowerPC Built-in Functions</title>

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<a name="PowerPC-Built_002din-Functions"></a>
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<p>
Next: <a href="PowerPC-AltiVec_002fVSX-Built_002din-Functions.html#PowerPC-AltiVec_002fVSX-Built_002din-Functions" accesskey="n" rel="next">PowerPC AltiVec/VSX Built-in Functions</a>, Previous: <a href="picoChip-Built_002din-Functions.html#picoChip-Built_002din-Functions" accesskey="p" rel="prev">picoChip Built-in Functions</a>, Up: <a href="Target-Builtins.html#Target-Builtins" accesskey="u" rel="up">Target Builtins</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="PowerPC-Built_002din-Functions-1"></a>
<h4 class="subsection">6.60.21 PowerPC Built-in Functions</h4>

<p>The following built-in functions are always available and can be used to
check the PowerPC target platform type:
</p>
<dl>
<dt><a name="index-_005f_005fbuiltin_005fcpu_005finit"></a>Built-in Function: <em>void</em> <strong>__builtin_cpu_init</strong> <em>(void)</em></dt>
<dd><p>This function is a <code>nop</code> on the PowerPC platform and is included solely
to maintain API compatibility with the x86 builtins.
</p></dd></dl>

<dl>
<dt><a name="index-_005f_005fbuiltin_005fcpu_005finit-1"></a>Built-in Function: <em>void</em> <strong>__builtin_cpu_init</strong> <em>(void)</em></dt>
<dd><p>This function is a <code>nop</code> on the PowerPC platform and is included solely
to maintain API compatibility with the x86 builtins.
</p></dd></dl>

<dl>
<dt><a name="index-_005f_005fbuiltin_005fcpu_005fis"></a>Built-in Function: <em>int</em> <strong>__builtin_cpu_is</strong> <em>(const char *<var>cpuname</var>)</em></dt>
<dd><p>This function returns a value of <code>1</code> if the run-time CPU is of type
<var>cpuname</var> and returns <code>0</code> otherwise
</p>
<p>The <code>__builtin_cpu_is</code> function requires GLIBC 2.23 or newer
which exports the hardware capability bits.  GCC defines the macro
<code>__BUILTIN_CPU_SUPPORTS__</code> if the <code>__builtin_cpu_supports</code>
built-in function is fully supported.
</p>
<p>If GCC was configured to use a GLIBC before 2.23, the built-in
function <code>__builtin_cpu_is</code> always returns a 0 and the compiler
issues a warning.
</p>
<p>The following CPU names can be detected:
</p>
<dl compact="compact">
<dt>&lsquo;<samp>power9</samp>&rsquo;</dt>
<dd><p>IBM POWER9 Server CPU.
</p></dd>
<dt>&lsquo;<samp>power8</samp>&rsquo;</dt>
<dd><p>IBM POWER8 Server CPU.
</p></dd>
<dt>&lsquo;<samp>power7</samp>&rsquo;</dt>
<dd><p>IBM POWER7 Server CPU.
</p></dd>
<dt>&lsquo;<samp>power6x</samp>&rsquo;</dt>
<dd><p>IBM POWER6 Server CPU (RAW mode).
</p></dd>
<dt>&lsquo;<samp>power6</samp>&rsquo;</dt>
<dd><p>IBM POWER6 Server CPU (Architected mode).
</p></dd>
<dt>&lsquo;<samp>power5+</samp>&rsquo;</dt>
<dd><p>IBM POWER5+ Server CPU.
</p></dd>
<dt>&lsquo;<samp>power5</samp>&rsquo;</dt>
<dd><p>IBM POWER5 Server CPU.
</p></dd>
<dt>&lsquo;<samp>ppc970</samp>&rsquo;</dt>
<dd><p>IBM 970 Server CPU (ie, Apple G5).
</p></dd>
<dt>&lsquo;<samp>power4</samp>&rsquo;</dt>
<dd><p>IBM POWER4 Server CPU.
</p></dd>
<dt>&lsquo;<samp>ppca2</samp>&rsquo;</dt>
<dd><p>IBM A2 64-bit Embedded CPU
</p></dd>
<dt>&lsquo;<samp>ppc476</samp>&rsquo;</dt>
<dd><p>IBM PowerPC 476FP 32-bit Embedded CPU.
</p></dd>
<dt>&lsquo;<samp>ppc464</samp>&rsquo;</dt>
<dd><p>IBM PowerPC 464 32-bit Embedded CPU.
</p></dd>
<dt>&lsquo;<samp>ppc440</samp>&rsquo;</dt>
<dd><p>PowerPC 440 32-bit Embedded CPU.
</p></dd>
<dt>&lsquo;<samp>ppc405</samp>&rsquo;</dt>
<dd><p>PowerPC 405 32-bit Embedded CPU.
</p></dd>
<dt>&lsquo;<samp>ppc-cell-be</samp>&rsquo;</dt>
<dd><p>IBM PowerPC Cell Broadband Engine Architecture CPU.
</p></dd>
</dl>

<p>Here is an example:
</p><div class="smallexample">
<pre class="smallexample">#ifdef __BUILTIN_CPU_SUPPORTS__
  if (__builtin_cpu_is (&quot;power8&quot;))
    {
       do_power8 (); // POWER8 specific implementation.
    }
  else
#endif
    {
       do_generic (); // Generic implementation.
    }
</pre></div>
</dd></dl>

<dl>
<dt><a name="index-_005f_005fbuiltin_005fcpu_005fsupports"></a>Built-in Function: <em>int</em> <strong>__builtin_cpu_supports</strong> <em>(const char *<var>feature</var>)</em></dt>
<dd><p>This function returns a value of <code>1</code> if the run-time CPU supports the HWCAP
feature <var>feature</var> and returns <code>0</code> otherwise.
</p>
<p>The <code>__builtin_cpu_supports</code> function requires GLIBC 2.23 or
newer which exports the hardware capability bits.  GCC defines the
macro <code>__BUILTIN_CPU_SUPPORTS__</code> if the
<code>__builtin_cpu_supports</code> built-in function is fully supported.
</p>
<p>If GCC was configured to use a GLIBC before 2.23, the built-in
function <code>__builtin_cpu_suports</code> always returns a 0 and the
compiler issues a warning.
</p>
<p>The following features can be
detected:
</p>
<dl compact="compact">
<dt>&lsquo;<samp>4xxmac</samp>&rsquo;</dt>
<dd><p>4xx CPU has a Multiply Accumulator.
</p></dd>
<dt>&lsquo;<samp>altivec</samp>&rsquo;</dt>
<dd><p>CPU has a SIMD/Vector Unit.
</p></dd>
<dt>&lsquo;<samp>arch_2_05</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.05 (eg, POWER6)
</p></dd>
<dt>&lsquo;<samp>arch_2_06</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.06 (eg, POWER7)
</p></dd>
<dt>&lsquo;<samp>arch_2_07</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.07 (eg, POWER8)
</p></dd>
<dt>&lsquo;<samp>arch_3_00</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 3.0 (eg, POWER9)
</p></dd>
<dt>&lsquo;<samp>archpmu</samp>&rsquo;</dt>
<dd><p>CPU supports the set of compatible performance monitoring events.
</p></dd>
<dt>&lsquo;<samp>booke</samp>&rsquo;</dt>
<dd><p>CPU supports the Embedded ISA category.
</p></dd>
<dt>&lsquo;<samp>cellbe</samp>&rsquo;</dt>
<dd><p>CPU has a CELL broadband engine.
</p></dd>
<dt>&lsquo;<samp>dfp</samp>&rsquo;</dt>
<dd><p>CPU has a decimal floating point unit.
</p></dd>
<dt>&lsquo;<samp>dscr</samp>&rsquo;</dt>
<dd><p>CPU supports the data stream control register.
</p></dd>
<dt>&lsquo;<samp>ebb</samp>&rsquo;</dt>
<dd><p>CPU supports event base branching.
</p></dd>
<dt>&lsquo;<samp>efpdouble</samp>&rsquo;</dt>
<dd><p>CPU has a SPE double precision floating point unit.
</p></dd>
<dt>&lsquo;<samp>efpsingle</samp>&rsquo;</dt>
<dd><p>CPU has a SPE single precision floating point unit.
</p></dd>
<dt>&lsquo;<samp>fpu</samp>&rsquo;</dt>
<dd><p>CPU has a floating point unit.
</p></dd>
<dt>&lsquo;<samp>htm</samp>&rsquo;</dt>
<dd><p>CPU has hardware transaction memory instructions.
</p></dd>
<dt>&lsquo;<samp>htm-nosc</samp>&rsquo;</dt>
<dd><p>Kernel aborts hardware transactions when a syscall is made.
</p></dd>
<dt>&lsquo;<samp>ic_snoop</samp>&rsquo;</dt>
<dd><p>CPU supports icache snooping capabilities.
</p></dd>
<dt>&lsquo;<samp>ieee128</samp>&rsquo;</dt>
<dd><p>CPU supports 128-bit IEEE binary floating point instructions.
</p></dd>
<dt>&lsquo;<samp>isel</samp>&rsquo;</dt>
<dd><p>CPU supports the integer select instruction.
</p></dd>
<dt>&lsquo;<samp>mmu</samp>&rsquo;</dt>
<dd><p>CPU has a memory management unit.
</p></dd>
<dt>&lsquo;<samp>notb</samp>&rsquo;</dt>
<dd><p>CPU does not have a timebase (eg, 601 and 403gx).
</p></dd>
<dt>&lsquo;<samp>pa6t</samp>&rsquo;</dt>
<dd><p>CPU supports the PA Semi 6T CORE ISA.
</p></dd>
<dt>&lsquo;<samp>power4</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.00 (eg, POWER4)
</p></dd>
<dt>&lsquo;<samp>power5</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.02 (eg, POWER5)
</p></dd>
<dt>&lsquo;<samp>power5+</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.03 (eg, POWER5+)
</p></dd>
<dt>&lsquo;<samp>power6x</samp>&rsquo;</dt>
<dd><p>CPU supports ISA 2.05 (eg, POWER6) extended opcodes mffgpr and mftgpr.
</p></dd>
<dt>&lsquo;<samp>ppc32</samp>&rsquo;</dt>
<dd><p>CPU supports 32-bit mode execution.
</p></dd>
<dt>&lsquo;<samp>ppc601</samp>&rsquo;</dt>
<dd><p>CPU supports the old POWER ISA (eg, 601)
</p></dd>
<dt>&lsquo;<samp>ppc64</samp>&rsquo;</dt>
<dd><p>CPU supports 64-bit mode execution.
</p></dd>
<dt>&lsquo;<samp>ppcle</samp>&rsquo;</dt>
<dd><p>CPU supports a little-endian mode that uses address swizzling.
</p></dd>
<dt>&lsquo;<samp>smt</samp>&rsquo;</dt>
<dd><p>CPU support simultaneous multi-threading.
</p></dd>
<dt>&lsquo;<samp>spe</samp>&rsquo;</dt>
<dd><p>CPU has a signal processing extension unit.
</p></dd>
<dt>&lsquo;<samp>tar</samp>&rsquo;</dt>
<dd><p>CPU supports the target address register.
</p></dd>
<dt>&lsquo;<samp>true_le</samp>&rsquo;</dt>
<dd><p>CPU supports true little-endian mode.
</p></dd>
<dt>&lsquo;<samp>ucache</samp>&rsquo;</dt>
<dd><p>CPU has unified I/D cache.
</p></dd>
<dt>&lsquo;<samp>vcrypto</samp>&rsquo;</dt>
<dd><p>CPU supports the vector cryptography instructions.
</p></dd>
<dt>&lsquo;<samp>vsx</samp>&rsquo;</dt>
<dd><p>CPU supports the vector-scalar extension.
</p></dd>
</dl>

<p>Here is an example:
</p><div class="smallexample">
<pre class="smallexample">#ifdef __BUILTIN_CPU_SUPPORTS__
  if (__builtin_cpu_supports (&quot;fpu&quot;))
    {
       asm(&quot;fadd %0,%1,%2&quot; : &quot;=d&quot;(dst) : &quot;d&quot;(src1), &quot;d&quot;(src2));
    }
  else
#endif
    {
       dst = __fadd (src1, src2); // Software FP addition function.
    }
</pre></div>
</dd></dl>

<p>These built-in functions are available for the PowerPC family of
processors:
</p><div class="smallexample">
<pre class="smallexample">float __builtin_recipdivf (float, float);
float __builtin_rsqrtf (float);
double __builtin_recipdiv (double, double);
double __builtin_rsqrt (double);
uint64_t __builtin_ppc_get_timebase ();
unsigned long __builtin_ppc_mftb ();
double __builtin_unpack_longdouble (long double, int);
long double __builtin_pack_longdouble (double, double);
</pre></div>

<p>The <code>vec_rsqrt</code>, <code>__builtin_rsqrt</code>, and
<code>__builtin_rsqrtf</code> functions generate multiple instructions to
implement the reciprocal sqrt functionality using reciprocal sqrt
estimate instructions.
</p>
<p>The <code>__builtin_recipdiv</code>, and <code>__builtin_recipdivf</code>
functions generate multiple instructions to implement division using
the reciprocal estimate instructions.
</p>
<p>The <code>__builtin_ppc_get_timebase</code> and <code>__builtin_ppc_mftb</code>
functions generate instructions to read the Time Base Register.  The
<code>__builtin_ppc_get_timebase</code> function may generate multiple
instructions and always returns the 64 bits of the Time Base Register.
The <code>__builtin_ppc_mftb</code> function always generates one instruction and
returns the Time Base Register value as an unsigned long, throwing away
the most significant word on 32-bit environments.
</p>
<p>Additional built-in functions are available for the 64-bit PowerPC
family of processors, for efficient use of 128-bit floating point
(<code>__float128</code>) values.
</p>
<p>The following floating-point built-in functions are available with
<code>-mfloat128</code> and Altivec support.  All of them implement the
function that is part of the name.
</p>
<div class="smallexample">
<pre class="smallexample">__float128 __builtin_fabsq (__float128)
__float128 __builtin_copysignq (__float128, __float128)
</pre></div>

<p>The following built-in functions are available with <code>-mfloat128</code>
and Altivec support.
</p>
<dl compact="compact">
<dt><code>__float128 __builtin_infq (void)</code></dt>
<dd><p>Similar to <code>__builtin_inf</code>, except the return type is <code>__float128</code>.
<a name="index-_005f_005fbuiltin_005finfq"></a>
</p>
</dd>
<dt><code>__float128 __builtin_huge_valq (void)</code></dt>
<dd><p>Similar to <code>__builtin_huge_val</code>, except the return type is <code>__float128</code>.
<a name="index-_005f_005fbuiltin_005fhuge_005fvalq"></a>
</p>
</dd>
<dt><code>__float128 __builtin_nanq (void)</code></dt>
<dd><p>Similar to <code>__builtin_nan</code>, except the return type is <code>__float128</code>.
<a name="index-_005f_005fbuiltin_005fnanq"></a>
</p>
</dd>
<dt><code>__float128 __builtin_nansq (void)</code></dt>
<dd><p>Similar to <code>__builtin_nans</code>, except the return type is <code>__float128</code>.
<a name="index-_005f_005fbuiltin_005fnansq"></a>
</p></dd>
</dl>

<p>The following built-in functions are available for the PowerPC family
of processors, starting with ISA 2.06 or later (<samp>-mcpu=power7</samp>
or <samp>-mpopcntd</samp>):
</p><div class="smallexample">
<pre class="smallexample">long __builtin_bpermd (long, long);
int __builtin_divwe (int, int);
unsigned int __builtin_divweu (unsigned int, unsigned int);
long __builtin_divde (long, long);
unsigned long __builtin_divdeu (unsigned long, unsigned long);
unsigned int cdtbcd (unsigned int);
unsigned int cbcdtd (unsigned int);
unsigned int addg6s (unsigned int, unsigned int);
</pre></div>

<p>The <code>__builtin_divde</code> and <code>__builtin_divdeu</code> functions
require a 64-bit environment supporting ISA 2.06 or later.
</p>
<p>The following built-in functions are available for the PowerPC family
of processors, starting with ISA 3.0 or later (<samp>-mcpu=power9</samp>):
</p><div class="smallexample">
<pre class="smallexample">long long __builtin_darn (void);
long long __builtin_darn_raw (void);
int __builtin_darn_32 (void);

unsigned int scalar_extract_exp (double source);
unsigned long long int scalar_extract_sig (double source);

double
scalar_insert_exp (unsigned long long int significand, unsigned long long int exponent);
double
scalar_insert_exp (double significand, unsigned long long int exponent);

int scalar_cmp_exp_gt (double arg1, double arg2);
int scalar_cmp_exp_lt (double arg1, double arg2);
int scalar_cmp_exp_eq (double arg1, double arg2);
int scalar_cmp_exp_unordered (double arg1, double arg2);

bool scalar_test_data_class (float source, const int condition);
bool scalar_test_data_class (double source, const int condition);

bool scalar_test_neg (float source);
bool scalar_test_neg (double source);

int __builtin_byte_in_set (unsigned char u, unsigned long long set);
int __builtin_byte_in_range (unsigned char u, unsigned int range);
int __builtin_byte_in_either_range (unsigned char u, unsigned int ranges);

int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_lt (unsigned int comparison, _Decimal128 value);
int __builtin_dfp_dtstsfi_lt_dd (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_lt_td (unsigned int comparison, _Decimal128 value);

int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_gt (unsigned int comparison, _Decimal128 value);
int __builtin_dfp_dtstsfi_gt_dd (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_gt_td (unsigned int comparison, _Decimal128 value);

int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_eq (unsigned int comparison, _Decimal128 value);
int __builtin_dfp_dtstsfi_eq_dd (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_eq_td (unsigned int comparison, _Decimal128 value);

int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_ov (unsigned int comparison, _Decimal128 value);
int __builtin_dfp_dtstsfi_ov_dd (unsigned int comparison, _Decimal64 value);
int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value);
</pre></div>

<p>The <code>__builtin_darn</code> and <code>__builtin_darn_raw</code>
functions require a
64-bit environment supporting ISA 3.0 or later.
The <code>__builtin_darn</code> function provides a 64-bit conditioned
random number.  The <code>__builtin_darn_raw</code> function provides a
64-bit raw random number.  The <code>__builtin_darn_32</code> function
provides a 32-bit random number.
</p>
<p>The <code>scalar_extract_exp</code> and <code>scalar_extract_sig</code>
functions require a 64-bit environment supporting ISA 3.0 or later.
The <code>scalar_extract_exp</code> and <code>scalar_extract_sig</code> built-in
functions return the significand and the biased exponent value
respectively of their <code>source</code> arguments.
Within the result returned by <code>scalar_extract_sig</code>,
the <code>0x10000000000000</code> bit is set if the
function&rsquo;s <code>source</code> argument is in normalized form.
Otherwise, this bit is set to 0.
Note that the sign of the significand is not represented in the result
returned from the <code>scalar_extract_sig</code> function.  Use the
<code>scalar_test_neg</code> function to test the sign of its <code>double</code>
argument.
</p>
<p>The <code>scalar_insert_exp</code> 
function requires a 64-bit environment supporting ISA 3.0 or later.
The <code>scalar_insert_exp</code> built-in function returns a double-precision
floating point value that is constructed by assembling the values of its
<code>significand</code> and <code>exponent</code> arguments.  The sign of the
result is copied from the most significant bit of the
<code>significand</code> argument.  The significand and exponent components
of the result are composed of the least significant 11 bits of the
<code>exponent</code> argument and the least significant 52 bits of the
<code>significand</code> argument.
</p>
<p>The <code>scalar_cmp_exp_gt</code>, <code>scalar_cmp_exp_lt</code>,
<code>scalar_cmp_exp_eq</code>, and <code>scalar_cmp_exp_unordered</code> built-in
functions return a non-zero value if <code>arg1</code> is greater than, less
than, equal to, or not comparable to <code>arg2</code> respectively.  The
arguments are not comparable if one or the other equals NaN (not a
number). 
</p>
<p>The <code>scalar_test_data_class</code> built-in function returns 1
if any of the condition tests enabled by the value of the
<code>condition</code> variable are true, and 0 otherwise.  The
<code>condition</code> argument must be a compile-time constant integer with
value not exceeding 127.  The
<code>condition</code> argument is encoded as a bitmask with each bit
enabling the testing of a different condition, as characterized by the
following:
</p><div class="smallexample">
<pre class="smallexample">0x40    Test for NaN
0x20    Test for +Infinity
0x10    Test for -Infinity
0x08    Test for +Zero
0x04    Test for -Zero
0x02    Test for +Denormal
0x01    Test for -Denormal
</pre></div>

<p>The <code>scalar_test_neg</code> built-in function returns 1 if its
<code>source</code> argument holds a negative value, 0 otherwise.
</p>
<p>The <code>__builtin_byte_in_set</code> function requires a
64-bit environment supporting ISA 3.0 or later.  This function returns
a non-zero value if and only if its <code>u</code> argument exactly equals one of
the eight bytes contained within its 64-bit <code>set</code> argument.
</p>
<p>The <code>__builtin_byte_in_range</code> and
<code>__builtin_byte_in_either_range</code> require an environment
supporting ISA 3.0 or later.  For these two functions, the
<code>range</code> argument is encoded as 4 bytes, organized as
<code>hi_1:lo_1:hi_2:lo_2</code>.
The <code>__builtin_byte_in_range</code> function returns a
non-zero value if and only if its <code>u</code> argument is within the
range bounded between <code>lo_2</code> and <code>hi_2</code> inclusive.
The <code>__builtin_byte_in_either_range</code> function returns non-zero if
and only if its <code>u</code> argument is within either the range bounded
between <code>lo_1</code> and <code>hi_1</code> inclusive or the range bounded
between <code>lo_2</code> and <code>hi_2</code> inclusive.
</p>
<p>The <code>__builtin_dfp_dtstsfi_lt</code> function returns a non-zero value
if and only if the number of signficant digits of its <code>value</code> argument
is less than its <code>comparison</code> argument.  The
<code>__builtin_dfp_dtstsfi_lt_dd</code> and
<code>__builtin_dfp_dtstsfi_lt_td</code> functions behave similarly, but
require that the type of the <code>value</code> argument be
<code>__Decimal64</code> and <code>__Decimal128</code> respectively.
</p>
<p>The <code>__builtin_dfp_dtstsfi_gt</code> function returns a non-zero value
if and only if the number of signficant digits of its <code>value</code> argument
is greater than its <code>comparison</code> argument.  The
<code>__builtin_dfp_dtstsfi_gt_dd</code> and
<code>__builtin_dfp_dtstsfi_gt_td</code> functions behave similarly, but
require that the type of the <code>value</code> argument be
<code>__Decimal64</code> and <code>__Decimal128</code> respectively.
</p>
<p>The <code>__builtin_dfp_dtstsfi_eq</code> function returns a non-zero value
if and only if the number of signficant digits of its <code>value</code> argument
equals its <code>comparison</code> argument.  The
<code>__builtin_dfp_dtstsfi_eq_dd</code> and
<code>__builtin_dfp_dtstsfi_eq_td</code> functions behave similarly, but
require that the type of the <code>value</code> argument be
<code>__Decimal64</code> and <code>__Decimal128</code> respectively.
</p>
<p>The <code>__builtin_dfp_dtstsfi_ov</code> function returns a non-zero value
if and only if its <code>value</code> argument has an undefined number of
significant digits, such as when <code>value</code> is an encoding of <code>NaN</code>.
The <code>__builtin_dfp_dtstsfi_ov_dd</code> and
<code>__builtin_dfp_dtstsfi_ov_td</code> functions behave similarly, but
require that the type of the <code>value</code> argument be
<code>__Decimal64</code> and <code>__Decimal128</code> respectively.
</p>
<p>The following built-in functions are also available for the PowerPC family
of processors, starting with ISA 3.0 or later
(<samp>-mcpu=power9</samp>).  These string functions are described
separately in order to group the descriptions closer to the function
prototypes:
</p><div class="smallexample">
<pre class="smallexample">int vec_all_nez (vector signed char, vector signed char);
int vec_all_nez (vector unsigned char, vector unsigned char);
int vec_all_nez (vector signed short, vector signed short);
int vec_all_nez (vector unsigned short, vector unsigned short);
int vec_all_nez (vector signed int, vector signed int);
int vec_all_nez (vector unsigned int, vector unsigned int);

int vec_any_eqz (vector signed char, vector signed char);
int vec_any_eqz (vector unsigned char, vector unsigned char);
int vec_any_eqz (vector signed short, vector signed short);
int vec_any_eqz (vector unsigned short, vector unsigned short);
int vec_any_eqz (vector signed int, vector signed int);
int vec_any_eqz (vector unsigned int, vector unsigned int);

vector bool char vec_cmpnez (vector signed char arg1, vector signed char arg2);
vector bool char vec_cmpnez (vector unsigned char arg1, vector unsigned char arg2);
vector bool short vec_cmpnez (vector signed short arg1, vector signed short arg2);
vector bool short vec_cmpnez (vector unsigned short arg1, vector unsigned short arg2);
vector bool int vec_cmpnez (vector signed int arg1, vector signed int arg2);
vector bool int vec_cmpnez (vector unsigned int, vector unsigned int);

signed int vec_cntlz_lsbb (vector signed char);
signed int vec_cntlz_lsbb (vector unsigned char);

signed int vec_cnttz_lsbb (vector signed char);
signed int vec_cnttz_lsbb (vector unsigned char);

vector signed char vec_xl_len (signed char *addr, size_t len);
vector unsigned char vec_xl_len (unsigned char *addr, size_t len);
vector signed int vec_xl_len (signed int *addr, size_t len);
vector unsigned int vec_xl_len (unsigned int *addr, size_t len);
vector signed __int128 vec_xl_len (signed __int128 *addr, size_t len);
vector unsigned __int128 vec_xl_len (unsigned __int128 *addr, size_t len);
vector signed long long vec_xl_len (signed long long *addr, size_t len);
vector unsigned long long vec_xl_len (unsigned long long *addr, size_t len);
vector signed short vec_xl_len (signed short *addr, size_t len);
vector unsigned short vec_xl_len (unsigned short *addr, size_t len);
vector double vec_xl_len (double *addr, size_t len);
vector float vec_xl_len (float *addr, size_t len);

void vec_xst_len (vector signed char data, signed char *addr, size_t len);
void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);
void vec_xst_len (vector signed int data, signed int *addr, size_t len);
void vec_xst_len (vector unsigned int data, unsigned int *addr, size_t len);
void vec_xst_len (vector unsigned __int128 data, unsigned __int128 *addr, size_t len);
void vec_xst_len (vector signed long long data, signed long long *addr, size_t len);
void vec_xst_len (vector unsigned long long data, unsigned long long *addr, size_t len);
void vec_xst_len (vector signed short data, signed short *addr, size_t len);
void vec_xst_len (vector unsigned short data, unsigned short *addr, size_t len);
void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len);
void vec_xst_len (vector double data, double *addr, size_t len);
void vec_xst_len (vector float data, float *addr, size_t len);

signed char vec_xlx (unsigned int index, vector signed char data);
unsigned char vec_xlx (unsigned int index, vector unsigned char data);
signed short vec_xlx (unsigned int index, vector signed short data);
unsigned short vec_xlx (unsigned int index, vector unsigned short data);
signed int vec_xlx (unsigned int index, vector signed int data);
unsigned int vec_xlx (unsigned int index, vector unsigned int data);
float vec_xlx (unsigned int index, vector float data);

signed char vec_xrx (unsigned int index, vector signed char data);
unsigned char vec_xrx (unsigned int index, vector unsigned char data);
signed short vec_xrx (unsigned int index, vector signed short data);
unsigned short vec_xrx (unsigned int index, vector unsigned short data);
signed int vec_xrx (unsigned int index, vector signed int data);
unsigned int vec_xrx (unsigned int index, vector unsigned int data);
float vec_xrx (unsigned int index, vector float data);
</pre></div>

<p>The <code>vec_all_nez</code>, <code>vec_any_eqz</code>, and <code>vec_cmpnez</code>
perform pairwise comparisons between the elements at the same
positions within their two vector arguments.
The <code>vec_all_nez</code> function returns a
non-zero value if and only if all pairwise comparisons are not
equal and no element of either vector argument contains a zero.
The <code>vec_any_eqz</code> function returns a
non-zero value if and only if at least one pairwise comparison is equal
or if at least one element of either vector argument contains a zero.
The <code>vec_cmpnez</code> function returns a vector of the same type as
its two arguments, within which each element consists of all ones to
denote that either the corresponding elements of the incoming arguments are
not equal or that at least one of the corresponding elements contains
zero.  Otherwise, the element of the returned vector contains all zeros.
</p>
<p>The <code>vec_cntlz_lsbb</code> function returns the count of the number of
consecutive leading byte elements (starting from position 0 within the
supplied vector argument) for which the least-significant bit
equals zero.  The <code>vec_cnttz_lsbb</code> function returns the count of
the number of consecutive trailing byte elements (starting from
position 15 and counting backwards within the supplied vector
argument) for which the least-significant bit equals zero.
</p>
<p>The <code>vec_xl_len</code> and <code>vec_xst_len</code> functions require a
64-bit environment supporting ISA 3.0 or later.  The <code>vec_xl_len</code>
function loads a variable length vector from memory.  The
<code>vec_xst_len</code> function stores a variable length vector to memory.
With both the <code>vec_xl_len</code> and <code>vec_xst_len</code> functions, the
<code>addr</code> argument represents the memory address to or from which
data will be transferred, and the
<code>len</code> argument represents the number of bytes to be
transferred, as computed by the C expression <code>min((len &amp; 0xff), 16)</code>.
If this expression&rsquo;s value is not a multiple of the vector element&rsquo;s
size, the behavior of this function is undefined.
In the case that the underlying computer is configured to run in
big-endian mode, the data transfer moves bytes 0 to <code>(len - 1)</code> of
the corresponding vector.  In little-endian mode, the data transfer
moves bytes <code>(16 - len)</code> to <code>15</code> of the corresponding
vector.  For the load function, any bytes of the result vector that
are not loaded from memory are set to zero.
The value of the <code>addr</code> argument need not be aligned on a
multiple of the vector&rsquo;s element size.
</p>
<p>The <code>vec_xlx</code> and <code>vec_xrx</code> functions extract the single
element selected by the <code>index</code> argument from the vector
represented by the <code>data</code> argument.  The <code>index</code> argument
always specifies a byte offset, regardless of the size of the vector
element.  With <code>vec_xlx</code>, <code>index</code> is the offset of the first
byte of the element to be extracted.  With <code>vec_xrx</code>, <code>index</code>
represents the last byte of the element to be extracted, measured
from the right end of the vector.  In other words, the last byte of
the element to be extracted is found at position <code>(15 - index)</code>.
There is no requirement that <code>index</code> be a multiple of the vector
element size.  However, if the size of the vector element added to
<code>index</code> is greater than 15, the content of the returned value is
undefined.
</p>
<p>The following built-in functions are available for the PowerPC family
of processors when hardware decimal floating point
(<samp>-mhard-dfp</samp>) is available:
</p><div class="smallexample">
<pre class="smallexample">long long __builtin_dxex (_Decimal64);
long long __builtin_dxexq (_Decimal128);
_Decimal64 __builtin_ddedpd (int, _Decimal64);
_Decimal128 __builtin_ddedpdq (int, _Decimal128);
_Decimal64 __builtin_denbcd (int, _Decimal64);
_Decimal128 __builtin_denbcdq (int, _Decimal128);
_Decimal64 __builtin_diex (long long, _Decimal64);
_Decimal128 _builtin_diexq (long long, _Decimal128);
_Decimal64 __builtin_dscli (_Decimal64, int);
_Decimal128 __builtin_dscliq (_Decimal128, int);
_Decimal64 __builtin_dscri (_Decimal64, int);
_Decimal128 __builtin_dscriq (_Decimal128, int);
unsigned long long __builtin_unpack_dec128 (_Decimal128, int);
_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
</pre></div>

<p>The following built-in functions are available for the PowerPC family
of processors when the Vector Scalar (vsx) instruction set is
available:
</p><div class="smallexample">
<pre class="smallexample">unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int);
vector __int128_t __builtin_pack_vector_int128 (unsigned long long,
                                                unsigned long long);
</pre></div>

<hr>
<div class="header">
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