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<a name="NDS32-Options"></a>
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<p>
Next: <a href="Nios-II-Options.html#Nios-II-Options" accesskey="n" rel="next">Nios II Options</a>, Previous: <a href="MSP430-Options.html#MSP430-Options" accesskey="p" rel="prev">MSP430 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
<a name="NDS32-Options-1"></a>
<h4 class="subsection">3.18.31 NDS32 Options</h4>
<a name="index-NDS32-Options"></a>

<p>These options are defined for NDS32 implementations:
</p>
<dl compact="compact">
<dt><code>-mbig-endian</code></dt>
<dd><a name="index-mbig_002dendian-7"></a>
<p>Generate code in big-endian mode.
</p>
</dd>
<dt><code>-mlittle-endian</code></dt>
<dd><a name="index-mlittle_002dendian-7"></a>
<p>Generate code in little-endian mode.
</p>
</dd>
<dt><code>-mreduced-regs</code></dt>
<dd><a name="index-mreduced_002dregs"></a>
<p>Use reduced-set registers for register allocation.
</p>
</dd>
<dt><code>-mfull-regs</code></dt>
<dd><a name="index-mfull_002dregs"></a>
<p>Use full-set registers for register allocation.
</p>
</dd>
<dt><code>-mcmov</code></dt>
<dd><a name="index-mcmov"></a>
<p>Generate conditional move instructions.
</p>
</dd>
<dt><code>-mno-cmov</code></dt>
<dd><a name="index-mno_002dcmov"></a>
<p>Do not generate conditional move instructions.
</p>
</dd>
<dt><code>-mperf-ext</code></dt>
<dd><a name="index-mperf_002dext"></a>
<p>Generate performance extension instructions.
</p>
</dd>
<dt><code>-mno-perf-ext</code></dt>
<dd><a name="index-mno_002dperf_002dext"></a>
<p>Do not generate performance extension instructions.
</p>
</dd>
<dt><code>-mv3push</code></dt>
<dd><a name="index-mv3push"></a>
<p>Generate v3 push25/pop25 instructions.
</p>
</dd>
<dt><code>-mno-v3push</code></dt>
<dd><a name="index-mno_002dv3push"></a>
<p>Do not generate v3 push25/pop25 instructions.
</p>
</dd>
<dt><code>-m16-bit</code></dt>
<dd><a name="index-m16_002dbit-1"></a>
<p>Generate 16-bit instructions.
</p>
</dd>
<dt><code>-mno-16-bit</code></dt>
<dd><a name="index-mno_002d16_002dbit"></a>
<p>Do not generate 16-bit instructions.
</p>
</dd>
<dt><code>-misr-vector-size=<var>num</var></code></dt>
<dd><a name="index-misr_002dvector_002dsize"></a>
<p>Specify the size of each interrupt vector, which must be 4 or 16.
</p>
</dd>
<dt><code>-mcache-block-size=<var>num</var></code></dt>
<dd><a name="index-mcache_002dblock_002dsize"></a>
<p>Specify the size of each cache block,
which must be a power of 2 between 4 and 512.
</p>
</dd>
<dt><code>-march=<var>arch</var></code></dt>
<dd><a name="index-march-8"></a>
<p>Specify the name of the target architecture.
</p>
</dd>
<dt><code>-mcmodel=<var>code-model</var></code></dt>
<dd><a name="index-mcmodel"></a>
<p>Set the code model to one of
</p><dl compact="compact">
<dt>&lsquo;<samp>small</samp>&rsquo;</dt>
<dd><p>All the data and read-only data segments must be within 512KB addressing space.
The text segment must be within 16MB addressing space.
</p></dd>
<dt>&lsquo;<samp>medium</samp>&rsquo;</dt>
<dd><p>The data segment must be within 512KB while the read-only data segment can be
within 4GB addressing space.  The text segment should be still within 16MB
addressing space.
</p></dd>
<dt>&lsquo;<samp>large</samp>&rsquo;</dt>
<dd><p>All the text and data segments can be within 4GB addressing space.
</p></dd>
</dl>

</dd>
<dt><code>-mctor-dtor</code></dt>
<dd><a name="index-mctor_002ddtor"></a>
<p>Enable constructor/destructor feature.
</p>
</dd>
<dt><code>-mrelax</code></dt>
<dd><a name="index-mrelax-4"></a>
<p>Guide linker to relax instructions.
</p>
</dd>
</dl>

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