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  71. <a name="MIPS-Options"></a>
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    73. 

  73. <p>
    74. 

  74. Next: <a href="MMIX-Options.html#MMIX-Options" accesskey="n" rel="next">MMIX Options</a>, Previous: <a href="MicroBlaze-Options.html#MicroBlaze-Options" accesskey="p" rel="prev">MicroBlaze Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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    76. 

  76. <hr>
    77. 

  77. <a name="MIPS-Options-1"></a>
    78. 

  78. <h4 class="subsection">3.18.26 MIPS Options</h4>
    79. 

  79. <a name="index-MIPS-options"></a>
    80. 

  80. 

  81. <dl compact="compact">
    82. 

  82. <dt><code>-EB</code></dt>
    83. 

  83. <dd><a name="index-EB-1"></a>
    84. 

  84. <p>Generate big-endian code.
    85. 

  85. </p>
    86. 

  86. </dd>
    87. 

  87. <dt><code>-EL</code></dt>
    88. 

  88. <dd><a name="index-EL-1"></a>
    89. 

  89. <p>Generate little-endian code.  This is the default for &lsquo;<samp>mips*el-*-*</samp>&rsquo;
    90. 

  90. configurations.
    91. 

  91. </p>
    92. 

  92. </dd>
    93. 

  93. <dt><code>-march=<var>arch</var></code></dt>
    94. 

  94. <dd><a name="index-march-7"></a>
    95. 

  95. <p>Generate code that runs on <var>arch</var>, which can be the name of a
    96. 

  96. generic MIPS ISA, or the name of a particular processor.
    97. 

  97. The ISA names are:
    98. 

  98. &lsquo;<samp>mips1</samp>&rsquo;, &lsquo;<samp>mips2</samp>&rsquo;, &lsquo;<samp>mips3</samp>&rsquo;, &lsquo;<samp>mips4</samp>&rsquo;,
    99. 

  99. &lsquo;<samp>mips32</samp>&rsquo;, &lsquo;<samp>mips32r2</samp>&rsquo;, &lsquo;<samp>mips32r3</samp>&rsquo;, &lsquo;<samp>mips32r5</samp>&rsquo;,
    100. 

  100. &lsquo;<samp>mips32r6</samp>&rsquo;, &lsquo;<samp>mips64</samp>&rsquo;, &lsquo;<samp>mips64r2</samp>&rsquo;, &lsquo;<samp>mips64r3</samp>&rsquo;,
    101. 

  101. &lsquo;<samp>mips64r5</samp>&rsquo; and &lsquo;<samp>mips64r6</samp>&rsquo;.
    102. 

  102. The processor names are:
    103. 

  103. &lsquo;<samp>4kc</samp>&rsquo;, &lsquo;<samp>4km</samp>&rsquo;, &lsquo;<samp>4kp</samp>&rsquo;, &lsquo;<samp>4ksc</samp>&rsquo;,
    104. 

  104. &lsquo;<samp>4kec</samp>&rsquo;, &lsquo;<samp>4kem</samp>&rsquo;, &lsquo;<samp>4kep</samp>&rsquo;, &lsquo;<samp>4ksd</samp>&rsquo;,
    105. 

  105. &lsquo;<samp>5kc</samp>&rsquo;, &lsquo;<samp>5kf</samp>&rsquo;,
    106. 

  106. &lsquo;<samp>20kc</samp>&rsquo;,
    107. 

  107. &lsquo;<samp>24kc</samp>&rsquo;, &lsquo;<samp>24kf2_1</samp>&rsquo;, &lsquo;<samp>24kf1_1</samp>&rsquo;,
    108. 

  108. &lsquo;<samp>24kec</samp>&rsquo;, &lsquo;<samp>24kef2_1</samp>&rsquo;, &lsquo;<samp>24kef1_1</samp>&rsquo;,
    109. 

  109. &lsquo;<samp>34kc</samp>&rsquo;, &lsquo;<samp>34kf2_1</samp>&rsquo;, &lsquo;<samp>34kf1_1</samp>&rsquo;, &lsquo;<samp>34kn</samp>&rsquo;,
    110. 

  110. &lsquo;<samp>74kc</samp>&rsquo;, &lsquo;<samp>74kf2_1</samp>&rsquo;, &lsquo;<samp>74kf1_1</samp>&rsquo;, &lsquo;<samp>74kf3_2</samp>&rsquo;,
    111. 

  111. &lsquo;<samp>1004kc</samp>&rsquo;, &lsquo;<samp>1004kf2_1</samp>&rsquo;, &lsquo;<samp>1004kf1_1</samp>&rsquo;,
    112. 

  112. &lsquo;<samp>i6400</samp>&rsquo;,
    113. 

  113. &lsquo;<samp>interaptiv</samp>&rsquo;,
    114. 

  114. &lsquo;<samp>loongson2e</samp>&rsquo;, &lsquo;<samp>loongson2f</samp>&rsquo;, &lsquo;<samp>loongson3a</samp>&rsquo;,
    115. 

  115. &lsquo;<samp>m4k</samp>&rsquo;,
    116. 

  116. &lsquo;<samp>m14k</samp>&rsquo;, &lsquo;<samp>m14kc</samp>&rsquo;, &lsquo;<samp>m14ke</samp>&rsquo;, &lsquo;<samp>m14kec</samp>&rsquo;,
    117. 

  117. &lsquo;<samp>m5100</samp>&rsquo;, &lsquo;<samp>m5101</samp>&rsquo;,
    118. 

  118. &lsquo;<samp>octeon</samp>&rsquo;, &lsquo;<samp>octeon+</samp>&rsquo;, &lsquo;<samp>octeon2</samp>&rsquo;, &lsquo;<samp>octeon3</samp>&rsquo;,
    119. 

  119. &lsquo;<samp>orion</samp>&rsquo;,
    120. 

  120. &lsquo;<samp>p5600</samp>&rsquo;,
    121. 

  121. &lsquo;<samp>r2000</samp>&rsquo;, &lsquo;<samp>r3000</samp>&rsquo;, &lsquo;<samp>r3900</samp>&rsquo;, &lsquo;<samp>r4000</samp>&rsquo;, &lsquo;<samp>r4400</samp>&rsquo;,
    122. 

  122. &lsquo;<samp>r4600</samp>&rsquo;, &lsquo;<samp>r4650</samp>&rsquo;, &lsquo;<samp>r4700</samp>&rsquo;, &lsquo;<samp>r6000</samp>&rsquo;, &lsquo;<samp>r8000</samp>&rsquo;,
    123. 

  123. &lsquo;<samp>rm7000</samp>&rsquo;, &lsquo;<samp>rm9000</samp>&rsquo;,
    124. 

  124. &lsquo;<samp>r10000</samp>&rsquo;, &lsquo;<samp>r12000</samp>&rsquo;, &lsquo;<samp>r14000</samp>&rsquo;, &lsquo;<samp>r16000</samp>&rsquo;,
    125. 

  125. &lsquo;<samp>sb1</samp>&rsquo;,
    126. 

  126. &lsquo;<samp>sr71000</samp>&rsquo;,
    127. 

  127. &lsquo;<samp>vr4100</samp>&rsquo;, &lsquo;<samp>vr4111</samp>&rsquo;, &lsquo;<samp>vr4120</samp>&rsquo;, &lsquo;<samp>vr4130</samp>&rsquo;, &lsquo;<samp>vr4300</samp>&rsquo;,
    128. 

  128. &lsquo;<samp>vr5000</samp>&rsquo;, &lsquo;<samp>vr5400</samp>&rsquo;, &lsquo;<samp>vr5500</samp>&rsquo;,
    129. 

  129. &lsquo;<samp>xlr</samp>&rsquo; and &lsquo;<samp>xlp</samp>&rsquo;.
    130. 

  130. The special value &lsquo;<samp>from-abi</samp>&rsquo; selects the
    131. 

  131. most compatible architecture for the selected ABI (that is,
    132. 

  132. &lsquo;<samp>mips1</samp>&rsquo; for 32-bit ABIs and &lsquo;<samp>mips3</samp>&rsquo; for 64-bit ABIs).
    133. 

  133. </p>
    134. 

  134. <p>The native Linux/GNU toolchain also supports the value &lsquo;<samp>native</samp>&rsquo;,
    135. 

  135. which selects the best architecture option for the host processor.
    136. 

  136. <samp>-march=native</samp> has no effect if GCC does not recognize
    137. 

  137. the processor.
    138. 

  138. </p>
    139. 

  139. <p>In processor names, a final &lsquo;<samp>000</samp>&rsquo; can be abbreviated as &lsquo;<samp>k</samp>&rsquo;
    140. 

  140. (for example, <samp>-march=r2k</samp>).  Prefixes are optional, and
    141. 

  141. &lsquo;<samp>vr</samp>&rsquo; may be written &lsquo;<samp>r</samp>&rsquo;.
    142. 

  142. </p>
    143. 

  143. <p>Names of the form &lsquo;<samp><var>n</var>f2_1</samp>&rsquo; refer to processors with
    144. 

  144. FPUs clocked at half the rate of the core, names of the form
    145. 

  145. &lsquo;<samp><var>n</var>f1_1</samp>&rsquo; refer to processors with FPUs clocked at the same
    146. 

  146. rate as the core, and names of the form &lsquo;<samp><var>n</var>f3_2</samp>&rsquo; refer to
    147. 

  147. processors with FPUs clocked a ratio of 3:2 with respect to the core.
    148. 

  148. For compatibility reasons, &lsquo;<samp><var>n</var>f</samp>&rsquo; is accepted as a synonym
    149. 

  149. for &lsquo;<samp><var>n</var>f2_1</samp>&rsquo; while &lsquo;<samp><var>n</var>x</samp>&rsquo; and &lsquo;<samp><var>b</var>fx</samp>&rsquo; are
    150. 

  150. accepted as synonyms for &lsquo;<samp><var>n</var>f1_1</samp>&rsquo;.
    151. 

  151. </p>
    152. 

  152. <p>GCC defines two macros based on the value of this option.  The first
    153. 

  153. is <code>_MIPS_ARCH</code>, which gives the name of target architecture, as
    154. 

  154. a string.  The second has the form <code>_MIPS_ARCH_<var>foo</var></code>,
    155. 

  155. where <var>foo</var> is the capitalized value of <code>_MIPS_ARCH</code>.
    156. 

  156. For example, <samp>-march=r2000</samp> sets <code>_MIPS_ARCH</code>
    157. 

  157. to <code>&quot;r2000&quot;</code> and defines the macro <code>_MIPS_ARCH_R2000</code>.
    158. 

  158. </p>
    159. 

  159. <p>Note that the <code>_MIPS_ARCH</code> macro uses the processor names given
    160. 

  160. above.  In other words, it has the full prefix and does not
    161. 

  161. abbreviate &lsquo;<samp>000</samp>&rsquo; as &lsquo;<samp>k</samp>&rsquo;.  In the case of &lsquo;<samp>from-abi</samp>&rsquo;,
    162. 

  162. the macro names the resolved architecture (either <code>&quot;mips1&quot;</code> or
    163. 

  163. <code>&quot;mips3&quot;</code>).  It names the default architecture when no
    164. 

  164. <samp>-march</samp> option is given.
    165. 

  165. </p>
    166. 

  166. </dd>
    167. 

  167. <dt><code>-mtune=<var>arch</var></code></dt>
    168. 

  168. <dd><a name="index-mtune-8"></a>
    169. 

  169. <p>Optimize for <var>arch</var>.  Among other things, this option controls
    170. 

  170. the way instructions are scheduled, and the perceived cost of arithmetic
    171. 

  171. operations.  The list of <var>arch</var> values is the same as for
    172. 

  172. <samp>-march</samp>.
    173. 

  173. </p>
    174. 

  174. <p>When this option is not used, GCC optimizes for the processor
    175. 

  175. specified by <samp>-march</samp>.  By using <samp>-march</samp> and
    176. 

  176. <samp>-mtune</samp> together, it is possible to generate code that
    177. 

  177. runs on a family of processors, but optimize the code for one
    178. 

  178. particular member of that family.
    179. 

  179. </p>
    180. 

  180. <p><samp>-mtune</samp> defines the macros <code>_MIPS_TUNE</code> and
    181. 

  181. <code>_MIPS_TUNE_<var>foo</var></code>, which work in the same way as the
    182. 

  182. <samp>-march</samp> ones described above.
    183. 

  183. </p>
    184. 

  184. </dd>
    185. 

  185. <dt><code>-mips1</code></dt>
    186. 

  186. <dd><a name="index-mips1"></a>
    187. 

  187. <p>Equivalent to <samp>-march=mips1</samp>.
    188. 

  188. </p>
    189. 

  189. </dd>
    190. 

  190. <dt><code>-mips2</code></dt>
    191. 

  191. <dd><a name="index-mips2"></a>
    192. 

  192. <p>Equivalent to <samp>-march=mips2</samp>.
    193. 

  193. </p>
    194. 

  194. </dd>
    195. 

  195. <dt><code>-mips3</code></dt>
    196. 

  196. <dd><a name="index-mips3"></a>
    197. 

  197. <p>Equivalent to <samp>-march=mips3</samp>.
    198. 

  198. </p>
    199. 

  199. </dd>
    200. 

  200. <dt><code>-mips4</code></dt>
    201. 

  201. <dd><a name="index-mips4"></a>
    202. 

  202. <p>Equivalent to <samp>-march=mips4</samp>.
    203. 

  203. </p>
    204. 

  204. </dd>
    205. 

  205. <dt><code>-mips32</code></dt>
    206. 

  206. <dd><a name="index-mips32"></a>
    207. 

  207. <p>Equivalent to <samp>-march=mips32</samp>.
    208. 

  208. </p>
    209. 

  209. </dd>
    210. 

  210. <dt><code>-mips32r3</code></dt>
    211. 

  211. <dd><a name="index-mips32r3"></a>
    212. 

  212. <p>Equivalent to <samp>-march=mips32r3</samp>.
    213. 

  213. </p>
    214. 

  214. </dd>
    215. 

  215. <dt><code>-mips32r5</code></dt>
    216. 

  216. <dd><a name="index-mips32r5"></a>
    217. 

  217. <p>Equivalent to <samp>-march=mips32r5</samp>.
    218. 

  218. </p>
    219. 

  219. </dd>
    220. 

  220. <dt><code>-mips32r6</code></dt>
    221. 

  221. <dd><a name="index-mips32r6"></a>
    222. 

  222. <p>Equivalent to <samp>-march=mips32r6</samp>.
    223. 

  223. </p>
    224. 

  224. </dd>
    225. 

  225. <dt><code>-mips64</code></dt>
    226. 

  226. <dd><a name="index-mips64"></a>
    227. 

  227. <p>Equivalent to <samp>-march=mips64</samp>.
    228. 

  228. </p>
    229. 

  229. </dd>
    230. 

  230. <dt><code>-mips64r2</code></dt>
    231. 

  231. <dd><a name="index-mips64r2"></a>
    232. 

  232. <p>Equivalent to <samp>-march=mips64r2</samp>.
    233. 

  233. </p>
    234. 

  234. </dd>
    235. 

  235. <dt><code>-mips64r3</code></dt>
    236. 

  236. <dd><a name="index-mips64r3"></a>
    237. 

  237. <p>Equivalent to <samp>-march=mips64r3</samp>.
    238. 

  238. </p>
    239. 

  239. </dd>
    240. 

  240. <dt><code>-mips64r5</code></dt>
    241. 

  241. <dd><a name="index-mips64r5"></a>
    242. 

  242. <p>Equivalent to <samp>-march=mips64r5</samp>.
    243. 

  243. </p>
    244. 

  244. </dd>
    245. 

  245. <dt><code>-mips64r6</code></dt>
    246. 

  246. <dd><a name="index-mips64r6"></a>
    247. 

  247. <p>Equivalent to <samp>-march=mips64r6</samp>.
    248. 

  248. </p>
    249. 

  249. </dd>
    250. 

  250. <dt><code>-mips16</code></dt>
    251. 

  251. <dt><code>-mno-mips16</code></dt>
    252. 

  252. <dd><a name="index-mips16"></a>
    253. 

  253. <a name="index-mno_002dmips16"></a>
    254. 

  254. <p>Generate (do not generate) MIPS16 code.  If GCC is targeting a
    255. 

  255. MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
    256. 

  256. </p>
    257. 

  257. <p>MIPS16 code generation can also be controlled on a per-function basis
    258. 

  258. by means of <code>mips16</code> and <code>nomips16</code> attributes.
    259. 

  259. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>, for more information.
    260. 

  260. </p>
    261. 

  261. </dd>
    262. 

  262. <dt><code>-mflip-mips16</code></dt>
    263. 

  263. <dd><a name="index-mflip_002dmips16"></a>
    264. 

  264. <p>Generate MIPS16 code on alternating functions.  This option is provided
    265. 

  265. for regression testing of mixed MIPS16/non-MIPS16 code generation, and is
    266. 

  266. not intended for ordinary use in compiling user code.
    267. 

  267. </p>
    268. 

  268. </dd>
    269. 

  269. <dt><code>-minterlink-compressed</code></dt>
    270. 

  270. <dt><code>-mno-interlink-compressed</code></dt>
    271. 

  271. <dd><a name="index-minterlink_002dcompressed"></a>
    272. 

  272. <a name="index-mno_002dinterlink_002dcompressed"></a>
    273. 

  273. <p>Require (do not require) that code using the standard (uncompressed) MIPS ISA
    274. 

  274. be link-compatible with MIPS16 and microMIPS code, and vice versa.
    275. 

  275. </p>
    276. 

  276. <p>For example, code using the standard ISA encoding cannot jump directly
    277. 

  277. to MIPS16 or microMIPS code; it must either use a call or an indirect jump.
    278. 

  278. <samp>-minterlink-compressed</samp> therefore disables direct jumps unless GCC
    279. 

  279. knows that the target of the jump is not compressed.
    280. 

  280. </p>
    281. 

  281. </dd>
    282. 

  282. <dt><code>-minterlink-mips16</code></dt>
    283. 

  283. <dt><code>-mno-interlink-mips16</code></dt>
    284. 

  284. <dd><a name="index-minterlink_002dmips16"></a>
    285. 

  285. <a name="index-mno_002dinterlink_002dmips16"></a>
    286. 

  286. <p>Aliases of <samp>-minterlink-compressed</samp> and
    287. 

  287. <samp>-mno-interlink-compressed</samp>.  These options predate the microMIPS ASE
    288. 

  288. and are retained for backwards compatibility.
    289. 

  289. </p>
    290. 

  290. </dd>
    291. 

  291. <dt><code>-mabi=32</code></dt>
    292. 

  292. <dt><code>-mabi=o64</code></dt>
    293. 

  293. <dt><code>-mabi=n32</code></dt>
    294. 

  294. <dt><code>-mabi=64</code></dt>
    295. 

  295. <dt><code>-mabi=eabi</code></dt>
    296. 

  296. <dd><a name="index-mabi_003d32"></a>
    297. 

  297. <a name="index-mabi_003do64"></a>
    298. 

  298. <a name="index-mabi_003dn32"></a>
    299. 

  299. <a name="index-mabi_003d64"></a>
    300. 

  300. <a name="index-mabi_003deabi"></a>
    301. 

  301. <p>Generate code for the given ABI.
    302. 

  302. </p>
    303. 

  303. <p>Note that the EABI has a 32-bit and a 64-bit variant.  GCC normally
    304. 

  304. generates 64-bit code when you select a 64-bit architecture, but you
    305. 

  305. can use <samp>-mgp32</samp> to get 32-bit code instead.
    306. 

  306. </p>
    307. 

  307. <p>For information about the O64 ABI, see
    308. 

  308. <a href="http://gcc.gnu.org/projects/mipso64-abi.html">http://gcc.gnu.org/projects/mipso64-abi.html</a>.
    309. 

  309. </p>
    310. 

  310. <p>GCC supports a variant of the o32 ABI in which floating-point registers
    311. 

  311. are 64 rather than 32 bits wide.  You can select this combination with
    312. 

  312. <samp>-mabi=32</samp> <samp>-mfp64</samp>.  This ABI relies on the <code>mthc1</code>
    313. 

  313. and <code>mfhc1</code> instructions and is therefore only supported for
    314. 

  314. MIPS32R2, MIPS32R3 and MIPS32R5 processors.
    315. 

  315. </p>
    316. 

  316. <p>The register assignments for arguments and return values remain the
    317. 

  317. same, but each scalar value is passed in a single 64-bit register
    318. 

  318. rather than a pair of 32-bit registers.  For example, scalar
    319. 

  319. floating-point values are returned in &lsquo;<samp>$f0</samp>&rsquo; only, not a
    320. 

  320. &lsquo;<samp>$f0</samp>&rsquo;/&lsquo;<samp>$f1</samp>&rsquo; pair.  The set of call-saved registers also
    321. 

  321. remains the same in that the even-numbered double-precision registers
    322. 

  322. are saved.
    323. 

  323. </p>
    324. 

  324. <p>Two additional variants of the o32 ABI are supported to enable
    325. 

  325. a transition from 32-bit to 64-bit registers.  These are FPXX
    326. 

  326. (<samp>-mfpxx</samp>) and FP64A (<samp>-mfp64</samp> <samp>-mno-odd-spreg</samp>).
    327. 

  327. The FPXX extension mandates that all code must execute correctly
    328. 

  328. when run using 32-bit or 64-bit registers.  The code can be interlinked
    329. 

  329. with either FP32 or FP64, but not both.
    330. 

  330. The FP64A extension is similar to the FP64 extension but forbids the
    331. 

  331. use of odd-numbered single-precision registers.  This can be used
    332. 

  332. in conjunction with the <code>FRE</code> mode of FPUs in MIPS32R5
    333. 

  333. processors and allows both FP32 and FP64A code to interlink and
    334. 

  334. run in the same process without changing FPU modes.
    335. 

  335. </p>
    336. 

  336. </dd>
    337. 

  337. <dt><code>-mabicalls</code></dt>
    338. 

  338. <dt><code>-mno-abicalls</code></dt>
    339. 

  339. <dd><a name="index-mabicalls"></a>
    340. 

  340. <a name="index-mno_002dabicalls"></a>
    341. 

  341. <p>Generate (do not generate) code that is suitable for SVR4-style
    342. 

  342. dynamic objects.  <samp>-mabicalls</samp> is the default for SVR4-based
    343. 

  343. systems.
    344. 

  344. </p>
    345. 

  345. </dd>
    346. 

  346. <dt><code>-mshared</code></dt>
    347. 

  347. <dt><code>-mno-shared</code></dt>
    348. 

  348. <dd><p>Generate (do not generate) code that is fully position-independent,
    349. 

  349. and that can therefore be linked into shared libraries.  This option
    350. 

  350. only affects <samp>-mabicalls</samp>.
    351. 

  351. </p>
    352. 

  352. <p>All <samp>-mabicalls</samp> code has traditionally been position-independent,
    353. 

  353. regardless of options like <samp>-fPIC</samp> and <samp>-fpic</samp>.  However,
    354. 

  354. as an extension, the GNU toolchain allows executables to use absolute
    355. 

  355. accesses for locally-binding symbols.  It can also use shorter GP
    356. 

  356. initialization sequences and generate direct calls to locally-defined
    357. 

  357. functions.  This mode is selected by <samp>-mno-shared</samp>.
    358. 

  358. </p>
    359. 

  359. <p><samp>-mno-shared</samp> depends on binutils 2.16 or higher and generates
    360. 

  360. objects that can only be linked by the GNU linker.  However, the option
    361. 

  361. does not affect the ABI of the final executable; it only affects the ABI
    362. 

  362. of relocatable objects.  Using <samp>-mno-shared</samp> generally makes
    363. 

  363. executables both smaller and quicker.
    364. 

  364. </p>
    365. 

  365. <p><samp>-mshared</samp> is the default.
    366. 

  366. </p>
    367. 

  367. </dd>
    368. 

  368. <dt><code>-mplt</code></dt>
    369. 

  369. <dt><code>-mno-plt</code></dt>
    370. 

  370. <dd><a name="index-mplt"></a>
    371. 

  371. <a name="index-mno_002dplt"></a>
    372. 

  372. <p>Assume (do not assume) that the static and dynamic linkers
    373. 

  373. support PLTs and copy relocations.  This option only affects
    374. 

  374. <samp>-mno-shared -mabicalls</samp>.  For the n64 ABI, this option
    375. 

  375. has no effect without <samp>-msym32</samp>.
    376. 

  376. </p>
    377. 

  377. <p>You can make <samp>-mplt</samp> the default by configuring
    378. 

  378. GCC with <samp>--with-mips-plt</samp>.  The default is
    379. 

  379. <samp>-mno-plt</samp> otherwise.
    380. 

  380. </p>
    381. 

  381. </dd>
    382. 

  382. <dt><code>-mxgot</code></dt>
    383. 

  383. <dt><code>-mno-xgot</code></dt>
    384. 

  384. <dd><a name="index-mxgot-1"></a>
    385. 

  385. <a name="index-mno_002dxgot-1"></a>
    386. 

  386. <p>Lift (do not lift) the usual restrictions on the size of the global
    387. 

  387. offset table.
    388. 

  388. </p>
    389. 

  389. <p>GCC normally uses a single instruction to load values from the GOT.
    390. 

  390. While this is relatively efficient, it only works if the GOT
    391. 

  391. is smaller than about 64k.  Anything larger causes the linker
    392. 

  392. to report an error such as:
    393. 

  393. </p>
    394. 

  394. <a name="index-relocation-truncated-to-fit-_0028MIPS_0029"></a>
    395. 

  395. <div class="smallexample">
    396. 

  396. <pre class="smallexample">relocation truncated to fit: R_MIPS_GOT16 foobar
    397. 

  397. </pre></div>
    398. 

  398. 

  399. <p>If this happens, you should recompile your code with <samp>-mxgot</samp>.
    400. 

  400. This works with very large GOTs, although the code is also
    401. 

  401. less efficient, since it takes three instructions to fetch the
    402. 

  402. value of a global symbol.
    403. 

  403. </p>
    404. 

  404. <p>Note that some linkers can create multiple GOTs.  If you have such a
    405. 

  405. linker, you should only need to use <samp>-mxgot</samp> when a single object
    406. 

  406. file accesses more than 64k&rsquo;s worth of GOT entries.  Very few do.
    407. 

  407. </p>
    408. 

  408. <p>These options have no effect unless GCC is generating position
    409. 

  409. independent code.
    410. 

  410. </p>
    411. 

  411. </dd>
    412. 

  412. <dt><code>-mgp32</code></dt>
    413. 

  413. <dd><a name="index-mgp32"></a>
    414. 

  414. <p>Assume that general-purpose registers are 32 bits wide.
    415. 

  415. </p>
    416. 

  416. </dd>
    417. 

  417. <dt><code>-mgp64</code></dt>
    418. 

  418. <dd><a name="index-mgp64"></a>
    419. 

  419. <p>Assume that general-purpose registers are 64 bits wide.
    420. 

  420. </p>
    421. 

  421. </dd>
    422. 

  422. <dt><code>-mfp32</code></dt>
    423. 

  423. <dd><a name="index-mfp32"></a>
    424. 

  424. <p>Assume that floating-point registers are 32 bits wide.
    425. 

  425. </p>
    426. 

  426. </dd>
    427. 

  427. <dt><code>-mfp64</code></dt>
    428. 

  428. <dd><a name="index-mfp64"></a>
    429. 

  429. <p>Assume that floating-point registers are 64 bits wide.
    430. 

  430. </p>
    431. 

  431. </dd>
    432. 

  432. <dt><code>-mfpxx</code></dt>
    433. 

  433. <dd><a name="index-mfpxx"></a>
    434. 

  434. <p>Do not assume the width of floating-point registers.
    435. 

  435. </p>
    436. 

  436. </dd>
    437. 

  437. <dt><code>-mhard-float</code></dt>
    438. 

  438. <dd><a name="index-mhard_002dfloat-3"></a>
    439. 

  439. <p>Use floating-point coprocessor instructions.
    440. 

  440. </p>
    441. 

  441. </dd>
    442. 

  442. <dt><code>-msoft-float</code></dt>
    443. 

  443. <dd><a name="index-msoft_002dfloat-6"></a>
    444. 

  444. <p>Do not use floating-point coprocessor instructions.  Implement
    445. 

  445. floating-point calculations using library calls instead.
    446. 

  446. </p>
    447. 

  447. </dd>
    448. 

  448. <dt><code>-mno-float</code></dt>
    449. 

  449. <dd><a name="index-mno_002dfloat"></a>
    450. 

  450. <p>Equivalent to <samp>-msoft-float</samp>, but additionally asserts that the
    451. 

  451. program being compiled does not perform any floating-point operations.
    452. 

  452. This option is presently supported only by some bare-metal MIPS
    453. 

  453. configurations, where it may select a special set of libraries
    454. 

  454. that lack all floating-point support (including, for example, the
    455. 

  455. floating-point <code>printf</code> formats).  
    456. 

  456. If code compiled with <samp>-mno-float</samp> accidentally contains
    457. 

  457. floating-point operations, it is likely to suffer a link-time
    458. 

  458. or run-time failure.
    459. 

  459. </p>
    460. 

  460. </dd>
    461. 

  461. <dt><code>-msingle-float</code></dt>
    462. 

  462. <dd><a name="index-msingle_002dfloat"></a>
    463. 

  463. <p>Assume that the floating-point coprocessor only supports single-precision
    464. 

  464. operations.
    465. 

  465. </p>
    466. 

  466. </dd>
    467. 

  467. <dt><code>-mdouble-float</code></dt>
    468. 

  468. <dd><a name="index-mdouble_002dfloat"></a>
    469. 

  469. <p>Assume that the floating-point coprocessor supports double-precision
    470. 

  470. operations.  This is the default.
    471. 

  471. </p>
    472. 

  472. </dd>
    473. 

  473. <dt><code>-modd-spreg</code></dt>
    474. 

  474. <dt><code>-mno-odd-spreg</code></dt>
    475. 

  475. <dd><a name="index-modd_002dspreg"></a>
    476. 

  476. <a name="index-mno_002dodd_002dspreg"></a>
    477. 

  477. <p>Enable the use of odd-numbered single-precision floating-point registers
    478. 

  478. for the o32 ABI.  This is the default for processors that are known to
    479. 

  479. support these registers.  When using the o32 FPXX ABI, <samp>-mno-odd-spreg</samp>
    480. 

  480. is set by default.
    481. 

  481. </p>
    482. 

  482. </dd>
    483. 

  483. <dt><code>-mabs=2008</code></dt>
    484. 

  484. <dt><code>-mabs=legacy</code></dt>
    485. 

  485. <dd><a name="index-mabs_003d2008"></a>
    486. 

  486. <a name="index-mabs_003dlegacy"></a>
    487. 

  487. <p>These options control the treatment of the special not-a-number (NaN)
    488. 

  488. IEEE 754 floating-point data with the <code>abs.<i>fmt</i></code> and
    489. 

  489. <code>neg.<i>fmt</i></code> machine instructions.
    490. 

  490. </p>
    491. 

  491. <p>By default or when <samp>-mabs=legacy</samp> is used the legacy
    492. 

  492. treatment is selected.  In this case these instructions are considered
    493. 

  493. arithmetic and avoided where correct operation is required and the
    494. 

  494. input operand might be a NaN.  A longer sequence of instructions that
    495. 

  495. manipulate the sign bit of floating-point datum manually is used
    496. 

  496. instead unless the <samp>-ffinite-math-only</samp> option has also been
    497. 

  497. specified.
    498. 

  498. </p>
    499. 

  499. <p>The <samp>-mabs=2008</samp> option selects the IEEE 754-2008 treatment.  In
    500. 

  500. this case these instructions are considered non-arithmetic and therefore
    501. 

  501. operating correctly in all cases, including in particular where the
    502. 

  502. input operand is a NaN.  These instructions are therefore always used
    503. 

  503. for the respective operations.
    504. 

  504. </p>
    505. 

  505. </dd>
    506. 

  506. <dt><code>-mnan=2008</code></dt>
    507. 

  507. <dt><code>-mnan=legacy</code></dt>
    508. 

  508. <dd><a name="index-mnan_003d2008"></a>
    509. 

  509. <a name="index-mnan_003dlegacy"></a>
    510. 

  510. <p>These options control the encoding of the special not-a-number (NaN)
    511. 

  511. IEEE 754 floating-point data.
    512. 

  512. </p>
    513. 

  513. <p>The <samp>-mnan=legacy</samp> option selects the legacy encoding.  In this
    514. 

  514. case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
    515. 

  515. significand field being 0, whereas signaling NaNs (sNaNs) are denoted
    516. 

  516. by the first bit of their trailing significand field being 1.
    517. 

  517. </p>
    518. 

  518. <p>The <samp>-mnan=2008</samp> option selects the IEEE 754-2008 encoding.  In
    519. 

  519. this case qNaNs are denoted by the first bit of their trailing
    520. 

  520. significand field being 1, whereas sNaNs are denoted by the first bit of
    521. 

  521. their trailing significand field being 0.
    522. 

  522. </p>
    523. 

  523. <p>The default is <samp>-mnan=legacy</samp> unless GCC has been configured with
    524. 

  524. <samp>--with-nan=2008</samp>.
    525. 

  525. </p>
    526. 

  526. </dd>
    527. 

  527. <dt><code>-mllsc</code></dt>
    528. 

  528. <dt><code>-mno-llsc</code></dt>
    529. 

  529. <dd><a name="index-mllsc"></a>
    530. 

  530. <a name="index-mno_002dllsc"></a>
    531. 

  531. <p>Use (do not use) &lsquo;<samp>ll</samp>&rsquo;, &lsquo;<samp>sc</samp>&rsquo;, and &lsquo;<samp>sync</samp>&rsquo; instructions to
    532. 

  532. implement atomic memory built-in functions.  When neither option is
    533. 

  533. specified, GCC uses the instructions if the target architecture
    534. 

  534. supports them.
    535. 

  535. </p>
    536. 

  536. <p><samp>-mllsc</samp> is useful if the runtime environment can emulate the
    537. 

  537. instructions and <samp>-mno-llsc</samp> can be useful when compiling for
    538. 

  538. nonstandard ISAs.  You can make either option the default by
    539. 

  539. configuring GCC with <samp>--with-llsc</samp> and <samp>--without-llsc</samp>
    540. 

  540. respectively.  <samp>--with-llsc</samp> is the default for some
    541. 

  541. configurations; see the installation documentation for details.
    542. 

  542. </p>
    543. 

  543. </dd>
    544. 

  544. <dt><code>-mdsp</code></dt>
    545. 

  545. <dt><code>-mno-dsp</code></dt>
    546. 

  546. <dd><a name="index-mdsp"></a>
    547. 

  547. <a name="index-mno_002ddsp"></a>
    548. 

  548. <p>Use (do not use) revision 1 of the MIPS DSP ASE.
    549. 

  549. See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>.  This option defines the
    550. 

  550. preprocessor macro <code>__mips_dsp</code>.  It also defines
    551. 

  551. <code>__mips_dsp_rev</code> to 1.
    552. 

  552. </p>
    553. 

  553. </dd>
    554. 

  554. <dt><code>-mdspr2</code></dt>
    555. 

  555. <dt><code>-mno-dspr2</code></dt>
    556. 

  556. <dd><a name="index-mdspr2"></a>
    557. 

  557. <a name="index-mno_002ddspr2"></a>
    558. 

  558. <p>Use (do not use) revision 2 of the MIPS DSP ASE.
    559. 

  559. See <a href="MIPS-DSP-Built_002din-Functions.html#MIPS-DSP-Built_002din-Functions">MIPS DSP Built-in Functions</a>.  This option defines the
    560. 

  560. preprocessor macros <code>__mips_dsp</code> and <code>__mips_dspr2</code>.
    561. 

  561. It also defines <code>__mips_dsp_rev</code> to 2.
    562. 

  562. </p>
    563. 

  563. </dd>
    564. 

  564. <dt><code>-msmartmips</code></dt>
    565. 

  565. <dt><code>-mno-smartmips</code></dt>
    566. 

  566. <dd><a name="index-msmartmips"></a>
    567. 

  567. <a name="index-mno_002dsmartmips"></a>
    568. 

  568. <p>Use (do not use) the MIPS SmartMIPS ASE.
    569. 

  569. </p>
    570. 

  570. </dd>
    571. 

  571. <dt><code>-mpaired-single</code></dt>
    572. 

  572. <dt><code>-mno-paired-single</code></dt>
    573. 

  573. <dd><a name="index-mpaired_002dsingle"></a>
    574. 

  574. <a name="index-mno_002dpaired_002dsingle"></a>
    575. 

  575. <p>Use (do not use) paired-single floating-point instructions.
    576. 

  576. See <a href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support">MIPS Paired-Single Support</a>.  This option requires
    577. 

  577. hardware floating-point support to be enabled.
    578. 

  578. </p>
    579. 

  579. </dd>
    580. 

  580. <dt><code>-mdmx</code></dt>
    581. 

  581. <dt><code>-mno-mdmx</code></dt>
    582. 

  582. <dd><a name="index-mdmx"></a>
    583. 

  583. <a name="index-mno_002dmdmx"></a>
    584. 

  584. <p>Use (do not use) MIPS Digital Media Extension instructions.
    585. 

  585. This option can only be used when generating 64-bit code and requires
    586. 

  586. hardware floating-point support to be enabled.
    587. 

  587. </p>
    588. 

  588. </dd>
    589. 

  589. <dt><code>-mips3d</code></dt>
    590. 

  590. <dt><code>-mno-mips3d</code></dt>
    591. 

  591. <dd><a name="index-mips3d"></a>
    592. 

  592. <a name="index-mno_002dmips3d"></a>
    593. 

  593. <p>Use (do not use) the MIPS-3D ASE.  See <a href="MIPS_002d3D-Built_002din-Functions.html#MIPS_002d3D-Built_002din-Functions">MIPS-3D Built-in Functions</a>.
    594. 

  594. The option <samp>-mips3d</samp> implies <samp>-mpaired-single</samp>.
    595. 

  595. </p>
    596. 

  596. </dd>
    597. 

  597. <dt><code>-mmicromips</code></dt>
    598. 

  598. <dt><code>-mno-micromips</code></dt>
    599. 

  599. <dd><a name="index-mmicromips"></a>
    600. 

  600. <a name="index-mno_002dmmicromips"></a>
    601. 

  601. <p>Generate (do not generate) microMIPS code.
    602. 

  602. </p>
    603. 

  603. <p>MicroMIPS code generation can also be controlled on a per-function basis
    604. 

  604. by means of <code>micromips</code> and <code>nomicromips</code> attributes.
    605. 

  605. See <a href="Function-Attributes.html#Function-Attributes">Function Attributes</a>, for more information.
    606. 

  606. </p>
    607. 

  607. </dd>
    608. 

  608. <dt><code>-mmt</code></dt>
    609. 

  609. <dt><code>-mno-mt</code></dt>
    610. 

  610. <dd><a name="index-mmt"></a>
    611. 

  611. <a name="index-mno_002dmt"></a>
    612. 

  612. <p>Use (do not use) MT Multithreading instructions.
    613. 

  613. </p>
    614. 

  614. </dd>
    615. 

  615. <dt><code>-mmcu</code></dt>
    616. 

  616. <dt><code>-mno-mcu</code></dt>
    617. 

  617. <dd><a name="index-mmcu-1"></a>
    618. 

  618. <a name="index-mno_002dmcu"></a>
    619. 

  619. <p>Use (do not use) the MIPS MCU ASE instructions.
    620. 

  620. </p>
    621. 

  621. </dd>
    622. 

  622. <dt><code>-meva</code></dt>
    623. 

  623. <dt><code>-mno-eva</code></dt>
    624. 

  624. <dd><a name="index-meva"></a>
    625. 

  625. <a name="index-mno_002deva"></a>
    626. 

  626. <p>Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
    627. 

  627. </p>
    628. 

  628. </dd>
    629. 

  629. <dt><code>-mvirt</code></dt>
    630. 

  630. <dt><code>-mno-virt</code></dt>
    631. 

  631. <dd><a name="index-mvirt"></a>
    632. 

  632. <a name="index-mno_002dvirt"></a>
    633. 

  633. <p>Use (do not use) the MIPS Virtualization (VZ) instructions.
    634. 

  634. </p>
    635. 

  635. </dd>
    636. 

  636. <dt><code>-mxpa</code></dt>
    637. 

  637. <dt><code>-mno-xpa</code></dt>
    638. 

  638. <dd><a name="index-mxpa"></a>
    639. 

  639. <a name="index-mno_002dxpa"></a>
    640. 

  640. <p>Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
    641. 

  641. </p>
    642. 

  642. </dd>
    643. 

  643. <dt><code>-mlong64</code></dt>
    644. 

  644. <dd><a name="index-mlong64"></a>
    645. 

  645. <p>Force <code>long</code> types to be 64 bits wide.  See <samp>-mlong32</samp> for
    646. 

  646. an explanation of the default and the way that the pointer size is
    647. 

  647. determined.
    648. 

  648. </p>
    649. 

  649. </dd>
    650. 

  650. <dt><code>-mlong32</code></dt>
    651. 

  651. <dd><a name="index-mlong32"></a>
    652. 

  652. <p>Force <code>long</code>, <code>int</code>, and pointer types to be 32 bits wide.
    653. 

  653. </p>
    654. 

  654. <p>The default size of <code>int</code>s, <code>long</code>s and pointers depends on
    655. 

  655. the ABI.  All the supported ABIs use 32-bit <code>int</code>s.  The n64 ABI
    656. 

  656. uses 64-bit <code>long</code>s, as does the 64-bit EABI; the others use
    657. 

  657. 32-bit <code>long</code>s.  Pointers are the same size as <code>long</code>s,
    658. 

  658. or the same size as integer registers, whichever is smaller.
    659. 

  659. </p>
    660. 

  660. </dd>
    661. 

  661. <dt><code>-msym32</code></dt>
    662. 

  662. <dt><code>-mno-sym32</code></dt>
    663. 

  663. <dd><a name="index-msym32"></a>
    664. 

  664. <a name="index-mno_002dsym32"></a>
    665. 

  665. <p>Assume (do not assume) that all symbols have 32-bit values, regardless
    666. 

  666. of the selected ABI.  This option is useful in combination with
    667. 

  667. <samp>-mabi=64</samp> and <samp>-mno-abicalls</samp> because it allows GCC
    668. 

  668. to generate shorter and faster references to symbolic addresses.
    669. 

  669. </p>
    670. 

  670. </dd>
    671. 

  671. <dt><code>-G <var>num</var></code></dt>
    672. 

  672. <dd><a name="index-G-1"></a>
    673. 

  673. <p>Put definitions of externally-visible data in a small data section
    674. 

  674. if that data is no bigger than <var>num</var> bytes.  GCC can then generate
    675. 

  675. more efficient accesses to the data; see <samp>-mgpopt</samp> for details.
    676. 

  676. </p>
    677. 

  677. <p>The default <samp>-G</samp> option depends on the configuration.
    678. 

  678. </p>
    679. 

  679. </dd>
    680. 

  680. <dt><code>-mlocal-sdata</code></dt>
    681. 

  681. <dt><code>-mno-local-sdata</code></dt>
    682. 

  682. <dd><a name="index-mlocal_002dsdata"></a>
    683. 

  683. <a name="index-mno_002dlocal_002dsdata"></a>
    684. 

  684. <p>Extend (do not extend) the <samp>-G</samp> behavior to local data too,
    685. 

  685. such as to static variables in C.  <samp>-mlocal-sdata</samp> is the
    686. 

  686. default for all configurations.
    687. 

  687. </p>
    688. 

  688. <p>If the linker complains that an application is using too much small data,
    689. 

  689. you might want to try rebuilding the less performance-critical parts with
    690. 

  690. <samp>-mno-local-sdata</samp>.  You might also want to build large
    691. 

  691. libraries with <samp>-mno-local-sdata</samp>, so that the libraries leave
    692. 

  692. more room for the main program.
    693. 

  693. </p>
    694. 

  694. </dd>
    695. 

  695. <dt><code>-mextern-sdata</code></dt>
    696. 

  696. <dt><code>-mno-extern-sdata</code></dt>
    697. 

  697. <dd><a name="index-mextern_002dsdata"></a>
    698. 

  698. <a name="index-mno_002dextern_002dsdata"></a>
    699. 

  699. <p>Assume (do not assume) that externally-defined data is in
    700. 

  700. a small data section if the size of that data is within the <samp>-G</samp> limit.
    701. 

  701. <samp>-mextern-sdata</samp> is the default for all configurations.
    702. 

  702. </p>
    703. 

  703. <p>If you compile a module <var>Mod</var> with <samp>-mextern-sdata</samp> <samp>-G
    704. 

  704. <var>num</var></samp> <samp>-mgpopt</samp>, and <var>Mod</var> references a variable <var>Var</var>
    705. 

  705. that is no bigger than <var>num</var> bytes, you must make sure that <var>Var</var>
    706. 

  706. is placed in a small data section.  If <var>Var</var> is defined by another
    707. 

  707. module, you must either compile that module with a high-enough
    708. 

  708. <samp>-G</samp> setting or attach a <code>section</code> attribute to <var>Var</var>&rsquo;s
    709. 

  709. definition.  If <var>Var</var> is common, you must link the application
    710. 

  710. with a high-enough <samp>-G</samp> setting.
    711. 

  711. </p>
    712. 

  712. <p>The easiest way of satisfying these restrictions is to compile
    713. 

  713. and link every module with the same <samp>-G</samp> option.  However,
    714. 

  714. you may wish to build a library that supports several different
    715. 

  715. small data limits.  You can do this by compiling the library with
    716. 

  716. the highest supported <samp>-G</samp> setting and additionally using
    717. 

  717. <samp>-mno-extern-sdata</samp> to stop the library from making assumptions
    718. 

  718. about externally-defined data.
    719. 

  719. </p>
    720. 

  720. </dd>
    721. 

  721. <dt><code>-mgpopt</code></dt>
    722. 

  722. <dt><code>-mno-gpopt</code></dt>
    723. 

  723. <dd><a name="index-mgpopt"></a>
    724. 

  724. <a name="index-mno_002dgpopt"></a>
    725. 

  725. <p>Use (do not use) GP-relative accesses for symbols that are known to be
    726. 

  726. in a small data section; see <samp>-G</samp>, <samp>-mlocal-sdata</samp> and
    727. 

  727. <samp>-mextern-sdata</samp>.  <samp>-mgpopt</samp> is the default for all
    728. 

  728. configurations.
    729. 

  729. </p>
    730. 

  730. <p><samp>-mno-gpopt</samp> is useful for cases where the <code>$gp</code> register
    731. 

  731. might not hold the value of <code>_gp</code>.  For example, if the code is
    732. 

  732. part of a library that might be used in a boot monitor, programs that
    733. 

  733. call boot monitor routines pass an unknown value in <code>$gp</code>.
    734. 

  734. (In such situations, the boot monitor itself is usually compiled
    735. 

  735. with <samp>-G0</samp>.)
    736. 

  736. </p>
    737. 

  737. <p><samp>-mno-gpopt</samp> implies <samp>-mno-local-sdata</samp> and
    738. 

  738. <samp>-mno-extern-sdata</samp>.
    739. 

  739. </p>
    740. 

  740. </dd>
    741. 

  741. <dt><code>-membedded-data</code></dt>
    742. 

  742. <dt><code>-mno-embedded-data</code></dt>
    743. 

  743. <dd><a name="index-membedded_002ddata"></a>
    744. 

  744. <a name="index-mno_002dembedded_002ddata"></a>
    745. 

  745. <p>Allocate variables to the read-only data section first if possible, then
    746. 

  746. next in the small data section if possible, otherwise in data.  This gives
    747. 

  747. slightly slower code than the default, but reduces the amount of RAM required
    748. 

  748. when executing, and thus may be preferred for some embedded systems.
    749. 

  749. </p>
    750. 

  750. </dd>
    751. 

  751. <dt><code>-muninit-const-in-rodata</code></dt>
    752. 

  752. <dt><code>-mno-uninit-const-in-rodata</code></dt>
    753. 

  753. <dd><a name="index-muninit_002dconst_002din_002drodata"></a>
    754. 

  754. <a name="index-mno_002duninit_002dconst_002din_002drodata"></a>
    755. 

  755. <p>Put uninitialized <code>const</code> variables in the read-only data section.
    756. 

  756. This option is only meaningful in conjunction with <samp>-membedded-data</samp>.
    757. 

  757. </p>
    758. 

  758. </dd>
    759. 

  759. <dt><code>-mcode-readable=<var>setting</var></code></dt>
    760. 

  760. <dd><a name="index-mcode_002dreadable"></a>
    761. 

  761. <p>Specify whether GCC may generate code that reads from executable sections.
    762. 

  762. There are three possible settings:
    763. 

  763. </p>
    764. 

  764. <dl compact="compact">
    765. 

  765. <dt><code>-mcode-readable=yes</code></dt>
    766. 

  766. <dd><p>Instructions may freely access executable sections.  This is the
    767. 

  767. default setting.
    768. 

  768. </p>
    769. 

  769. </dd>
    770. 

  770. <dt><code>-mcode-readable=pcrel</code></dt>
    771. 

  771. <dd><p>MIPS16 PC-relative load instructions can access executable sections,
    772. 

  772. but other instructions must not do so.  This option is useful on 4KSc
    773. 

  773. and 4KSd processors when the code TLBs have the Read Inhibit bit set.
    774. 

  774. It is also useful on processors that can be configured to have a dual
    775. 

  775. instruction/data SRAM interface and that, like the M4K, automatically
    776. 

  776. redirect PC-relative loads to the instruction RAM.
    777. 

  777. </p>
    778. 

  778. </dd>
    779. 

  779. <dt><code>-mcode-readable=no</code></dt>
    780. 

  780. <dd><p>Instructions must not access executable sections.  This option can be
    781. 

  781. useful on targets that are configured to have a dual instruction/data
    782. 

  782. SRAM interface but that (unlike the M4K) do not automatically redirect
    783. 

  783. PC-relative loads to the instruction RAM.
    784. 

  784. </p></dd>
    785. 

  785. </dl>
    786. 

  786. 

  787. </dd>
    788. 

  788. <dt><code>-msplit-addresses</code></dt>
    789. 

  789. <dt><code>-mno-split-addresses</code></dt>
    790. 

  790. <dd><a name="index-msplit_002daddresses"></a>
    791. 

  791. <a name="index-mno_002dsplit_002daddresses"></a>
    792. 

  792. <p>Enable (disable) use of the <code>%hi()</code> and <code>%lo()</code> assembler
    793. 

  793. relocation operators.  This option has been superseded by
    794. 

  794. <samp>-mexplicit-relocs</samp> but is retained for backwards compatibility.
    795. 

  795. </p>
    796. 

  796. </dd>
    797. 

  797. <dt><code>-mexplicit-relocs</code></dt>
    798. 

  798. <dt><code>-mno-explicit-relocs</code></dt>
    799. 

  799. <dd><a name="index-mexplicit_002drelocs-1"></a>
    800. 

  800. <a name="index-mno_002dexplicit_002drelocs-1"></a>
    801. 

  801. <p>Use (do not use) assembler relocation operators when dealing with symbolic
    802. 

  802. addresses.  The alternative, selected by <samp>-mno-explicit-relocs</samp>,
    803. 

  803. is to use assembler macros instead.
    804. 

  804. </p>
    805. 

  805. <p><samp>-mexplicit-relocs</samp> is the default if GCC was configured
    806. 

  806. to use an assembler that supports relocation operators.
    807. 

  807. </p>
    808. 

  808. </dd>
    809. 

  809. <dt><code>-mcheck-zero-division</code></dt>
    810. 

  810. <dt><code>-mno-check-zero-division</code></dt>
    811. 

  811. <dd><a name="index-mcheck_002dzero_002ddivision"></a>
    812. 

  812. <a name="index-mno_002dcheck_002dzero_002ddivision"></a>
    813. 

  813. <p>Trap (do not trap) on integer division by zero.
    814. 

  814. </p>
    815. 

  815. <p>The default is <samp>-mcheck-zero-division</samp>.
    816. 

  816. </p>
    817. 

  817. </dd>
    818. 

  818. <dt><code>-mdivide-traps</code></dt>
    819. 

  819. <dt><code>-mdivide-breaks</code></dt>
    820. 

  820. <dd><a name="index-mdivide_002dtraps"></a>
    821. 

  821. <a name="index-mdivide_002dbreaks"></a>
    822. 

  822. <p>MIPS systems check for division by zero by generating either a
    823. 

  823. conditional trap or a break instruction.  Using traps results in
    824. 

  824. smaller code, but is only supported on MIPS II and later.  Also, some
    825. 

  825. versions of the Linux kernel have a bug that prevents trap from
    826. 

  826. generating the proper signal (<code>SIGFPE</code>).  Use <samp>-mdivide-traps</samp> to
    827. 

  827. allow conditional traps on architectures that support them and
    828. 

  828. <samp>-mdivide-breaks</samp> to force the use of breaks.
    829. 

  829. </p>
    830. 

  830. <p>The default is usually <samp>-mdivide-traps</samp>, but this can be
    831. 

  831. overridden at configure time using <samp>--with-divide=breaks</samp>.
    832. 

  832. Divide-by-zero checks can be completely disabled using
    833. 

  833. <samp>-mno-check-zero-division</samp>.
    834. 

  834. </p>
    835. 

  835. </dd>
    836. 

  836. <dt><code>-mload-store-pairs</code></dt>
    837. 

  837. <dt><code>-mno-load-store-pairs</code></dt>
    838. 

  838. <dd><a name="index-mload_002dstore_002dpairs"></a>
    839. 

  839. <a name="index-mno_002dload_002dstore_002dpairs"></a>
    840. 

  840. <p>Enable (disable) an optimization that pairs consecutive load or store
    841. 

  841. instructions to enable load/store bonding.  This option is enabled by
    842. 

  842. default but only takes effect when the selected architecture is known
    843. 

  843. to support bonding.
    844. 

  844. </p>
    845. 

  845. </dd>
    846. 

  846. <dt><code>-mmemcpy</code></dt>
    847. 

  847. <dt><code>-mno-memcpy</code></dt>
    848. 

  848. <dd><a name="index-mmemcpy-1"></a>
    849. 

  849. <a name="index-mno_002dmemcpy"></a>
    850. 

  850. <p>Force (do not force) the use of <code>memcpy</code> for non-trivial block
    851. 

  851. moves.  The default is <samp>-mno-memcpy</samp>, which allows GCC to inline
    852. 

  852. most constant-sized copies.
    853. 

  853. </p>
    854. 

  854. </dd>
    855. 

  855. <dt><code>-mlong-calls</code></dt>
    856. 

  856. <dt><code>-mno-long-calls</code></dt>
    857. 

  857. <dd><a name="index-mlong_002dcalls-5"></a>
    858. 

  858. <a name="index-mno_002dlong_002dcalls-3"></a>
    859. 

  859. <p>Disable (do not disable) use of the <code>jal</code> instruction.  Calling
    860. 

  860. functions using <code>jal</code> is more efficient but requires the caller
    861. 

  861. and callee to be in the same 256 megabyte segment.
    862. 

  862. </p>
    863. 

  863. <p>This option has no effect on abicalls code.  The default is
    864. 

  864. <samp>-mno-long-calls</samp>.
    865. 

  865. </p>
    866. 

  866. </dd>
    867. 

  867. <dt><code>-mmad</code></dt>
    868. 

  868. <dt><code>-mno-mad</code></dt>
    869. 

  869. <dd><a name="index-mmad"></a>
    870. 

  870. <a name="index-mno_002dmad"></a>
    871. 

  871. <p>Enable (disable) use of the <code>mad</code>, <code>madu</code> and <code>mul</code>
    872. 

  872. instructions, as provided by the R4650 ISA.
    873. 

  873. </p>
    874. 

  874. </dd>
    875. 

  875. <dt><code>-mimadd</code></dt>
    876. 

  876. <dt><code>-mno-imadd</code></dt>
    877. 

  877. <dd><a name="index-mimadd"></a>
    878. 

  878. <a name="index-mno_002dimadd"></a>
    879. 

  879. <p>Enable (disable) use of the <code>madd</code> and <code>msub</code> integer
    880. 

  880. instructions.  The default is <samp>-mimadd</samp> on architectures
    881. 

  881. that support <code>madd</code> and <code>msub</code> except for the 74k 
    882. 

  882. architecture where it was found to generate slower code.
    883. 

  883. </p>
    884. 

  884. </dd>
    885. 

  885. <dt><code>-mfused-madd</code></dt>
    886. 

  886. <dt><code>-mno-fused-madd</code></dt>
    887. 

  887. <dd><a name="index-mfused_002dmadd-1"></a>
    888. 

  888. <a name="index-mno_002dfused_002dmadd-1"></a>
    889. 

  889. <p>Enable (disable) use of the floating-point multiply-accumulate
    890. 

  890. instructions, when they are available.  The default is
    891. 

  891. <samp>-mfused-madd</samp>.
    892. 

  892. </p>
    893. 

  893. <p>On the R8000 CPU when multiply-accumulate instructions are used,
    894. 

  894. the intermediate product is calculated to infinite precision
    895. 

  895. and is not subject to the FCSR Flush to Zero bit.  This may be
    896. 

  896. undesirable in some circumstances.  On other processors the result
    897. 

  897. is numerically identical to the equivalent computation using
    898. 

  898. separate multiply, add, subtract and negate instructions.
    899. 

  899. </p>
    900. 

  900. </dd>
    901. 

  901. <dt><code>-nocpp</code></dt>
    902. 

  902. <dd><a name="index-nocpp"></a>
    903. 

  903. <p>Tell the MIPS assembler to not run its preprocessor over user
    904. 

  904. assembler files (with a &lsquo;<samp>.s</samp>&rsquo; suffix) when assembling them.
    905. 

  905. </p>
    906. 

  906. </dd>
    907. 

  907. <dt><code>-mfix-24k</code></dt>
    908. 

  908. <dt><code>-mno-fix-24k</code></dt>
    909. 

  909. <dd><a name="index-mfix_002d24k"></a>
    910. 

  910. <a name="index-mno_002dfix_002d24k"></a>
    911. 

  911. <p>Work around the 24K E48 (lost data on stores during refill) errata.
    912. 

  912. The workarounds are implemented by the assembler rather than by GCC.
    913. 

  913. </p>
    914. 

  914. </dd>
    915. 

  915. <dt><code>-mfix-r4000</code></dt>
    916. 

  916. <dt><code>-mno-fix-r4000</code></dt>
    917. 

  917. <dd><a name="index-mfix_002dr4000"></a>
    918. 

  918. <a name="index-mno_002dfix_002dr4000"></a>
    919. 

  919. <p>Work around certain R4000 CPU errata:
    920. 

  920. </p><ul class="no-bullet">
    921. 

  921. <li>- A double-word or a variable shift may give an incorrect result if executed
    922. 

  922. immediately after starting an integer division.
    923. 

  923. </li><li>- A double-word or a variable shift may give an incorrect result if executed
    924. 

  924. while an integer multiplication is in progress.
    925. 

  925. </li><li>- An integer division may give an incorrect result if started in a delay slot
    926. 

  926. of a taken branch or a jump.
    927. 

  927. </li></ul>
    928. 

  928. 

  929. </dd>
    930. 

  930. <dt><code>-mfix-r4400</code></dt>
    931. 

  931. <dt><code>-mno-fix-r4400</code></dt>
    932. 

  932. <dd><a name="index-mfix_002dr4400"></a>
    933. 

  933. <a name="index-mno_002dfix_002dr4400"></a>
    934. 

  934. <p>Work around certain R4400 CPU errata:
    935. 

  935. </p><ul class="no-bullet">
    936. 

  936. <li>- A double-word or a variable shift may give an incorrect result if executed
    937. 

  937. immediately after starting an integer division.
    938. 

  938. </li></ul>
    939. 

  939. 

  940. </dd>
    941. 

  941. <dt><code>-mfix-r10000</code></dt>
    942. 

  942. <dt><code>-mno-fix-r10000</code></dt>
    943. 

  943. <dd><a name="index-mfix_002dr10000"></a>
    944. 

  944. <a name="index-mno_002dfix_002dr10000"></a>
    945. 

  945. <p>Work around certain R10000 errata:
    946. 

  946. </p><ul class="no-bullet">
    947. 

  947. <li>- <code>ll</code>/<code>sc</code> sequences may not behave atomically on revisions
    948. 

  948. prior to 3.0.  They may deadlock on revisions 2.6 and earlier.
    949. 

  949. </li></ul>
    950. 

  950. 

  951. <p>This option can only be used if the target architecture supports
    952. 

  952. branch-likely instructions.  <samp>-mfix-r10000</samp> is the default when
    953. 

  953. <samp>-march=r10000</samp> is used; <samp>-mno-fix-r10000</samp> is the default
    954. 

  954. otherwise.
    955. 

  955. </p>
    956. 

  956. </dd>
    957. 

  957. <dt><code>-mfix-rm7000</code></dt>
    958. 

  958. <dt><code>-mno-fix-rm7000</code></dt>
    959. 

  959. <dd><a name="index-mfix_002drm7000"></a>
    960. 

  960. <p>Work around the RM7000 <code>dmult</code>/<code>dmultu</code> errata.  The
    961. 

  961. workarounds are implemented by the assembler rather than by GCC.
    962. 

  962. </p>
    963. 

  963. </dd>
    964. 

  964. <dt><code>-mfix-vr4120</code></dt>
    965. 

  965. <dt><code>-mno-fix-vr4120</code></dt>
    966. 

  966. <dd><a name="index-mfix_002dvr4120"></a>
    967. 

  967. <p>Work around certain VR4120 errata:
    968. 

  968. </p><ul class="no-bullet">
    969. 

  969. <li>- <code>dmultu</code> does not always produce the correct result.
    970. 

  970. </li><li>- <code>div</code> and <code>ddiv</code> do not always produce the correct result if one
    971. 

  971. of the operands is negative.
    972. 

  972. </li></ul>
    973. 

  973. <p>The workarounds for the division errata rely on special functions in
    974. 

  974. <samp>libgcc.a</samp>.  At present, these functions are only provided by
    975. 

  975. the <code>mips64vr*-elf</code> configurations.
    976. 

  976. </p>
    977. 

  977. <p>Other VR4120 errata require a NOP to be inserted between certain pairs of
    978. 

  978. instructions.  These errata are handled by the assembler, not by GCC itself.
    979. 

  979. </p>
    980. 

  980. </dd>
    981. 

  981. <dt><code>-mfix-vr4130</code></dt>
    982. 

  982. <dd><a name="index-mfix_002dvr4130"></a>
    983. 

  983. <p>Work around the VR4130 <code>mflo</code>/<code>mfhi</code> errata.  The
    984. 

  984. workarounds are implemented by the assembler rather than by GCC,
    985. 

  985. although GCC avoids using <code>mflo</code> and <code>mfhi</code> if the
    986. 

  986. VR4130 <code>macc</code>, <code>macchi</code>, <code>dmacc</code> and <code>dmacchi</code>
    987. 

  987. instructions are available instead.
    988. 

  988. </p>
    989. 

  989. </dd>
    990. 

  990. <dt><code>-mfix-sb1</code></dt>
    991. 

  991. <dt><code>-mno-fix-sb1</code></dt>
    992. 

  992. <dd><a name="index-mfix_002dsb1"></a>
    993. 

  993. <p>Work around certain SB-1 CPU core errata.
    994. 

  994. (This flag currently works around the SB-1 revision 2
    995. 

  995. &ldquo;F1&rdquo; and &ldquo;F2&rdquo; floating-point errata.)
    996. 

  996. </p>
    997. 

  997. </dd>
    998. 

  998. <dt><code>-mr10k-cache-barrier=<var>setting</var></code></dt>
    999. 

  999. <dd><a name="index-mr10k_002dcache_002dbarrier"></a>
    1000. 

  1000. <p>Specify whether GCC should insert cache barriers to avoid the
    1001. 

  1001. side-effects of speculation on R10K processors.
    1002. 

  1002. </p>
    1003. 

  1003. <p>In common with many processors, the R10K tries to predict the outcome
    1004. 

  1004. of a conditional branch and speculatively executes instructions from
    1005. 

  1005. the &ldquo;taken&rdquo; branch.  It later aborts these instructions if the
    1006. 

  1006. predicted outcome is wrong.  However, on the R10K, even aborted
    1007. 

  1007. instructions can have side effects.
    1008. 

  1008. </p>
    1009. 

  1009. <p>This problem only affects kernel stores and, depending on the system,
    1010. 

  1010. kernel loads.  As an example, a speculatively-executed store may load
    1011. 

  1011. the target memory into cache and mark the cache line as dirty, even if
    1012. 

  1012. the store itself is later aborted.  If a DMA operation writes to the
    1013. 

  1013. same area of memory before the &ldquo;dirty&rdquo; line is flushed, the cached
    1014. 

  1014. data overwrites the DMA-ed data.  See the R10K processor manual
    1015. 

  1015. for a full description, including other potential problems.
    1016. 

  1016. </p>
    1017. 

  1017. <p>One workaround is to insert cache barrier instructions before every memory
    1018. 

  1018. access that might be speculatively executed and that might have side
    1019. 

  1019. effects even if aborted.  <samp>-mr10k-cache-barrier=<var>setting</var></samp>
    1020. 

  1020. controls GCC&rsquo;s implementation of this workaround.  It assumes that
    1021. 

  1021. aborted accesses to any byte in the following regions does not have
    1022. 

  1022. side effects:
    1023. 

  1023. </p>
    1024. 

  1024. <ol>
    1025. 

  1025. <li> the memory occupied by the current function&rsquo;s stack frame;
    1026. 

  1026. 

  1027. </li><li> the memory occupied by an incoming stack argument;
    1028. 

  1028. 

  1029. </li><li> the memory occupied by an object with a link-time-constant address.
    1030. 

  1030. </li></ol>
    1031. 

  1031. 

  1032. <p>It is the kernel&rsquo;s responsibility to ensure that speculative
    1033. 

  1033. accesses to these regions are indeed safe.
    1034. 

  1034. </p>
    1035. 

  1035. <p>If the input program contains a function declaration such as:
    1036. 

  1036. </p>
    1037. 

  1037. <div class="smallexample">
    1038. 

  1038. <pre class="smallexample">void foo (void);
    1039. 

  1039. </pre></div>
    1040. 

  1040. 

  1041. <p>then the implementation of <code>foo</code> must allow <code>j foo</code> and
    1042. 

  1042. <code>jal foo</code> to be executed speculatively.  GCC honors this
    1043. 

  1043. restriction for functions it compiles itself.  It expects non-GCC
    1044. 

  1044. functions (such as hand-written assembly code) to do the same.
    1045. 

  1045. </p>
    1046. 

  1046. <p>The option has three forms:
    1047. 

  1047. </p>
    1048. 

  1048. <dl compact="compact">
    1049. 

  1049. <dt><code>-mr10k-cache-barrier=load-store</code></dt>
    1050. 

  1050. <dd><p>Insert a cache barrier before a load or store that might be
    1051. 

  1051. speculatively executed and that might have side effects even
    1052. 

  1052. if aborted.
    1053. 

  1053. </p>
    1054. 

  1054. </dd>
    1055. 

  1055. <dt><code>-mr10k-cache-barrier=store</code></dt>
    1056. 

  1056. <dd><p>Insert a cache barrier before a store that might be speculatively
    1057. 

  1057. executed and that might have side effects even if aborted.
    1058. 

  1058. </p>
    1059. 

  1059. </dd>
    1060. 

  1060. <dt><code>-mr10k-cache-barrier=none</code></dt>
    1061. 

  1061. <dd><p>Disable the insertion of cache barriers.  This is the default setting.
    1062. 

  1062. </p></dd>
    1063. 

  1063. </dl>
    1064. 

  1064. 

  1065. </dd>
    1066. 

  1066. <dt><code>-mflush-func=<var>func</var></code></dt>
    1067. 

  1067. <dt><code>-mno-flush-func</code></dt>
    1068. 

  1068. <dd><a name="index-mflush_002dfunc"></a>
    1069. 

  1069. <p>Specifies the function to call to flush the I and D caches, or to not
    1070. 

  1070. call any such function.  If called, the function must take the same
    1071. 

  1071. arguments as the common <code>_flush_func</code>, that is, the address of the
    1072. 

  1072. memory range for which the cache is being flushed, the size of the
    1073. 

  1073. memory range, and the number 3 (to flush both caches).  The default
    1074. 

  1074. depends on the target GCC was configured for, but commonly is either
    1075. 

  1075. <code>_flush_func</code> or <code>__cpu_flush</code>.
    1076. 

  1076. </p>
    1077. 

  1077. </dd>
    1078. 

  1078. <dt><code>mbranch-cost=<var>num</var></code></dt>
    1079. 

  1079. <dd><a name="index-mbranch_002dcost-2"></a>
    1080. 

  1080. <p>Set the cost of branches to roughly <var>num</var> &ldquo;simple&rdquo; instructions.
    1081. 

  1081. This cost is only a heuristic and is not guaranteed to produce
    1082. 

  1082. consistent results across releases.  A zero cost redundantly selects
    1083. 

  1083. the default, which is based on the <samp>-mtune</samp> setting.
    1084. 

  1084. </p>
    1085. 

  1085. </dd>
    1086. 

  1086. <dt><code>-mbranch-likely</code></dt>
    1087. 

  1087. <dt><code>-mno-branch-likely</code></dt>
    1088. 

  1088. <dd><a name="index-mbranch_002dlikely"></a>
    1089. 

  1089. <a name="index-mno_002dbranch_002dlikely"></a>
    1090. 

  1090. <p>Enable or disable use of Branch Likely instructions, regardless of the
    1091. 

  1091. default for the selected architecture.  By default, Branch Likely
    1092. 

  1092. instructions may be generated if they are supported by the selected
    1093. 

  1093. architecture.  An exception is for the MIPS32 and MIPS64 architectures
    1094. 

  1094. and processors that implement those architectures; for those, Branch
    1095. 

  1095. Likely instructions are not be generated by default because the MIPS32
    1096. 

  1096. and MIPS64 architectures specifically deprecate their use.
    1097. 

  1097. </p>
    1098. 

  1098. </dd>
    1099. 

  1099. <dt><code>-mcompact-branches=never</code></dt>
    1100. 

  1100. <dt><code>-mcompact-branches=optimal</code></dt>
    1101. 

  1101. <dt><code>-mcompact-branches=always</code></dt>
    1102. 

  1102. <dd><a name="index-mcompact_002dbranches_003dnever"></a>
    1103. 

  1103. <a name="index-mcompact_002dbranches_003doptimal"></a>
    1104. 

  1104. <a name="index-mcompact_002dbranches_003dalways"></a>
    1105. 

  1105. <p>These options control which form of branches will be generated.  The
    1106. 

  1106. default is <samp>-mcompact-branches=optimal</samp>.
    1107. 

  1107. </p>
    1108. 

  1108. <p>The <samp>-mcompact-branches=never</samp> option ensures that compact branch
    1109. 

  1109. instructions will never be generated.
    1110. 

  1110. </p>
    1111. 

  1111. <p>The <samp>-mcompact-branches=always</samp> option ensures that a compact
    1112. 

  1112. branch instruction will be generated if available.  If a compact branch
    1113. 

  1113. instruction is not available, a delay slot form of the branch will be
    1114. 

  1114. used instead.
    1115. 

  1115. </p>
    1116. 

  1116. <p>This option is supported from MIPS Release 6 onwards.
    1117. 

  1117. </p>
    1118. 

  1118. <p>The <samp>-mcompact-branches=optimal</samp> option will cause a delay slot
    1119. 

  1119. branch to be used if one is available in the current ISA and the delay
    1120. 

  1120. slot is successfully filled.  If the delay slot is not filled, a compact
    1121. 

  1121. branch will be chosen if one is available.
    1122. 

  1122. </p>
    1123. 

  1123. </dd>
    1124. 

  1124. <dt><code>-mfp-exceptions</code></dt>
    1125. 

  1125. <dt><code>-mno-fp-exceptions</code></dt>
    1126. 

  1126. <dd><a name="index-mfp_002dexceptions"></a>
    1127. 

  1127. <p>Specifies whether FP exceptions are enabled.  This affects how
    1128. 

  1128. FP instructions are scheduled for some processors.
    1129. 

  1129. The default is that FP exceptions are
    1130. 

  1130. enabled.
    1131. 

  1131. </p>
    1132. 

  1132. <p>For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
    1133. 

  1133. 64-bit code, then we can use both FP pipes.  Otherwise, we can only use one
    1134. 

  1134. FP pipe.
    1135. 

  1135. </p>
    1136. 

  1136. </dd>
    1137. 

  1137. <dt><code>-mvr4130-align</code></dt>
    1138. 

  1138. <dt><code>-mno-vr4130-align</code></dt>
    1139. 

  1139. <dd><a name="index-mvr4130_002dalign"></a>
    1140. 

  1140. <p>The VR4130 pipeline is two-way superscalar, but can only issue two
    1141. 

  1141. instructions together if the first one is 8-byte aligned.  When this
    1142. 

  1142. option is enabled, GCC aligns pairs of instructions that it
    1143. 

  1143. thinks should execute in parallel.
    1144. 

  1144. </p>
    1145. 

  1145. <p>This option only has an effect when optimizing for the VR4130.
    1146. 

  1146. It normally makes code faster, but at the expense of making it bigger.
    1147. 

  1147. It is enabled by default at optimization level <samp>-O3</samp>.
    1148. 

  1148. </p>
    1149. 

  1149. </dd>
    1150. 

  1150. <dt><code>-msynci</code></dt>
    1151. 

  1151. <dt><code>-mno-synci</code></dt>
    1152. 

  1152. <dd><a name="index-msynci"></a>
    1153. 

  1153. <p>Enable (disable) generation of <code>synci</code> instructions on
    1154. 

  1154. architectures that support it.  The <code>synci</code> instructions (if
    1155. 

  1155. enabled) are generated when <code>__builtin___clear_cache</code> is
    1156. 

  1156. compiled.
    1157. 

  1157. </p>
    1158. 

  1158. <p>This option defaults to <samp>-mno-synci</samp>, but the default can be
    1159. 

  1159. overridden by configuring GCC with <samp>--with-synci</samp>.
    1160. 

  1160. </p>
    1161. 

  1161. <p>When compiling code for single processor systems, it is generally safe
    1162. 

  1162. to use <code>synci</code>.  However, on many multi-core (SMP) systems, it
    1163. 

  1163. does not invalidate the instruction caches on all cores and may lead
    1164. 

  1164. to undefined behavior.
    1165. 

  1165. </p>
    1166. 

  1166. </dd>
    1167. 

  1167. <dt><code>-mrelax-pic-calls</code></dt>
    1168. 

  1168. <dt><code>-mno-relax-pic-calls</code></dt>
    1169. 

  1169. <dd><a name="index-mrelax_002dpic_002dcalls"></a>
    1170. 

  1170. <p>Try to turn PIC calls that are normally dispatched via register
    1171. 

  1171. <code>$25</code> into direct calls.  This is only possible if the linker can
    1172. 

  1172. resolve the destination at link time and if the destination is within
    1173. 

  1173. range for a direct call.
    1174. 

  1174. </p>
    1175. 

  1175. <p><samp>-mrelax-pic-calls</samp> is the default if GCC was configured to use
    1176. 

  1176. an assembler and a linker that support the <code>.reloc</code> assembly
    1177. 

  1177. directive and <samp>-mexplicit-relocs</samp> is in effect.  With
    1178. 

  1178. <samp>-mno-explicit-relocs</samp>, this optimization can be performed by the
    1179. 

  1179. assembler and the linker alone without help from the compiler.
    1180. 

  1180. </p>
    1181. 

  1181. </dd>
    1182. 

  1182. <dt><code>-mmcount-ra-address</code></dt>
    1183. 

  1183. <dt><code>-mno-mcount-ra-address</code></dt>
    1184. 

  1184. <dd><a name="index-mmcount_002dra_002daddress"></a>
    1185. 

  1185. <a name="index-mno_002dmcount_002dra_002daddress"></a>
    1186. 

  1186. <p>Emit (do not emit) code that allows <code>_mcount</code> to modify the
    1187. 

  1187. calling function&rsquo;s return address.  When enabled, this option extends
    1188. 

  1188. the usual <code>_mcount</code> interface with a new <var>ra-address</var>
    1189. 

  1189. parameter, which has type <code>intptr_t *</code> and is passed in register
    1190. 

  1190. <code>$12</code>.  <code>_mcount</code> can then modify the return address by
    1191. 

  1191. doing both of the following:
    1192. 

  1192. </p><ul>
    1193. 

  1193. <li> Returning the new address in register <code>$31</code>.
    1194. 

  1194. </li><li> Storing the new address in <code>*<var>ra-address</var></code>,
    1195. 

  1195. if <var>ra-address</var> is nonnull.
    1196. 

  1196. </li></ul>
    1197. 

  1197. 

  1198. <p>The default is <samp>-mno-mcount-ra-address</samp>.
    1199. 

  1199. </p>
    1200. 

  1200. </dd>
    1201. 

  1201. <dt><code>-mframe-header-opt</code></dt>
    1202. 

  1202. <dt><code>-mno-frame-header-opt</code></dt>
    1203. 

  1203. <dd><a name="index-mframe_002dheader_002dopt"></a>
    1204. 

  1204. <p>Enable (disable) frame header optimization in the o32 ABI.  When using the
    1205. 

  1205. o32 ABI, calling functions will allocate 16 bytes on the stack for the called
    1206. 

  1206. function to write out register arguments.  When enabled, this optimization
    1207. 

  1207. will suppress the allocation of the frame header if it can be determined that
    1208. 

  1208. it is unused.
    1209. 

  1209. </p>
    1210. 

  1210. <p>This optimization is off by default at all optimization levels.
    1211. 

  1211. </p>
    1212. 

  1212. </dd>
    1213. 

  1213. <dt><code>-mlxc1-sxc1</code></dt>
    1214. 

  1214. <dt><code>-mno-lxc1-sxc1</code></dt>
    1215. 

  1215. <dd><a name="index-mlxc1_002dsxc1"></a>
    1216. 

  1216. <p>When applicable, enable (disable) the generation of <code>lwxc1</code>,
    1217. 

  1217. <code>swxc1</code>, <code>ldxc1</code>, <code>sdxc1</code> instructions.  Enabled by default.
    1218. 

  1218. </p>
    1219. 

  1219. </dd>
    1220. 

  1220. <dt><code>-mmadd4</code></dt>
    1221. 

  1221. <dt><code>-mno-madd4</code></dt>
    1222. 

  1222. <dd><a name="index-mmadd4"></a>
    1223. 

  1223. <p>When applicable, enable (disable) the generation of 4-operand <code>madd.s</code>,
    1224. 

  1224. <code>madd.d</code> and related instructions.  Enabled by default.
    1225. 

  1225. </p>
    1226. 

  1226. </dd>
    1227. 

  1227. </dl>
    1228. 

  1228. 

  1229. <hr>
    1230. 

  1230. <div class="header">
    1231. 

  1231. <p>
    1232. 

  1232. Next: <a href="MMIX-Options.html#MMIX-Options" accesskey="n" rel="next">MMIX Options</a>, Previous: <a href="MicroBlaze-Options.html#MicroBlaze-Options" accesskey="p" rel="prev">MicroBlaze Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
    1233. 

  1233. </div>
    1234. 

  1234. 

  1235. 

  1236. 

  1237. </body>
    1238. 

  1238. </html>
    1239.