Página Principal Explorar Ajuda
Registe-se Iniciar Sessão
huangmeng
/
Embedded_AI
1
0
Fork 0
Ficheiros Problemas 0 Pull Requests 0 Wiki
Ramo: master
Ramos Etiquetas
Embedded_AI
/
gcc-linaro-7.5.0-2019.12-x86_64_arm-linux-gnueabihf
/
share
/
doc
/
gcc
/
ARM-Options.html

ARM-Options.html 32 KB
Link permanente Histórico Em bruto

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607 
  1. <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
    2. 

  2. <html>
    3. 

  3. <!-- Copyright (C) 1988-2017 Free Software Foundation, Inc.
    4. 

  4. 

  5. Permission is granted to copy, distribute and/or modify this document
    6. 

  6. under the terms of the GNU Free Documentation License, Version 1.3 or
    7. 

  7. any later version published by the Free Software Foundation; with the
    8. 

  8. Invariant Sections being "Funding Free Software", the Front-Cover
    9. 

  9. Texts being (a) (see below), and with the Back-Cover Texts being (b)
    10. 

  10. (see below).  A copy of the license is included in the section entitled
    11. 

  11. "GNU Free Documentation License".
    12. 

  12. 

  13. (a) The FSF's Front-Cover Text is:
    14. 

  14. 

  15. A GNU Manual
    16. 

  16. 

  17. (b) The FSF's Back-Cover Text is:
    18. 

  18. 

  19. You have freedom to copy and modify this GNU Manual, like GNU
    20. 

  20.      software.  Copies published by the Free Software Foundation raise
    21. 

  21.      funds for GNU development. -->
    22. 

  22. <!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
    23. 

  23. <head>
    24. 

  24. <title>Using the GNU Compiler Collection (GCC): ARM Options</title>
    25. 

  25. 

  26. <meta name="description" content="Using the GNU Compiler Collection (GCC): ARM Options">
    27. 

  27. <meta name="keywords" content="Using the GNU Compiler Collection (GCC): ARM Options">
    28. 

  28. <meta name="resource-type" content="document">
    29. 

  29. <meta name="distribution" content="global">
    30. 

  30. <meta name="Generator" content="makeinfo">
    31. 

  31. <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
    32. 

  32. <link href="index.html#Top" rel="start" title="Top">
    33. 

  33. <link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
    34. 

  34. <link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
    35. 

  35. <link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
    36. 

  36. <link href="AVR-Options.html#AVR-Options" rel="next" title="AVR Options">
    37. 

  37. <link href="ARC-Options.html#ARC-Options" rel="prev" title="ARC Options">
    38. 

  38. <style type="text/css">
    39. 

  39. <!--
    40. 

  40. a.summary-letter {text-decoration: none}
    41. 

  41. blockquote.smallquotation {font-size: smaller}
    42. 

  42. div.display {margin-left: 3.2em}
    43. 

  43. div.example {margin-left: 3.2em}
    44. 

  44. div.indentedblock {margin-left: 3.2em}
    45. 

  45. div.lisp {margin-left: 3.2em}
    46. 

  46. div.smalldisplay {margin-left: 3.2em}
    47. 

  47. div.smallexample {margin-left: 3.2em}
    48. 

  48. div.smallindentedblock {margin-left: 3.2em; font-size: smaller}
    49. 

  49. div.smalllisp {margin-left: 3.2em}
    50. 

  50. kbd {font-style:oblique}
    51. 

  51. pre.display {font-family: inherit}
    52. 

  52. pre.format {font-family: inherit}
    53. 

  53. pre.menu-comment {font-family: serif}
    54. 

  54. pre.menu-preformatted {font-family: serif}
    55. 

  55. pre.smalldisplay {font-family: inherit; font-size: smaller}
    56. 

  56. pre.smallexample {font-size: smaller}
    57. 

  57. pre.smallformat {font-family: inherit; font-size: smaller}
    58. 

  58. pre.smalllisp {font-size: smaller}
    59. 

  59. span.nocodebreak {white-space:nowrap}
    60. 

  60. span.nolinebreak {white-space:nowrap}
    61. 

  61. span.roman {font-family:serif; font-weight:normal}
    62. 

  62. span.sansserif {font-family:sans-serif; font-weight:normal}
    63. 

  63. ul.no-bullet {list-style: none}
    64. 

  64. -->
    65. 

  65. </style>
    66. 

  66. 

  67. 

  68. </head>
    69. 

  69. 

  70. <body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
    71. 

  71. <a name="ARM-Options"></a>
    72. 

  72. <div class="header">
    73. 

  73. <p>
    74. 

  74. Next: <a href="AVR-Options.html#AVR-Options" accesskey="n" rel="next">AVR Options</a>, Previous: <a href="ARC-Options.html#ARC-Options" accesskey="p" rel="prev">ARC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
    75. 

  75. </div>
    76. 

  76. <hr>
    77. 

  77. <a name="ARM-Options-1"></a>
    78. 

  78. <h4 class="subsection">3.18.4 ARM Options</h4>
    79. 

  79. <a name="index-ARM-options"></a>
    80. 

  80. 

  81. <p>These &lsquo;<samp>-m</samp>&rsquo; options are defined for the ARM port:
    82. 

  82. </p>
    83. 

  83. <dl compact="compact">
    84. 

  84. <dt><code>-mabi=<var>name</var></code></dt>
    85. 

  85. <dd><a name="index-mabi-1"></a>
    86. 

  86. <p>Generate code for the specified ABI.  Permissible values are: &lsquo;<samp>apcs-gnu</samp>&rsquo;,
    87. 

  87. &lsquo;<samp>atpcs</samp>&rsquo;, &lsquo;<samp>aapcs</samp>&rsquo;, &lsquo;<samp>aapcs-linux</samp>&rsquo; and &lsquo;<samp>iwmmxt</samp>&rsquo;.
    88. 

  88. </p>
    89. 

  89. </dd>
    90. 

  90. <dt><code>-mapcs-frame</code></dt>
    91. 

  91. <dd><a name="index-mapcs_002dframe"></a>
    92. 

  92. <p>Generate a stack frame that is compliant with the ARM Procedure Call
    93. 

  93. Standard for all functions, even if this is not strictly necessary for
    94. 

  94. correct execution of the code.  Specifying <samp>-fomit-frame-pointer</samp>
    95. 

  95. with this option causes the stack frames not to be generated for
    96. 

  96. leaf functions.  The default is <samp>-mno-apcs-frame</samp>.
    97. 

  97. This option is deprecated.
    98. 

  98. </p>
    99. 

  99. </dd>
    100. 

  100. <dt><code>-mapcs</code></dt>
    101. 

  101. <dd><a name="index-mapcs"></a>
    102. 

  102. <p>This is a synonym for <samp>-mapcs-frame</samp> and is deprecated.
    103. 

  103. </p>
    104. 

  104. 

  105. </dd>
    106. 

  106. <dt><code>-mthumb-interwork</code></dt>
    107. 

  107. <dd><a name="index-mthumb_002dinterwork"></a>
    108. 

  108. <p>Generate code that supports calling between the ARM and Thumb
    109. 

  109. instruction sets.  Without this option, on pre-v5 architectures, the
    110. 

  110. two instruction sets cannot be reliably used inside one program.  The
    111. 

  111. default is <samp>-mno-thumb-interwork</samp>, since slightly larger code
    112. 

  112. is generated when <samp>-mthumb-interwork</samp> is specified.  In AAPCS
    113. 

  113. configurations this option is meaningless.
    114. 

  114. </p>
    115. 

  115. </dd>
    116. 

  116. <dt><code>-mno-sched-prolog</code></dt>
    117. 

  117. <dd><a name="index-mno_002dsched_002dprolog"></a>
    118. 

  118. <p>Prevent the reordering of instructions in the function prologue, or the
    119. 

  119. merging of those instruction with the instructions in the function&rsquo;s
    120. 

  120. body.  This means that all functions start with a recognizable set
    121. 

  121. of instructions (or in fact one of a choice from a small set of
    122. 

  122. different function prologues), and this information can be used to
    123. 

  123. locate the start of functions inside an executable piece of code.  The
    124. 

  124. default is <samp>-msched-prolog</samp>.
    125. 

  125. </p>
    126. 

  126. </dd>
    127. 

  127. <dt><code>-mfloat-abi=<var>name</var></code></dt>
    128. 

  128. <dd><a name="index-mfloat_002dabi"></a>
    129. 

  129. <p>Specifies which floating-point ABI to use.  Permissible values
    130. 

  130. are: &lsquo;<samp>soft</samp>&rsquo;, &lsquo;<samp>softfp</samp>&rsquo; and &lsquo;<samp>hard</samp>&rsquo;.
    131. 

  131. </p>
    132. 

  132. <p>Specifying &lsquo;<samp>soft</samp>&rsquo; causes GCC to generate output containing
    133. 

  133. library calls for floating-point operations.
    134. 

  134. &lsquo;<samp>softfp</samp>&rsquo; allows the generation of code using hardware floating-point
    135. 

  135. instructions, but still uses the soft-float calling conventions.
    136. 

  136. &lsquo;<samp>hard</samp>&rsquo; allows generation of floating-point instructions
    137. 

  137. and uses FPU-specific calling conventions.
    138. 

  138. </p>
    139. 

  139. <p>The default depends on the specific target configuration.  Note that
    140. 

  140. the hard-float and soft-float ABIs are not link-compatible; you must
    141. 

  141. compile your entire program with the same ABI, and link with a
    142. 

  142. compatible set of libraries.
    143. 

  143. </p>
    144. 

  144. </dd>
    145. 

  145. <dt><code>-mlittle-endian</code></dt>
    146. 

  146. <dd><a name="index-mlittle_002dendian-2"></a>
    147. 

  147. <p>Generate code for a processor running in little-endian mode.  This is
    148. 

  148. the default for all standard configurations.
    149. 

  149. </p>
    150. 

  150. </dd>
    151. 

  151. <dt><code>-mbig-endian</code></dt>
    152. 

  152. <dd><a name="index-mbig_002dendian-2"></a>
    153. 

  153. <p>Generate code for a processor running in big-endian mode; the default is
    154. 

  154. to compile code for a little-endian processor.
    155. 

  155. </p>
    156. 

  156. </dd>
    157. 

  157. <dt><code>-march=<var>name</var></code></dt>
    158. 

  158. <dd><a name="index-march-1"></a>
    159. 

  159. <p>This specifies the name of the target ARM architecture.  GCC uses this
    160. 

  160. name to determine what kind of instructions it can emit when generating
    161. 

  161. assembly code.  This option can be used in conjunction with or instead
    162. 

  162. of the <samp>-mcpu=</samp> option.  Permissible names are: &lsquo;<samp>armv2</samp>&rsquo;,
    163. 

  163. &lsquo;<samp>armv2a</samp>&rsquo;, &lsquo;<samp>armv3</samp>&rsquo;, &lsquo;<samp>armv3m</samp>&rsquo;, &lsquo;<samp>armv4</samp>&rsquo;, &lsquo;<samp>armv4t</samp>&rsquo;,
    164. 

  164. &lsquo;<samp>armv5</samp>&rsquo;, &lsquo;<samp>armv5e</samp>&rsquo;, &lsquo;<samp>armv5t</samp>&rsquo;, &lsquo;<samp>armv5te</samp>&rsquo;,
    165. 

  165. &lsquo;<samp>armv6</samp>&rsquo;, &lsquo;<samp>armv6-m</samp>&rsquo;, &lsquo;<samp>armv6j</samp>&rsquo;, &lsquo;<samp>armv6k</samp>&rsquo;,
    166. 

  166. &lsquo;<samp>armv6kz</samp>&rsquo;, &lsquo;<samp>armv6s-m</samp>&rsquo;,
    167. 

  167. &lsquo;<samp>armv6t2</samp>&rsquo;, &lsquo;<samp>armv6z</samp>&rsquo;, &lsquo;<samp>armv6zk</samp>&rsquo;,
    168. 

  168. &lsquo;<samp>armv7</samp>&rsquo;, &lsquo;<samp>armv7-a</samp>&rsquo;, &lsquo;<samp>armv7-m</samp>&rsquo;, &lsquo;<samp>armv7-r</samp>&rsquo;, &lsquo;<samp>armv7e-m</samp>&rsquo;,
    169. 

  169. &lsquo;<samp>armv7ve</samp>&rsquo;, &lsquo;<samp>armv8-a</samp>&rsquo;, &lsquo;<samp>armv8-a+crc</samp>&rsquo;, &lsquo;<samp>armv8.1-a</samp>&rsquo;,
    170. 

  170. &lsquo;<samp>armv8.1-a+crc</samp>&rsquo;, &lsquo;<samp>armv8-m.base</samp>&rsquo;, &lsquo;<samp>armv8-m.main</samp>&rsquo;,
    171. 

  171. &lsquo;<samp>armv8-m.main+dsp</samp>&rsquo;, &lsquo;<samp>iwmmxt</samp>&rsquo;, &lsquo;<samp>iwmmxt2</samp>&rsquo;.
    172. 

  172. </p>
    173. 

  173. <p>Architecture revisions older than &lsquo;<samp>armv4t</samp>&rsquo; are deprecated.
    174. 

  174. </p>
    175. 

  175. <p><samp>-march=armv6s-m</samp> is the &lsquo;<samp>armv6-m</samp>&rsquo; architecture with support for
    176. 

  176. the (now mandatory) SVC instruction.
    177. 

  177. </p>
    178. 

  178. <p><samp>-march=armv6zk</samp> is an alias for &lsquo;<samp>armv6kz</samp>&rsquo;, existing for backwards
    179. 

  179. compatibility.
    180. 

  180. </p>
    181. 

  181. <p><samp>-march=armv7ve</samp> is the &lsquo;<samp>armv7-a</samp>&rsquo; architecture with virtualization
    182. 

  182. extensions.
    183. 

  183. </p>
    184. 

  184. <p><samp>-march=armv8-a+crc</samp> enables code generation for the ARMv8-A
    185. 

  185. architecture together with the optional CRC32 extensions.
    186. 

  186. </p>
    187. 

  187. <p><samp>-march=armv8.1-a</samp> enables compiler support for the ARMv8.1-A
    188. 

  188. architecture.  This also enables the features provided by
    189. 

  189. <samp>-march=armv8-a+crc</samp>.
    190. 

  190. </p>
    191. 

  191. <p><samp>-march=armv8.2-a</samp> enables compiler support for the ARMv8.2-A
    192. 

  192. architecture.  This also enables the features provided by
    193. 

  193. <samp>-march=armv8.1-a</samp>.
    194. 

  194. </p>
    195. 

  195. <p><samp>-march=armv8.2-a+fp16</samp> enables compiler support for the
    196. 

  196. ARMv8.2-A architecture with the optional FP16 instructions extension.
    197. 

  197. This also enables the features provided by <samp>-march=armv8.1-a</samp>
    198. 

  198. and implies <samp>-mfp16-format=ieee</samp>.
    199. 

  199. </p>
    200. 

  200. <p><samp>-march=armv8.2-a+dotprod</samp> enables compiler support for the
    201. 

  201. ARMv8.2-A architecture with the optional Dot Product instructions extension.
    202. 

  202. This also enables the features provided by <samp>-march=armv8.1-a</samp>.
    203. 

  203. </p>
    204. 

  204. <p><samp>-march=armv8.2-a+fp16+dotprod</samp> enables compiler support for the
    205. 

  205. ARMv8.2-A architecture with the optional FP16 and Dot Product instructions
    206. 

  206. extension.  This also enables the features provided by <samp>-march=armv8.1-a</samp>
    207. 

  207. and implies <samp>-mfp16-format=ieee</samp>.
    208. 

  208. </p>
    209. 

  209. <p><samp>-march=native</samp> causes the compiler to auto-detect the architecture
    210. 

  210. of the build computer.  At present, this feature is only supported on
    211. 

  211. GNU/Linux, and not all architectures are recognized.  If the auto-detect
    212. 

  212. is unsuccessful the option has no effect.
    213. 

  213. </p>
    214. 

  214. </dd>
    215. 

  215. <dt><code>-mtune=<var>name</var></code></dt>
    216. 

  216. <dd><a name="index-mtune-3"></a>
    217. 

  217. <p>This option specifies the name of the target ARM processor for
    218. 

  218. which GCC should tune the performance of the code.
    219. 

  219. For some ARM implementations better performance can be obtained by using
    220. 

  220. this option.
    221. 

  221. Permissible names are: &lsquo;<samp>arm2</samp>&rsquo;, &lsquo;<samp>arm250</samp>&rsquo;,
    222. 

  222. &lsquo;<samp>arm3</samp>&rsquo;, &lsquo;<samp>arm6</samp>&rsquo;, &lsquo;<samp>arm60</samp>&rsquo;, &lsquo;<samp>arm600</samp>&rsquo;, &lsquo;<samp>arm610</samp>&rsquo;,
    223. 

  223. &lsquo;<samp>arm620</samp>&rsquo;, &lsquo;<samp>arm7</samp>&rsquo;, &lsquo;<samp>arm7m</samp>&rsquo;, &lsquo;<samp>arm7d</samp>&rsquo;, &lsquo;<samp>arm7dm</samp>&rsquo;,
    224. 

  224. &lsquo;<samp>arm7di</samp>&rsquo;, &lsquo;<samp>arm7dmi</samp>&rsquo;, &lsquo;<samp>arm70</samp>&rsquo;, &lsquo;<samp>arm700</samp>&rsquo;,
    225. 

  225. &lsquo;<samp>arm700i</samp>&rsquo;, &lsquo;<samp>arm710</samp>&rsquo;, &lsquo;<samp>arm710c</samp>&rsquo;, &lsquo;<samp>arm7100</samp>&rsquo;,
    226. 

  226. &lsquo;<samp>arm720</samp>&rsquo;,
    227. 

  227. &lsquo;<samp>arm7500</samp>&rsquo;, &lsquo;<samp>arm7500fe</samp>&rsquo;, &lsquo;<samp>arm7tdmi</samp>&rsquo;, &lsquo;<samp>arm7tdmi-s</samp>&rsquo;,
    228. 

  228. &lsquo;<samp>arm710t</samp>&rsquo;, &lsquo;<samp>arm720t</samp>&rsquo;, &lsquo;<samp>arm740t</samp>&rsquo;,
    229. 

  229. &lsquo;<samp>strongarm</samp>&rsquo;, &lsquo;<samp>strongarm110</samp>&rsquo;, &lsquo;<samp>strongarm1100</samp>&rsquo;,
    230. 

  230. &lsquo;<samp>strongarm1110</samp>&rsquo;,
    231. 

  231. &lsquo;<samp>arm8</samp>&rsquo;, &lsquo;<samp>arm810</samp>&rsquo;, &lsquo;<samp>arm9</samp>&rsquo;, &lsquo;<samp>arm9e</samp>&rsquo;, &lsquo;<samp>arm920</samp>&rsquo;,
    232. 

  232. &lsquo;<samp>arm920t</samp>&rsquo;, &lsquo;<samp>arm922t</samp>&rsquo;, &lsquo;<samp>arm946e-s</samp>&rsquo;, &lsquo;<samp>arm966e-s</samp>&rsquo;,
    233. 

  233. &lsquo;<samp>arm968e-s</samp>&rsquo;, &lsquo;<samp>arm926ej-s</samp>&rsquo;, &lsquo;<samp>arm940t</samp>&rsquo;, &lsquo;<samp>arm9tdmi</samp>&rsquo;,
    234. 

  234. &lsquo;<samp>arm10tdmi</samp>&rsquo;, &lsquo;<samp>arm1020t</samp>&rsquo;, &lsquo;<samp>arm1026ej-s</samp>&rsquo;,
    235. 

  235. &lsquo;<samp>arm10e</samp>&rsquo;, &lsquo;<samp>arm1020e</samp>&rsquo;, &lsquo;<samp>arm1022e</samp>&rsquo;,
    236. 

  236. &lsquo;<samp>arm1136j-s</samp>&rsquo;, &lsquo;<samp>arm1136jf-s</samp>&rsquo;, &lsquo;<samp>mpcore</samp>&rsquo;, &lsquo;<samp>mpcorenovfp</samp>&rsquo;,
    237. 

  237. &lsquo;<samp>arm1156t2-s</samp>&rsquo;, &lsquo;<samp>arm1156t2f-s</samp>&rsquo;, &lsquo;<samp>arm1176jz-s</samp>&rsquo;, &lsquo;<samp>arm1176jzf-s</samp>&rsquo;,
    238. 

  238. &lsquo;<samp>generic-armv7-a</samp>&rsquo;, &lsquo;<samp>cortex-a5</samp>&rsquo;, &lsquo;<samp>cortex-a7</samp>&rsquo;, &lsquo;<samp>cortex-a8</samp>&rsquo;,
    239. 

  239. &lsquo;<samp>cortex-a9</samp>&rsquo;, &lsquo;<samp>cortex-a12</samp>&rsquo;, &lsquo;<samp>cortex-a15</samp>&rsquo;, &lsquo;<samp>cortex-a17</samp>&rsquo;,
    240. 

  240. &lsquo;<samp>cortex-a32</samp>&rsquo;, &lsquo;<samp>cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a57</samp>&rsquo;,
    241. 

  241. &lsquo;<samp>cortex-a72</samp>&rsquo;, &lsquo;<samp>cortex-a73</samp>&rsquo;, &lsquo;<samp>cortex-r4</samp>&rsquo;,
    242. 

  242. &lsquo;<samp>cortex-r4f</samp>&rsquo;, &lsquo;<samp>cortex-r5</samp>&rsquo;, &lsquo;<samp>cortex-r7</samp>&rsquo;, &lsquo;<samp>cortex-r8</samp>&rsquo;,
    243. 

  243. &lsquo;<samp>cortex-m33</samp>&rsquo;,
    244. 

  244. &lsquo;<samp>cortex-m23</samp>&rsquo;,
    245. 

  245. &lsquo;<samp>cortex-m7</samp>&rsquo;,
    246. 

  246. &lsquo;<samp>cortex-m4</samp>&rsquo;,
    247. 

  247. &lsquo;<samp>cortex-m3</samp>&rsquo;,
    248. 

  248. &lsquo;<samp>cortex-m1</samp>&rsquo;,
    249. 

  249. &lsquo;<samp>cortex-m0</samp>&rsquo;,
    250. 

  250. &lsquo;<samp>cortex-m0plus</samp>&rsquo;,
    251. 

  251. &lsquo;<samp>cortex-m1.small-multiply</samp>&rsquo;,
    252. 

  252. &lsquo;<samp>cortex-m0.small-multiply</samp>&rsquo;,
    253. 

  253. &lsquo;<samp>cortex-m0plus.small-multiply</samp>&rsquo;,
    254. 

  254. &lsquo;<samp>exynos-m1</samp>&rsquo;,
    255. 

  255. &lsquo;<samp>marvell-pj4</samp>&rsquo;,
    256. 

  256. &lsquo;<samp>xscale</samp>&rsquo;, &lsquo;<samp>iwmmxt</samp>&rsquo;, &lsquo;<samp>iwmmxt2</samp>&rsquo;, &lsquo;<samp>ep9312</samp>&rsquo;,
    257. 

  257. &lsquo;<samp>fa526</samp>&rsquo;, &lsquo;<samp>fa626</samp>&rsquo;,
    258. 

  258. &lsquo;<samp>fa606te</samp>&rsquo;, &lsquo;<samp>fa626te</samp>&rsquo;, &lsquo;<samp>fmp626</samp>&rsquo;, &lsquo;<samp>fa726te</samp>&rsquo;,
    259. 

  259. &lsquo;<samp>xgene1</samp>&rsquo;.
    260. 

  260. </p>
    261. 

  261. <p>Additionally, this option can specify that GCC should tune the performance
    262. 

  262. of the code for a big.LITTLE system.  Permissible names are:
    263. 

  263. &lsquo;<samp>cortex-a15.cortex-a7</samp>&rsquo;, &lsquo;<samp>cortex-a17.cortex-a7</samp>&rsquo;,
    264. 

  264. &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,
    265. 

  265. &lsquo;<samp>cortex-a72.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;.
    266. 

  266. </p>
    267. 

  267. <p><samp>-mtune=generic-<var>arch</var></samp> specifies that GCC should tune the
    268. 

  268. performance for a blend of processors within architecture <var>arch</var>.
    269. 

  269. The aim is to generate code that run well on the current most popular
    270. 

  270. processors, balancing between optimizations that benefit some CPUs in the
    271. 

  271. range, and avoiding performance pitfalls of other CPUs.  The effects of
    272. 

  272. this option may change in future GCC versions as CPU models come and go.
    273. 

  273. </p>
    274. 

  274. <p><samp>-mtune=native</samp> causes the compiler to auto-detect the CPU
    275. 

  275. of the build computer.  At present, this feature is only supported on
    276. 

  276. GNU/Linux, and not all architectures are recognized.  If the auto-detect is
    277. 

  277. unsuccessful the option has no effect.
    278. 

  278. </p>
    279. 

  279. </dd>
    280. 

  280. <dt><code>-mcpu=<var>name</var></code></dt>
    281. 

  281. <dd><a name="index-mcpu-2"></a>
    282. 

  282. <p>This specifies the name of the target ARM processor.  GCC uses this name
    283. 

  283. to derive the name of the target ARM architecture (as if specified
    284. 

  284. by <samp>-march</samp>) and the ARM processor type for which to tune for
    285. 

  285. performance (as if specified by <samp>-mtune</samp>).  Where this option
    286. 

  286. is used in conjunction with <samp>-march</samp> or <samp>-mtune</samp>,
    287. 

  287. those options take precedence over the appropriate part of this option.
    288. 

  288. </p>
    289. 

  289. <p>Permissible names for this option are the same as those for
    290. 

  290. <samp>-mtune</samp>.
    291. 

  291. </p>
    292. 

  292. <p><samp>-mcpu=generic-<var>arch</var></samp> is also permissible, and is
    293. 

  293. equivalent to <samp>-march=<var>arch</var> -mtune=generic-<var>arch</var></samp>.
    294. 

  294. See <samp>-mtune</samp> for more information.
    295. 

  295. </p>
    296. 

  296. <p><samp>-mcpu=native</samp> causes the compiler to auto-detect the CPU
    297. 

  297. of the build computer.  At present, this feature is only supported on
    298. 

  298. GNU/Linux, and not all architectures are recognized.  If the auto-detect
    299. 

  299. is unsuccessful the option has no effect.
    300. 

  300. </p>
    301. 

  301. </dd>
    302. 

  302. <dt><code>-mfpu=<var>name</var></code></dt>
    303. 

  303. <dd><a name="index-mfpu-1"></a>
    304. 

  304. <p>This specifies what floating-point hardware (or hardware emulation) is
    305. 

  305. available on the target.  Permissible names are: &lsquo;<samp>vfpv2</samp>&rsquo;, &lsquo;<samp>vfpv3</samp>&rsquo;,
    306. 

  306. &lsquo;<samp>vfpv3-fp16</samp>&rsquo;, &lsquo;<samp>vfpv3-d16</samp>&rsquo;, &lsquo;<samp>vfpv3-d16-fp16</samp>&rsquo;, &lsquo;<samp>vfpv3xd</samp>&rsquo;,
    307. 

  307. &lsquo;<samp>vfpv3xd-fp16</samp>&rsquo;, &lsquo;<samp>neon-vfpv3</samp>&rsquo;, &lsquo;<samp>neon-fp16</samp>&rsquo;, &lsquo;<samp>vfpv4</samp>&rsquo;,
    308. 

  308. &lsquo;<samp>vfpv4-d16</samp>&rsquo;, &lsquo;<samp>fpv4-sp-d16</samp>&rsquo;, &lsquo;<samp>neon-vfpv4</samp>&rsquo;,
    309. 

  309. &lsquo;<samp>fpv5-d16</samp>&rsquo;, &lsquo;<samp>fpv5-sp-d16</samp>&rsquo;,
    310. 

  310. &lsquo;<samp>fp-armv8</samp>&rsquo;, &lsquo;<samp>neon-fp-armv8</samp>&rsquo; and &lsquo;<samp>crypto-neon-fp-armv8</samp>&rsquo;.
    311. 

  311. Note that &lsquo;<samp>neon</samp>&rsquo; is an alias for &lsquo;<samp>neon-vfpv3</samp>&rsquo; and &lsquo;<samp>vfp</samp>&rsquo;
    312. 

  312. is an alias for &lsquo;<samp>vfpv2</samp>&rsquo;.
    313. 

  313. </p>
    314. 

  314. <p>If <samp>-msoft-float</samp> is specified this specifies the format of
    315. 

  315. floating-point values.
    316. 

  316. </p>
    317. 

  317. <p>If the selected floating-point hardware includes the NEON extension
    318. 

  318. (e.g. <samp>-mfpu</samp>=&lsquo;<samp>neon</samp>&rsquo;), note that floating-point
    319. 

  319. operations are not generated by GCC&rsquo;s auto-vectorization pass unless
    320. 

  320. <samp>-funsafe-math-optimizations</samp> is also specified.  This is
    321. 

  321. because NEON hardware does not fully implement the IEEE 754 standard for
    322. 

  322. floating-point arithmetic (in particular denormal values are treated as
    323. 

  323. zero), so the use of NEON instructions may lead to a loss of precision.
    324. 

  324. </p>
    325. 

  325. <p>You can also set the fpu name at function level by using the <code>target(&quot;fpu=&quot;)</code> function attributes (see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>).
    326. 

  326. </p>
    327. 

  327. </dd>
    328. 

  328. <dt><code>-mfp16-format=<var>name</var></code></dt>
    329. 

  329. <dd><a name="index-mfp16_002dformat"></a>
    330. 

  330. <p>Specify the format of the <code>__fp16</code> half-precision floating-point type.
    331. 

  331. Permissible names are &lsquo;<samp>none</samp>&rsquo;, &lsquo;<samp>ieee</samp>&rsquo;, and &lsquo;<samp>alternative</samp>&rsquo;;
    332. 

  332. the default is &lsquo;<samp>none</samp>&rsquo;, in which case the <code>__fp16</code> type is not
    333. 

  333. defined.  See <a href="Half_002dPrecision.html#Half_002dPrecision">Half-Precision</a>, for more information.
    334. 

  334. </p>
    335. 

  335. </dd>
    336. 

  336. <dt><code>-mstructure-size-boundary=<var>n</var></code></dt>
    337. 

  337. <dd><a name="index-mstructure_002dsize_002dboundary"></a>
    338. 

  338. <p>The sizes of all structures and unions are rounded up to a multiple
    339. 

  339. of the number of bits set by this option.  Permissible values are 8, 32
    340. 

  340. and 64.  The default value varies for different toolchains.  For the COFF
    341. 

  341. targeted toolchain the default value is 8.  A value of 64 is only allowed
    342. 

  342. if the underlying ABI supports it.
    343. 

  343. </p>
    344. 

  344. <p>Specifying a larger number can produce faster, more efficient code, but
    345. 

  345. can also increase the size of the program.  Different values are potentially
    346. 

  346. incompatible.  Code compiled with one value cannot necessarily expect to
    347. 

  347. work with code or libraries compiled with another value, if they exchange
    348. 

  348. information using structures or unions.
    349. 

  349. </p>
    350. 

  350. </dd>
    351. 

  351. <dt><code>-mabort-on-noreturn</code></dt>
    352. 

  352. <dd><a name="index-mabort_002don_002dnoreturn"></a>
    353. 

  353. <p>Generate a call to the function <code>abort</code> at the end of a
    354. 

  354. <code>noreturn</code> function.  It is executed if the function tries to
    355. 

  355. return.
    356. 

  356. </p>
    357. 

  357. </dd>
    358. 

  358. <dt><code>-mlong-calls</code></dt>
    359. 

  359. <dt><code>-mno-long-calls</code></dt>
    360. 

  360. <dd><a name="index-mlong_002dcalls-2"></a>
    361. 

  361. <a name="index-mno_002dlong_002dcalls"></a>
    362. 

  362. <p>Tells the compiler to perform function calls by first loading the
    363. 

  363. address of the function into a register and then performing a subroutine
    364. 

  364. call on this register.  This switch is needed if the target function
    365. 

  365. lies outside of the 64-megabyte addressing range of the offset-based
    366. 

  366. version of subroutine call instruction.
    367. 

  367. </p>
    368. 

  368. <p>Even if this switch is enabled, not all function calls are turned
    369. 

  369. into long calls.  The heuristic is that static functions, functions
    370. 

  370. that have the <code>short_call</code> attribute, functions that are inside
    371. 

  371. the scope of a <code>#pragma no_long_calls</code> directive, and functions whose
    372. 

  372. definitions have already been compiled within the current compilation
    373. 

  373. unit are not turned into long calls.  The exceptions to this rule are
    374. 

  374. that weak function definitions, functions with the <code>long_call</code>
    375. 

  375. attribute or the <code>section</code> attribute, and functions that are within
    376. 

  376. the scope of a <code>#pragma long_calls</code> directive are always
    377. 

  377. turned into long calls.
    378. 

  378. </p>
    379. 

  379. <p>This feature is not enabled by default.  Specifying
    380. 

  380. <samp>-mno-long-calls</samp> restores the default behavior, as does
    381. 

  381. placing the function calls within the scope of a <code>#pragma
    382. 

  382. long_calls_off</code> directive.  Note these switches have no effect on how
    383. 

  383. the compiler generates code to handle function calls via function
    384. 

  384. pointers.
    385. 

  385. </p>
    386. 

  386. </dd>
    387. 

  387. <dt><code>-msingle-pic-base</code></dt>
    388. 

  388. <dd><a name="index-msingle_002dpic_002dbase"></a>
    389. 

  389. <p>Treat the register used for PIC addressing as read-only, rather than
    390. 

  390. loading it in the prologue for each function.  The runtime system is
    391. 

  391. responsible for initializing this register with an appropriate value
    392. 

  392. before execution begins.
    393. 

  393. </p>
    394. 

  394. </dd>
    395. 

  395. <dt><code>-mpic-register=<var>reg</var></code></dt>
    396. 

  396. <dd><a name="index-mpic_002dregister"></a>
    397. 

  397. <p>Specify the register to be used for PIC addressing.
    398. 

  398. For standard PIC base case, the default is any suitable register
    399. 

  399. determined by compiler.  For single PIC base case, the default is
    400. 

  400. &lsquo;<samp>R9</samp>&rsquo; if target is EABI based or stack-checking is enabled,
    401. 

  401. otherwise the default is &lsquo;<samp>R10</samp>&rsquo;.
    402. 

  402. </p>
    403. 

  403. </dd>
    404. 

  404. <dt><code>-mpic-data-is-text-relative</code></dt>
    405. 

  405. <dd><a name="index-mpic_002ddata_002dis_002dtext_002drelative"></a>
    406. 

  406. <p>Assume that the displacement between the text and data segments is fixed
    407. 

  407. at static link time.  This permits using PC-relative addressing
    408. 

  408. operations to access data known to be in the data segment.  For
    409. 

  409. non-VxWorks RTP targets, this option is enabled by default.  When
    410. 

  410. disabled on such targets, it will enable <samp>-msingle-pic-base</samp> by
    411. 

  411. default.
    412. 

  412. </p>
    413. 

  413. </dd>
    414. 

  414. <dt><code>-mpoke-function-name</code></dt>
    415. 

  415. <dd><a name="index-mpoke_002dfunction_002dname"></a>
    416. 

  416. <p>Write the name of each function into the text section, directly
    417. 

  417. preceding the function prologue.  The generated code is similar to this:
    418. 

  418. </p>
    419. 

  419. <div class="smallexample">
    420. 

  420. <pre class="smallexample">     t0
    421. 

  421.          .ascii &quot;arm_poke_function_name&quot;, 0
    422. 

  422.          .align
    423. 

  423.      t1
    424. 

  424.          .word 0xff000000 + (t1 - t0)
    425. 

  425.      arm_poke_function_name
    426. 

  426.          mov     ip, sp
    427. 

  427.          stmfd   sp!, {fp, ip, lr, pc}
    428. 

  428.          sub     fp, ip, #4
    429. 

  429. </pre></div>
    430. 

  430. 

  431. <p>When performing a stack backtrace, code can inspect the value of
    432. 

  432. <code>pc</code> stored at <code>fp + 0</code>.  If the trace function then looks at
    433. 

  433. location <code>pc - 12</code> and the top 8 bits are set, then we know that
    434. 

  434. there is a function name embedded immediately preceding this location
    435. 

  435. and has length <code>((pc[-3]) &amp; 0xff000000)</code>.
    436. 

  436. </p>
    437. 

  437. </dd>
    438. 

  438. <dt><code>-mthumb</code></dt>
    439. 

  439. <dt><code>-marm</code></dt>
    440. 

  440. <dd><a name="index-marm"></a>
    441. 

  441. <a name="index-mthumb"></a>
    442. 

  442. 

  443. <p>Select between generating code that executes in ARM and Thumb
    444. 

  444. states.  The default for most configurations is to generate code
    445. 

  445. that executes in ARM state, but the default can be changed by
    446. 

  446. configuring GCC with the <samp>--with-mode=</samp><var>state</var>
    447. 

  447. configure option.
    448. 

  448. </p>
    449. 

  449. <p>You can also override the ARM and Thumb mode for each function
    450. 

  450. by using the <code>target(&quot;thumb&quot;)</code> and <code>target(&quot;arm&quot;)</code> function attributes
    451. 

  451. (see <a href="ARM-Function-Attributes.html#ARM-Function-Attributes">ARM Function Attributes</a>) or pragmas (see <a href="Function-Specific-Option-Pragmas.html#Function-Specific-Option-Pragmas">Function Specific Option Pragmas</a>).
    452. 

  452. </p>
    453. 

  453. </dd>
    454. 

  454. <dt><code>-mtpcs-frame</code></dt>
    455. 

  455. <dd><a name="index-mtpcs_002dframe"></a>
    456. 

  456. <p>Generate a stack frame that is compliant with the Thumb Procedure Call
    457. 

  457. Standard for all non-leaf functions.  (A leaf function is one that does
    458. 

  458. not call any other functions.)  The default is <samp>-mno-tpcs-frame</samp>.
    459. 

  459. </p>
    460. 

  460. </dd>
    461. 

  461. <dt><code>-mtpcs-leaf-frame</code></dt>
    462. 

  462. <dd><a name="index-mtpcs_002dleaf_002dframe"></a>
    463. 

  463. <p>Generate a stack frame that is compliant with the Thumb Procedure Call
    464. 

  464. Standard for all leaf functions.  (A leaf function is one that does
    465. 

  465. not call any other functions.)  The default is <samp>-mno-apcs-leaf-frame</samp>.
    466. 

  466. </p>
    467. 

  467. </dd>
    468. 

  468. <dt><code>-mcallee-super-interworking</code></dt>
    469. 

  469. <dd><a name="index-mcallee_002dsuper_002dinterworking"></a>
    470. 

  470. <p>Gives all externally visible functions in the file being compiled an ARM
    471. 

  471. instruction set header which switches to Thumb mode before executing the
    472. 

  472. rest of the function.  This allows these functions to be called from
    473. 

  473. non-interworking code.  This option is not valid in AAPCS configurations
    474. 

  474. because interworking is enabled by default.
    475. 

  475. </p>
    476. 

  476. </dd>
    477. 

  477. <dt><code>-mcaller-super-interworking</code></dt>
    478. 

  478. <dd><a name="index-mcaller_002dsuper_002dinterworking"></a>
    479. 

  479. <p>Allows calls via function pointers (including virtual functions) to
    480. 

  480. execute correctly regardless of whether the target code has been
    481. 

  481. compiled for interworking or not.  There is a small overhead in the cost
    482. 

  482. of executing a function pointer if this option is enabled.  This option
    483. 

  483. is not valid in AAPCS configurations because interworking is enabled
    484. 

  484. by default.
    485. 

  485. </p>
    486. 

  486. </dd>
    487. 

  487. <dt><code>-mtp=<var>name</var></code></dt>
    488. 

  488. <dd><a name="index-mtp"></a>
    489. 

  489. <p>Specify the access model for the thread local storage pointer.  The valid
    490. 

  490. models are &lsquo;<samp>soft</samp>&rsquo;, which generates calls to <code>__aeabi_read_tp</code>,
    491. 

  491. &lsquo;<samp>cp15</samp>&rsquo;, which fetches the thread pointer from <code>cp15</code> directly
    492. 

  492. (supported in the arm6k architecture), and &lsquo;<samp>auto</samp>&rsquo;, which uses the
    493. 

  493. best available method for the selected processor.  The default setting is
    494. 

  494. &lsquo;<samp>auto</samp>&rsquo;.
    495. 

  495. </p>
    496. 

  496. </dd>
    497. 

  497. <dt><code>-mtls-dialect=<var>dialect</var></code></dt>
    498. 

  498. <dd><a name="index-mtls_002ddialect"></a>
    499. 

  499. <p>Specify the dialect to use for accessing thread local storage.  Two
    500. 

  500. <var>dialect</var>s are supported&mdash;&lsquo;<samp>gnu</samp>&rsquo; and &lsquo;<samp>gnu2</samp>&rsquo;.  The
    501. 

  501. &lsquo;<samp>gnu</samp>&rsquo; dialect selects the original GNU scheme for supporting
    502. 

  502. local and global dynamic TLS models.  The &lsquo;<samp>gnu2</samp>&rsquo; dialect
    503. 

  503. selects the GNU descriptor scheme, which provides better performance
    504. 

  504. for shared libraries.  The GNU descriptor scheme is compatible with
    505. 

  505. the original scheme, but does require new assembler, linker and
    506. 

  506. library support.  Initial and local exec TLS models are unaffected by
    507. 

  507. this option and always use the original scheme.
    508. 

  508. </p>
    509. 

  509. </dd>
    510. 

  510. <dt><code>-mword-relocations</code></dt>
    511. 

  511. <dd><a name="index-mword_002drelocations"></a>
    512. 

  512. <p>Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).
    513. 

  513. This is enabled by default on targets (uClinux, SymbianOS) where the runtime
    514. 

  514. loader imposes this restriction, and when <samp>-fpic</samp> or <samp>-fPIC</samp>
    515. 

  515. is specified.
    516. 

  516. </p>
    517. 

  517. </dd>
    518. 

  518. <dt><code>-mfix-cortex-m3-ldrd</code></dt>
    519. 

  519. <dd><a name="index-mfix_002dcortex_002dm3_002dldrd"></a>
    520. 

  520. <p>Some Cortex-M3 cores can cause data corruption when <code>ldrd</code> instructions
    521. 

  521. with overlapping destination and base registers are used.  This option avoids
    522. 

  522. generating these instructions.  This option is enabled by default when
    523. 

  523. <samp>-mcpu=cortex-m3</samp> is specified.
    524. 

  524. </p>
    525. 

  525. </dd>
    526. 

  526. <dt><code>-munaligned-access</code></dt>
    527. 

  527. <dt><code>-mno-unaligned-access</code></dt>
    528. 

  528. <dd><a name="index-munaligned_002daccess"></a>
    529. 

  529. <a name="index-mno_002dunaligned_002daccess"></a>
    530. 

  530. <p>Enables (or disables) reading and writing of 16- and 32- bit values
    531. 

  531. from addresses that are not 16- or 32- bit aligned.  By default
    532. 

  532. unaligned access is disabled for all pre-ARMv6, all ARMv6-M and for
    533. 

  533. ARMv8-M Baseline architectures, and enabled for all other
    534. 

  534. architectures.  If unaligned access is not enabled then words in packed
    535. 

  535. data structures are accessed a byte at a time.
    536. 

  536. </p>
    537. 

  537. <p>The ARM attribute <code>Tag_CPU_unaligned_access</code> is set in the
    538. 

  538. generated object file to either true or false, depending upon the
    539. 

  539. setting of this option.  If unaligned access is enabled then the
    540. 

  540. preprocessor symbol <code>__ARM_FEATURE_UNALIGNED</code> is also
    541. 

  541. defined.
    542. 

  542. </p>
    543. 

  543. </dd>
    544. 

  544. <dt><code>-mneon-for-64bits</code></dt>
    545. 

  545. <dd><a name="index-mneon_002dfor_002d64bits"></a>
    546. 

  546. <p>Enables using Neon to handle scalar 64-bits operations. This is
    547. 

  547. disabled by default since the cost of moving data from core registers
    548. 

  548. to Neon is high.
    549. 

  549. </p>
    550. 

  550. </dd>
    551. 

  551. <dt><code>-mslow-flash-data</code></dt>
    552. 

  552. <dd><a name="index-mslow_002dflash_002ddata"></a>
    553. 

  553. <p>Assume loading data from flash is slower than fetching instruction.
    554. 

  554. Therefore literal load is minimized for better performance.
    555. 

  555. This option is only supported when compiling for ARMv7 M-profile and
    556. 

  556. off by default.
    557. 

  557. </p>
    558. 

  558. </dd>
    559. 

  559. <dt><code>-masm-syntax-unified</code></dt>
    560. 

  560. <dd><a name="index-masm_002dsyntax_002dunified"></a>
    561. 

  561. <p>Assume inline assembler is using unified asm syntax.  The default is
    562. 

  562. currently off which implies divided syntax.  This option has no impact
    563. 

  563. on Thumb2. However, this may change in future releases of GCC.
    564. 

  564. Divided syntax should be considered deprecated.
    565. 

  565. </p>
    566. 

  566. </dd>
    567. 

  567. <dt><code>-mrestrict-it</code></dt>
    568. 

  568. <dd><a name="index-mrestrict_002dit"></a>
    569. 

  569. <p>Restricts generation of IT blocks to conform to the rules of ARMv8.
    570. 

  570. IT blocks can only contain a single 16-bit instruction from a select
    571. 

  571. set of instructions. This option is on by default for ARMv8 Thumb mode.
    572. 

  572. </p>
    573. 

  573. </dd>
    574. 

  574. <dt><code>-mprint-tune-info</code></dt>
    575. 

  575. <dd><a name="index-mprint_002dtune_002dinfo"></a>
    576. 

  576. <p>Print CPU tuning information as comment in assembler file.  This is
    577. 

  577. an option used only for regression testing of the compiler and not
    578. 

  578. intended for ordinary use in compiling code.  This option is disabled
    579. 

  579. by default.
    580. 

  580. </p>
    581. 

  581. </dd>
    582. 

  582. <dt><code>-mpure-code</code></dt>
    583. 

  583. <dd><a name="index-mpure_002dcode"></a>
    584. 

  584. <p>Do not allow constant data to be placed in code sections.
    585. 

  585. Additionally, when compiling for ELF object format give all text sections the
    586. 

  586. ELF processor-specific section attribute <code>SHF_ARM_PURECODE</code>.  This option
    587. 

  587. is only available when generating non-pic code for ARMv7-M targets.
    588. 

  588. </p>
    589. 

  589. </dd>
    590. 

  590. <dt><code>-mcmse</code></dt>
    591. 

  591. <dd><a name="index-mcmse"></a>
    592. 

  592. <p>Generate secure code as per the &quot;ARMv8-M Security Extensions: Requirements on
    593. 

  593. Development Tools Engineering Specification&quot;, which can be found on
    594. 

  594. <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf">http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf</a>.
    595. 

  595. </p></dd>
    596. 

  596. </dl>
    597. 

  597. 

  598. <hr>
    599. 

  599. <div class="header">
    600. 

  600. <p>
    601. 

  601. Next: <a href="AVR-Options.html#AVR-Options" accesskey="n" rel="next">AVR Options</a>, Previous: <a href="ARC-Options.html#ARC-Options" accesskey="p" rel="prev">ARC Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
    602. 

  602. </div>
    603. 

  603. 

  604. 

  605. 

  606. </body>
    607. 

  607. </html>
    608.