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<title>Using the GNU Compiler Collection (GCC): AArch64 Options</title>

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<a name="AArch64-Options"></a>
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<p>
Next: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="AArch64-Options-1"></a>
<h4 class="subsection">3.18.1 AArch64 Options</h4>
<a name="index-AArch64-Options"></a>

<p>These options are defined for AArch64 implementations:
</p>
<dl compact="compact">
<dt><code>-mabi=<var>name</var></code></dt>
<dd><a name="index-mabi"></a>
<p>Generate code for the specified data model.  Permissible values
are &lsquo;<samp>ilp32</samp>&rsquo; for SysV-like data model where int, long int and pointers
are 32 bits, and &lsquo;<samp>lp64</samp>&rsquo; for SysV-like data model where int is 32 bits,
but long int and pointers are 64 bits.
</p>
<p>The default depends on the specific target configuration.  Note that
the LP64 and ILP32 ABIs are not link-compatible; you must compile your
entire program with the same ABI, and link with a compatible set of libraries.
</p>
</dd>
<dt><code>-mbig-endian</code></dt>
<dd><a name="index-mbig_002dendian"></a>
<p>Generate big-endian code.  This is the default when GCC is configured for an
&lsquo;<samp>aarch64_be-*-*</samp>&rsquo; target.
</p>
</dd>
<dt><code>-mgeneral-regs-only</code></dt>
<dd><a name="index-mgeneral_002dregs_002donly"></a>
<p>Generate code which uses only the general-purpose registers.  This will prevent
the compiler from using floating-point and Advanced SIMD registers but will not
impose any restrictions on the assembler.
</p>
</dd>
<dt><code>-mlittle-endian</code></dt>
<dd><a name="index-mlittle_002dendian"></a>
<p>Generate little-endian code.  This is the default when GCC is configured for an
&lsquo;<samp>aarch64-*-*</samp>&rsquo; but not an &lsquo;<samp>aarch64_be-*-*</samp>&rsquo; target.
</p>
</dd>
<dt><code>-mcmodel=tiny</code></dt>
<dd><a name="index-mcmodel_003dtiny"></a>
<p>Generate code for the tiny code model.  The program and its statically defined
symbols must be within 1MB of each other.  Programs can be statically or
dynamically linked.
</p>
</dd>
<dt><code>-mcmodel=small</code></dt>
<dd><a name="index-mcmodel_003dsmall"></a>
<p>Generate code for the small code model.  The program and its statically defined
symbols must be within 4GB of each other.  Programs can be statically or
dynamically linked.  This is the default code model.
</p>
</dd>
<dt><code>-mcmodel=large</code></dt>
<dd><a name="index-mcmodel_003dlarge"></a>
<p>Generate code for the large code model.  This makes no assumptions about
addresses and sizes of sections.  Programs can be statically linked only.
</p>
</dd>
<dt><code>-mstrict-align</code></dt>
<dd><a name="index-mstrict_002dalign"></a>
<p>Avoid generating memory accesses that may not be aligned on a natural object
boundary as described in the architecture specification.
</p>
</dd>
<dt><code>-momit-leaf-frame-pointer</code></dt>
<dt><code>-mno-omit-leaf-frame-pointer</code></dt>
<dd><a name="index-momit_002dleaf_002dframe_002dpointer"></a>
<a name="index-mno_002domit_002dleaf_002dframe_002dpointer"></a>
<p>Omit or keep the frame pointer in leaf functions.  The former behavior is the
default.
</p>
</dd>
<dt><code>-mtls-dialect=desc</code></dt>
<dd><a name="index-mtls_002ddialect_003ddesc"></a>
<p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
of TLS variables.  This is the default.
</p>
</dd>
<dt><code>-mtls-dialect=traditional</code></dt>
<dd><a name="index-mtls_002ddialect_003dtraditional"></a>
<p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses
of TLS variables.
</p>
</dd>
<dt><code>-mtls-size=<var>size</var></code></dt>
<dd><a name="index-mtls_002dsize"></a>
<p>Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.
This option requires binutils 2.26 or newer.
</p>
</dd>
<dt><code>-mfix-cortex-a53-835769</code></dt>
<dt><code>-mno-fix-cortex-a53-835769</code></dt>
<dd><a name="index-mfix_002dcortex_002da53_002d835769"></a>
<a name="index-mno_002dfix_002dcortex_002da53_002d835769"></a>
<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
This involves inserting a NOP instruction between memory instructions and
64-bit integer multiply-accumulate instructions.
</p>
</dd>
<dt><code>-mfix-cortex-a53-843419</code></dt>
<dt><code>-mno-fix-cortex-a53-843419</code></dt>
<dd><a name="index-mfix_002dcortex_002da53_002d843419"></a>
<a name="index-mno_002dfix_002dcortex_002da53_002d843419"></a>
<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
This erratum workaround is made at link time and this will only pass the
corresponding flag to the linker.
</p>
</dd>
<dt><code>-mlow-precision-recip-sqrt</code></dt>
<dt><code>-mno-low-precision-recip-sqrt</code></dt>
<dd><a name="index-mlow_002dprecision_002drecip_002dsqrt"></a>
<a name="index-mno_002dlow_002dprecision_002drecip_002dsqrt"></a>
<p>Enable or disable the reciprocal square root approximation.
This option only has an effect if <samp>-ffast-math</samp> or
<samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of reciprocal square root results to about 16 bits for
single precision and to 32 bits for double precision.
</p>
</dd>
<dt><code>-mlow-precision-sqrt</code></dt>
<dt><code>-mno-low-precision-sqrt</code></dt>
<dd><a name="index-_002dmlow_002dprecision_002dsqrt"></a>
<a name="index-_002dmno_002dlow_002dprecision_002dsqrt"></a>
<p>Enable or disable the square root approximation.
This option only has an effect if <samp>-ffast-math</samp> or
<samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of square root results to about 16 bits for
single precision and to 32 bits for double precision.
If enabled, it implies <samp>-mlow-precision-recip-sqrt</samp>.
</p>
</dd>
<dt><code>-mlow-precision-div</code></dt>
<dt><code>-mno-low-precision-div</code></dt>
<dd><a name="index-_002dmlow_002dprecision_002ddiv"></a>
<a name="index-_002dmno_002dlow_002dprecision_002ddiv"></a>
<p>Enable or disable the division approximation.
This option only has an effect if <samp>-ffast-math</samp> or
<samp>-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of division results to about 16 bits for
single precision and to 32 bits for double precision.
</p>
</dd>
<dt><code>-march=<var>name</var></code></dt>
<dd><a name="index-march"></a>
<p>Specify the name of the target architecture and, optionally, one or
more feature modifiers.  This option has the form
<samp>-march=<var>arch</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>.
</p>
<p>The permissible values for <var>arch</var> are &lsquo;<samp>armv8-a</samp>&rsquo;,
&lsquo;<samp>armv8.1-a</samp>&rsquo;, &lsquo;<samp>armv8.2-a</samp>&rsquo;, &lsquo;<samp>armv8.3-a</samp>&rsquo; or <var>native</var>.
</p>
<p>The value &lsquo;<samp>armv8.3-a</samp>&rsquo; implies &lsquo;<samp>armv8.2-a</samp>&rsquo; and enables compiler
support for the ARMv8.3-A architecture extensions.
</p>
<p>The value &lsquo;<samp>armv8.2-a</samp>&rsquo; implies &lsquo;<samp>armv8.1-a</samp>&rsquo; and enables compiler
support for the ARMv8.2-A architecture extensions.
</p>
<p>The value &lsquo;<samp>armv8.1-a</samp>&rsquo; implies &lsquo;<samp>armv8-a</samp>&rsquo; and enables compiler
support for the ARMv8.1-A architecture extension.  In particular, it
enables the &lsquo;<samp>+crc</samp>&rsquo;, &lsquo;<samp>+lse</samp>&rsquo;, and &lsquo;<samp>+rdma</samp>&rsquo; features.
</p>
<p>The value &lsquo;<samp>native</samp>&rsquo; is available on native AArch64 GNU/Linux and
causes the compiler to pick the architecture of the host system.  This
option has no effect if the compiler is unable to recognize the
architecture of the host system,
</p>
<p>The permissible values for <var>feature</var> are listed in the sub-section
on <a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>
Feature Modifiers</a>.  Where conflicting feature modifiers are
specified, the right-most feature is used.
</p>
<p>GCC uses <var>name</var> to determine what kind of instructions it can emit
when generating assembly code.  If <samp>-march</samp> is specified
without either of <samp>-mtune</samp> or <samp>-mcpu</samp> also being
specified, the code is tuned to perform well across a range of target
processors implementing the target architecture.
</p>
</dd>
<dt><code>-mtune=<var>name</var></code></dt>
<dd><a name="index-mtune"></a>
<p>Specify the name of the target processor for which GCC should tune the
performance of the code.  Permissible values for this option are:
&lsquo;<samp>generic</samp>&rsquo;, &lsquo;<samp>cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a57</samp>&rsquo;,
&lsquo;<samp>cortex-a72</samp>&rsquo;, &lsquo;<samp>cortex-a73</samp>&rsquo;, &lsquo;<samp>exynos-m1</samp>&rsquo;, &lsquo;<samp>falkor</samp>&rsquo;,
&lsquo;<samp>qdf24xx</samp>&rsquo;, &lsquo;<samp>xgene1</samp>&rsquo;, &lsquo;<samp>vulcan</samp>&rsquo;, &lsquo;<samp>thunderx</samp>&rsquo;,
&lsquo;<samp>thunderxt88</samp>&rsquo;, &lsquo;<samp>thunderxt88p1</samp>&rsquo;, &lsquo;<samp>thunderxt81</samp>&rsquo;,
&lsquo;<samp>thunderxt83</samp>&rsquo;, &lsquo;<samp>thunderx2t99</samp>&rsquo;, &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;,
&lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a35</samp>&rsquo;,
&lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;, &lsquo;<samp>native</samp>&rsquo;.
</p>
<p>The values &lsquo;<samp>cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp>cortex-a72.cortex-a53</samp>&rsquo;,
&lsquo;<samp>cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp>cortex-a73.cortex-a53</samp>&rsquo;
specify that GCC should tune for a big.LITTLE system.
</p>
<p>Additionally on native AArch64 GNU/Linux systems the value
&lsquo;<samp>native</samp>&rsquo; tunes performance to the host system.  This option has no effect
if the compiler is unable to recognize the processor of the host system.
</p>
<p>Where none of <samp>-mtune=</samp>, <samp>-mcpu=</samp> or <samp>-march=</samp>
are specified, the code is tuned to perform well across a range
of target processors.
</p>
<p>This option cannot be suffixed by feature modifiers.
</p>
</dd>
<dt><code>-mcpu=<var>name</var></code></dt>
<dd><a name="index-mcpu"></a>
<p>Specify the name of the target processor, optionally suffixed by one
or more feature modifiers.  This option has the form
<samp>-mcpu=<var>cpu</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>, where
the permissible values for <var>cpu</var> are the same as those available
for <samp>-mtune</samp>.  The permissible values for <var>feature</var> are
documented in the sub-section on
<a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>
Feature Modifiers</a>.  Where conflicting feature modifiers are
specified, the right-most feature is used.
</p>
<p>GCC uses <var>name</var> to determine what kind of instructions it can emit when
generating assembly code (as if by <samp>-march</samp>) and to determine
the target processor for which to tune for performance (as if
by <samp>-mtune</samp>).  Where this option is used in conjunction
with <samp>-march</samp> or <samp>-mtune</samp>, those options take precedence
over the appropriate part of this option.
</p>
</dd>
<dt><code>-moverride=<var>string</var></code></dt>
<dd><a name="index-moverride"></a>
<p>Override tuning decisions made by the back-end in response to a
<samp>-mtune=</samp> switch.  The syntax, semantics, and accepted values
for <var>string</var> in this option are not guaranteed to be consistent
across releases.
</p>
<p>This option is only intended to be useful when developing GCC.
</p>
</dd>
<dt><code>-mpc-relative-literal-loads</code></dt>
<dt><code>-mno-pc-relative-literal-loads</code></dt>
<dd><a name="index-mpc_002drelative_002dliteral_002dloads"></a>
<a name="index-mno_002dpc_002drelative_002dliteral_002dloads"></a>
<p>Enable or disable PC-relative literal loads.  With this option literal pools are
accessed using a single instruction and emitted after each function.  This
limits the maximum size of functions to 1MB.  This is enabled by default for
<samp>-mcmodel=tiny</samp>.
</p>
</dd>
<dt><code>-msign-return-address=<var>scope</var></code></dt>
<dd><a name="index-msign_002dreturn_002daddress"></a>
<p>Select the function scope on which return address signing will be applied.
Permissible values are &lsquo;<samp>none</samp>&rsquo;, which disables return address signing,
&lsquo;<samp>non-leaf</samp>&rsquo;, which enables pointer signing for functions which are not leaf
functions, and &lsquo;<samp>all</samp>&rsquo;, which enables pointer signing for all functions.  The
default value is &lsquo;<samp>none</samp>&rsquo;.
</p>
</dd>
</dl>

<a name="g_t_002dmarch-and-_002dmcpu-Feature-Modifiers"></a>
<h4 class="subsubsection">3.18.1.1 <samp>-march</samp> and <samp>-mcpu</samp> Feature Modifiers</h4>
<a name="aarch64_002dfeature_002dmodifiers"></a><a name="index-_002dmarch-feature-modifiers"></a>
<a name="index-_002dmcpu-feature-modifiers"></a>
<p>Feature modifiers used with <samp>-march</samp> and <samp>-mcpu</samp> can be any of
the following and their inverses <samp>no<var>feature</var></samp>:
</p>
<dl compact="compact">
<dt>&lsquo;<samp>crc</samp>&rsquo;</dt>
<dd><p>Enable CRC extension.  This is on by default for
<samp>-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp>crypto</samp>&rsquo;</dt>
<dd><p>Enable Crypto extension.  This also enables Advanced SIMD and floating-point
instructions.
</p></dd>
<dt>&lsquo;<samp>fp</samp>&rsquo;</dt>
<dd><p>Enable floating-point instructions.  This is on by default for all possible
values for options <samp>-march</samp> and <samp>-mcpu</samp>.
</p></dd>
<dt>&lsquo;<samp>simd</samp>&rsquo;</dt>
<dd><p>Enable Advanced SIMD instructions.  This also enables floating-point
instructions.  This is on by default for all possible values for options
<samp>-march</samp> and <samp>-mcpu</samp>.
</p></dd>
<dt>&lsquo;<samp>lse</samp>&rsquo;</dt>
<dd><p>Enable Large System Extension instructions.  This is on by default for
<samp>-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp>rdma</samp>&rsquo;</dt>
<dd><p>Enable Round Double Multiply Accumulate instructions.  This is on by default
for <samp>-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp>fp16</samp>&rsquo;</dt>
<dd><p>Enable FP16 extension.  This also enables floating-point instructions.
</p></dd>
<dt>&lsquo;<samp>rcpc</samp>&rsquo;</dt>
<dd><p>Enable the RcPc extension.  This does not change code generation from GCC,
but is passed on to the assembler, enabling inline asm statements to use
instructions from the RcPc extension.
</p></dd>
<dt>&lsquo;<samp>dotprod</samp>&rsquo;</dt>
<dd><p>Enable the Dot Product extension.  This also enables Advanced SIMD instructions.
</p>
</dd>
</dl>

<p>Feature <samp>crypto</samp> implies <samp>simd</samp>, which implies <samp>fp</samp>.
Conversely, <samp>nofp</samp> implies <samp>nosimd</samp>, which implies
<samp>nocrypto</samp>.
</p>
<hr>
<div class="header">
<p>
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