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- <p>
- Next: <a href="i386_002dBugs.html#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="i386_002d16bit.html#i386_002d16bit" accesskey="p" rel="prev">i386-16bit</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
- </div>
- <hr>
- <a name="Specifying-CPU-Architecture"></a>
- <h4 class="subsection">9.15.15 Specifying CPU Architecture</h4>
- <a name="index-arch-directive_002c-i386"></a>
- <a name="index-i386-arch-directive"></a>
- <a name="index-arch-directive_002c-x86_002d64"></a>
- <a name="index-x86_002d64-arch-directive"></a>
- <p><code>as</code> may be told to assemble for a particular CPU
- (sub-)architecture with the <code>.arch <var>cpu_type</var></code> directive. This
- directive enables a warning when gas detects an instruction that is not
- supported on the CPU specified. The choices for <var>cpu_type</var> are:
- </p>
- <table>
- <tr><td width="20%">‘<samp>i8086</samp>’</td><td width="20%">‘<samp>i186</samp>’</td><td width="20%">‘<samp>i286</samp>’</td><td width="20%">‘<samp>i386</samp>’</td></tr>
- <tr><td width="20%">‘<samp>i486</samp>’</td><td width="20%">‘<samp>i586</samp>’</td><td width="20%">‘<samp>i686</samp>’</td><td width="20%">‘<samp>pentium</samp>’</td></tr>
- <tr><td width="20%">‘<samp>pentiumpro</samp>’</td><td width="20%">‘<samp>pentiumii</samp>’</td><td width="20%">‘<samp>pentiumiii</samp>’</td><td width="20%">‘<samp>pentium4</samp>’</td></tr>
- <tr><td width="20%">‘<samp>prescott</samp>’</td><td width="20%">‘<samp>nocona</samp>’</td><td width="20%">‘<samp>core</samp>’</td><td width="20%">‘<samp>core2</samp>’</td></tr>
- <tr><td width="20%">‘<samp>corei7</samp>’</td><td width="20%">‘<samp>l1om</samp>’</td><td width="20%">‘<samp>k1om</samp>’ ‘<samp>iamcu</samp>’</td></tr>
- <tr><td width="20%">‘<samp>k6</samp>’</td><td width="20%">‘<samp>k6_2</samp>’</td><td width="20%">‘<samp>athlon</samp>’</td><td width="20%">‘<samp>k8</samp>’</td></tr>
- <tr><td width="20%">‘<samp>amdfam10</samp>’</td><td width="20%">‘<samp>bdver1</samp>’</td><td width="20%">‘<samp>bdver2</samp>’</td><td width="20%">‘<samp>bdver3</samp>’</td></tr>
- <tr><td width="20%">‘<samp>bdver4</samp>’</td><td width="20%">‘<samp>znver1</samp>’</td><td width="20%">‘<samp>btver1</samp>’</td><td width="20%">‘<samp>btver2</samp>’</td></tr>
- <tr><td width="20%">‘<samp>generic32</samp>’</td><td width="20%">‘<samp>generic64</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.mmx</samp>’</td><td width="20%">‘<samp>.sse</samp>’</td><td width="20%">‘<samp>.sse2</samp>’</td><td width="20%">‘<samp>.sse3</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.ssse3</samp>’</td><td width="20%">‘<samp>.sse4.1</samp>’</td><td width="20%">‘<samp>.sse4.2</samp>’</td><td width="20%">‘<samp>.sse4</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.avx</samp>’</td><td width="20%">‘<samp>.vmx</samp>’</td><td width="20%">‘<samp>.smx</samp>’</td><td width="20%">‘<samp>.ept</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.clflush</samp>’</td><td width="20%">‘<samp>.movbe</samp>’</td><td width="20%">‘<samp>.xsave</samp>’</td><td width="20%">‘<samp>.xsaveopt</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.aes</samp>’</td><td width="20%">‘<samp>.pclmul</samp>’</td><td width="20%">‘<samp>.fma</samp>’</td><td width="20%">‘<samp>.fsgsbase</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.rdrnd</samp>’</td><td width="20%">‘<samp>.f16c</samp>’</td><td width="20%">‘<samp>.avx2</samp>’</td><td width="20%">‘<samp>.bmi2</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.lzcnt</samp>’</td><td width="20%">‘<samp>.invpcid</samp>’</td><td width="20%">‘<samp>.vmfunc</samp>’</td><td width="20%">‘<samp>.hle</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.rtm</samp>’</td><td width="20%">‘<samp>.adx</samp>’</td><td width="20%">‘<samp>.rdseed</samp>’</td><td width="20%">‘<samp>.prfchw</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.smap</samp>’</td><td width="20%">‘<samp>.mpx</samp>’</td><td width="20%">‘<samp>.sha</samp>’</td><td width="20%">‘<samp>.prefetchwt1</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.clflushopt</samp>’</td><td width="20%">‘<samp>.xsavec</samp>’</td><td width="20%">‘<samp>.xsaves</samp>’</td><td width="20%">‘<samp>.se1</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.avx512f</samp>’</td><td width="20%">‘<samp>.avx512cd</samp>’</td><td width="20%">‘<samp>.avx512er</samp>’</td><td width="20%">‘<samp>.avx512pf</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.avx512vl</samp>’</td><td width="20%">‘<samp>.avx512bw</samp>’</td><td width="20%">‘<samp>.avx512dq</samp>’</td><td width="20%">‘<samp>.avx512ifma</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.avx512vbmi</samp>’</td><td width="20%">‘<samp>.avx512_4fmaps</samp>’</td><td width="20%">‘<samp>.avx512_4vnniw</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.avx512_vpopcntdq</samp>’</td><td width="20%">‘<samp>.clwb</samp>’</td><td width="20%">‘<samp>.rdpid</samp>’</td><td width="20%">‘<samp>.ptwrite</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.3dnow</samp>’</td><td width="20%">‘<samp>.3dnowa</samp>’</td><td width="20%">‘<samp>.sse4a</samp>’</td><td width="20%">‘<samp>.sse5</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.syscall</samp>’</td><td width="20%">‘<samp>.rdtscp</samp>’</td><td width="20%">‘<samp>.svme</samp>’</td><td width="20%">‘<samp>.abm</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.lwp</samp>’</td><td width="20%">‘<samp>.fma4</samp>’</td><td width="20%">‘<samp>.xop</samp>’</td><td width="20%">‘<samp>.cx16</samp>’</td></tr>
- <tr><td width="20%">‘<samp>.padlock</samp>’</td><td width="20%">‘<samp>.clzero</samp>’</td><td width="20%">‘<samp>.mwaitx</samp>’</td></tr>
- </table>
- <p>Apart from the warning, there are only two other effects on
- <code>as</code> operation; Firstly, if you specify a CPU other than
- ‘<samp>i486</samp>’, then shift by one instructions such as ‘<samp>sarl $1, %eax</samp>’
- will automatically use a two byte opcode sequence. The larger three
- byte opcode sequence is used on the 486 (and when no architecture is
- specified) because it executes faster on the 486. Note that you can
- explicitly request the two byte opcode by writing ‘<samp>sarl %eax</samp>’.
- Secondly, if you specify ‘<samp>i8086</samp>’, ‘<samp>i186</samp>’, or ‘<samp>i286</samp>’,
- <em>and</em> ‘<samp>.code16</samp>’ or ‘<samp>.code16gcc</samp>’ then byte offset
- conditional jumps will be promoted when necessary to a two instruction
- sequence consisting of a conditional jump of the opposite sense around
- an unconditional jump to the target.
- </p>
- <p>Following the CPU architecture (but not a sub-architecture, which are those
- starting with a dot), you may specify ‘<samp>jumps</samp>’ or ‘<samp>nojumps</samp>’ to
- control automatic promotion of conditional jumps. ‘<samp>jumps</samp>’ is the
- default, and enables jump promotion; All external jumps will be of the long
- variety, and file-local jumps will be promoted as necessary.
- (see <a href="i386_002dJumps.html#i386_002dJumps">i386-Jumps</a>) ‘<samp>nojumps</samp>’ leaves external conditional jumps as
- byte offset jumps, and warns about file-local conditional jumps that
- <code>as</code> promotes.
- Unconditional jumps are treated as for ‘<samp>jumps</samp>’.
- </p>
- <p>For example
- </p>
- <div class="smallexample">
- <pre class="smallexample"> .arch i8086,nojumps
- </pre></div>
- <hr>
- <div class="header">
- <p>
- Next: <a href="i386_002dBugs.html#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="i386_002d16bit.html#i386_002d16bit" accesskey="p" rel="prev">i386-16bit</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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