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<title>Using as: SH Floating Point</title>

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<a name="SH-Floating-Point"></a>
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Next: <a href="SH-Directives.html#SH-Directives" accesskey="n" rel="next">SH Directives</a>, Previous: <a href="SH-Syntax.html#SH-Syntax" accesskey="p" rel="prev">SH Syntax</a>, Up: <a href="SH_002dDependent.html#SH_002dDependent" accesskey="u" rel="up">SH-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<a name="Floating-Point-15"></a>
<h4 class="subsection">9.41.3 Floating Point</h4>

<a name="index-floating-point_002c-SH-_0028IEEE_0029"></a>
<a name="index-SH-floating-point-_0028IEEE_0029"></a>
<p>SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use <code>.float</code> directive to generate <small>IEEE</small>
floating-point numbers.
</p>
<p>SH2E and SH3E support single-precision floating point calculations as
well as entirely PCAPI compatible emulation of double-precision
floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.
</p>
<p>In addition to single-precision and double-precision floating-point
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
engine that enables 32-bit floating-point data to be processed 128
bits at a time. It also supports 4 * 4 array operations and inner
product operations. Also, a superscalar architecture is employed that
enables simultaneous execution of two instructions (including FPU
instructions), providing performance of up to twice that of
conventional architectures at the same frequency.
</p>


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