Opcodes-for-i860.html 6.2 KB

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  63. <a name="i860-Opcodes"></a>
  64. <h4 class="subsection">9.16.4 i860 Opcodes</h4>
  65. <a name="index-opcodes_002c-i860"></a>
  66. <a name="index-i860-opcodes"></a>
  67. <p>All of the Intel i860XR and i860XP machine instructions are supported. Please see
  68. either <em>i860 Microprocessor Programmer&rsquo;s Reference Manual</em> or <em>i860 Microprocessor Architecture</em> for more information.
  69. </p><a name="Other-instruction-support-_0028pseudo_002dinstructions_0029"></a>
  70. <h4 class="subsubsection">9.16.4.1 Other instruction support (pseudo-instructions)</h4>
  71. <p>For compatibility with some other i860 assemblers, a number of
  72. pseudo-instructions are supported. While these are supported, they are
  73. a very undesirable feature that should be avoided &ndash; in particular, when
  74. they result in an expansion to multiple actual i860 instructions. Below
  75. are the pseudo-instructions that result in expansions.
  76. </p><ul>
  77. <li> Load large immediate into general register:
  78. <p>The pseudo-instruction <code>mov imm,%rn</code> (where the immediate does
  79. not fit within a signed 16-bit field) will be expanded into:
  80. </p><div class="smallexample">
  81. <pre class="smallexample">orh large_imm@h,%r0,%rn
  82. or large_imm@l,%rn,%rn
  83. </pre></div>
  84. </li><li> Load/store with relocatable address expression:
  85. <p>For example, the pseudo-instruction <code>ld.b addr_exp(%rx),%rn</code>
  86. will be expanded into:
  87. </p><div class="smallexample">
  88. <pre class="smallexample">orh addr_exp@ha,%rx,%r31
  89. ld.l addr_exp@l(%r31),%rn
  90. </pre></div>
  91. <p>The analogous expansions apply to <code>ld.x, st.x, fld.x, pfld.x, fst.x</code>, and <code>pst.x</code> as well.
  92. </p></li><li> Signed large immediate with add/subtract:
  93. <p>If any of the arithmetic operations <code>adds, addu, subs, subu</code> are used
  94. with an immediate larger than 16-bits (signed), then they will be expanded.
  95. For instance, the pseudo-instruction <code>adds large_imm,%rx,%rn</code> expands to:
  96. </p><div class="smallexample">
  97. <pre class="smallexample">orh large_imm@h,%r0,%r31
  98. or large_imm@l,%r31,%r31
  99. adds %r31,%rx,%rn
  100. </pre></div>
  101. </li><li> Unsigned large immediate with logical operations:
  102. <p>Logical operations (<code>or, andnot, or, xor</code>) also result in expansions.
  103. The pseudo-instruction <code>or large_imm,%rx,%rn</code> results in:
  104. </p><div class="smallexample">
  105. <pre class="smallexample">orh large_imm@h,%rx,%r31
  106. or large_imm@l,%r31,%rn
  107. </pre></div>
  108. <p>Similarly for the others, except for <code>and</code> which expands to:
  109. </p><div class="smallexample">
  110. <pre class="smallexample">andnot (-1 - large_imm)@h,%rx,%r31
  111. andnot (-1 - large_imm)@l,%r31,%rn
  112. </pre></div>
  113. </li></ul>
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