MIPS-FP-ABI-Variants.html 6.2 KB

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  57. <a name="MIPS-FP-ABI-Variants"></a>
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  59. <p>
  60. Next: <a href="MIPS-FP-ABI-Selection.html#MIPS-FP-ABI-Selection" accesskey="n" rel="next">MIPS FP ABI Selection</a>, Previous: <a href="MIPS-FP-ABI-History.html#MIPS-FP-ABI-History" accesskey="p" rel="prev">MIPS FP ABI History</a>, Up: <a href="MIPS-FP-ABIs.html#MIPS-FP-ABIs" accesskey="u" rel="up">MIPS FP ABIs</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  63. <a name="Supported-FP-ABIs"></a>
  64. <h4 class="subsubsection">9.27.9.2 Supported FP ABIs</h4>
  65. <p>The supported floating-point ABI variants are:
  66. </p>
  67. <dl compact="compact">
  68. <dt><code>0 - No floating-point</code></dt>
  69. <dd><p>This variant is used to indicate that floating-point is not used within
  70. the module at all and therefore has no impact on the ABI. This is the
  71. default.
  72. </p>
  73. </dd>
  74. <dt><code>1 - Double-precision</code></dt>
  75. <dd><p>This variant indicates that double-precision support is used. For 64-bit
  76. ABIs this means that 64-bit wide floating-point registers are required.
  77. For 32-bit ABIs this means that 32-bit wide floating-point registers are
  78. required and double-precision operations use pairs of registers.
  79. </p>
  80. </dd>
  81. <dt><code>2 - Single-precision</code></dt>
  82. <dd><p>This variant indicates that single-precision support is used. Double
  83. precision operations will be supported via soft-float routines.
  84. </p>
  85. </dd>
  86. <dt><code>3 - Soft-float</code></dt>
  87. <dd><p>This variant indicates that although floating-point support is used all
  88. operations are emulated in software. This means the ABI is modified to
  89. pass all floating-point data in general-purpose registers.
  90. </p>
  91. </dd>
  92. <dt><code>4 - Deprecated</code></dt>
  93. <dd><p>This variant existed as an initial attempt at supporting 64-bit wide
  94. floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
  95. superseded by 5, 6 and 7.
  96. </p>
  97. </dd>
  98. <dt><code>5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU</code></dt>
  99. <dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
  100. code in the module has been designed to operate correctly with either
  101. 32-bit wide or 64-bit wide floating-point registers. Double-precision
  102. support is used. Only O32 currently supports this variant and requires
  103. a minimum architecture of MIPS II.
  104. </p>
  105. </dd>
  106. <dt><code>6 - Double-precision 32-bit FPU, 64-bit FPU</code></dt>
  107. <dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
  108. code in the module requires 64-bit wide floating-point registers.
  109. Double-precision support is used. Only O32 currently supports this
  110. variant and requires a minimum architecture of MIPS32r2.
  111. </p>
  112. </dd>
  113. <dt><code>7 - Double-precision compat 32-bit FPU, 64-bit FPU</code></dt>
  114. <dd><p>This variant is used by 32-bit ABIs to indicate that the floating-point
  115. code in the module requires 64-bit wide floating-point registers.
  116. Double-precision support is used. This differs from the previous ABI
  117. as it restricts use of odd-numbered single-precision registers. Only
  118. O32 currently supports this variant and requires a minimum architecture
  119. of MIPS32r2.
  120. </p></dd>
  121. </dl>
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