Directives_002di860.html 4.7 KB

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  63. <a name="i860-Machine-Directives"></a>
  64. <h4 class="subsection">9.16.3 i860 Machine Directives</h4>
  65. <a name="index-machine-directives_002c-i860"></a>
  66. <a name="index-i860-machine-directives"></a>
  67. <dl compact="compact">
  68. <dd><a name="index-dual-directive_002c-i860"></a>
  69. </dd>
  70. <dt><code>.dual</code></dt>
  71. <dd><p>Enter dual instruction mode. While this directive is supported, the
  72. preferred way to use dual instruction mode is to explicitly code
  73. the dual bit with the <code>d.</code> prefix.
  74. </p></dd>
  75. </dl>
  76. <dl compact="compact">
  77. <dd><a name="index-enddual-directive_002c-i860"></a>
  78. </dd>
  79. <dt><code>.enddual</code></dt>
  80. <dd><p>Exit dual instruction mode. While this directive is supported, the
  81. preferred way to use dual instruction mode is to explicitly code
  82. the dual bit with the <code>d.</code> prefix.
  83. </p></dd>
  84. </dl>
  85. <dl compact="compact">
  86. <dd><a name="index-atmp-directive_002c-i860"></a>
  87. </dd>
  88. <dt><code>.atmp</code></dt>
  89. <dd><p>Change the temporary register used when expanding pseudo operations. The
  90. default register is <code>r31</code>.
  91. </p></dd>
  92. </dl>
  93. <p>The <code>.dual</code>, <code>.enddual</code>, and <code>.atmp</code> directives are available only in the Intel syntax mode.
  94. </p>
  95. <p>Both syntaxes allow for the standard <code>.align</code> directive. However,
  96. the Intel syntax additionally allows keywords for the alignment
  97. parameter: &quot;<code>.align type</code>&quot;, where &lsquo;type&rsquo; is one of <code>.short</code>, <code>.long</code>,
  98. <code>.quad</code>, <code>.single</code>, <code>.double</code> representing alignments of 2, 4,
  99. 16, 4, and 8, respectively.
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