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<a name="Xtensa"></a>
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Previous: <a href="WIN32.html#WIN32" accesskey="p" rel="prev">WIN32</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
<a name="ld-and-Xtensa-Processors"></a>
<h3 class="section">4.17 <code>ld</code> and Xtensa Processors</h3>

<a name="index-Xtensa-processors"></a>
<p>The default <code>ld</code> behavior for Xtensa processors is to interpret
<code>SECTIONS</code> commands so that lists of explicitly named sections in a
specification with a wildcard file will be interleaved when necessary to
keep literal pools within the range of PC-relative load offsets.  For
example, with the command:
</p>
<div class="smallexample">
<pre class="smallexample">SECTIONS
{
  .text : {
    *(.literal .text)
  }
}
</pre></div>

<p><code>ld</code> may interleave some of the <code>.literal</code>
and <code>.text</code> sections from different object files to ensure that the
literal pools are within the range of PC-relative load offsets.  A valid
interleaving might place the <code>.literal</code> sections from an initial
group of files followed by the <code>.text</code> sections of that group of
files.  Then, the <code>.literal</code> sections from the rest of the files
and the <code>.text</code> sections from the rest of the files would follow.
</p>
<a name="index-_002d_002drelax-on-Xtensa"></a>
<a name="index-relaxing-on-Xtensa"></a>
<p>Relaxation is enabled by default for the Xtensa version of <code>ld</code> and
provides two important link-time optimizations.  The first optimization
is to combine identical literal values to reduce code size.  A redundant
literal will be removed and all the <code>L32R</code> instructions that use it
will be changed to reference an identical literal, as long as the
location of the replacement literal is within the offset range of all
the <code>L32R</code> instructions.  The second optimization is to remove
unnecessary overhead from assembler-generated &ldquo;longcall&rdquo; sequences of
<code>L32R</code>/<code>CALLX<var>n</var></code> when the target functions are within
range of direct <code>CALL<var>n</var></code> instructions.
</p>
<p>For each of these cases where an indirect call sequence can be optimized
to a direct call, the linker will change the <code>CALLX<var>n</var></code>
instruction to a <code>CALL<var>n</var></code> instruction, remove the <code>L32R</code>
instruction, and remove the literal referenced by the <code>L32R</code>
instruction if it is not used for anything else.  Removing the
<code>L32R</code> instruction always reduces code size but can potentially
hurt performance by changing the alignment of subsequent branch targets.
By default, the linker will always preserve alignments, either by
switching some instructions between 24-bit encodings and the equivalent
density instructions or by inserting a no-op in place of the <code>L32R</code>
instruction that was removed.  If code size is more important than
performance, the <samp>--size-opt</samp> option can be used to prevent the
linker from widening density instructions or inserting no-ops, except in
a few cases where no-ops are required for correctness.
</p>
<p>The following Xtensa-specific command-line options can be used to
control the linker:
</p>
<a name="index-Xtensa-options"></a>
<dl compact="compact">
<dt><samp>--size-opt</samp></dt>
<dd><p>When optimizing indirect calls to direct calls, optimize for code size
more than performance.  With this option, the linker will not insert
no-ops or widen density instructions to preserve branch target
alignment.  There may still be some cases where no-ops are required to
preserve the correctness of the code.
</p></dd>
</dl>


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