s390-Mnemonics.html 8.7 KB

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  63. <a name="Instruction-Mnemonics"></a>
  64. <h4 class="subsubsection">9.39.3.2 Instruction Mnemonics</h4>
  65. <a name="index-instruction-mnemonics_002c-s390"></a>
  66. <a name="index-s390-instruction-mnemonics"></a>
  67. <p>All instructions documented in the Principles of Operation are supported
  68. with the mnemonic and order of operands as described.
  69. The instruction mnemonic identifies the instruction format
  70. (<a href="s390-Formats.html#s390-Formats">s390 Formats</a>) and the specific operation code for the instruction.
  71. For example, the &lsquo;<samp>lr</samp>&rsquo; mnemonic denotes the instruction format &lsquo;<samp>RR</samp>&rsquo;
  72. with the operation code &lsquo;<samp>0x18</samp>&rsquo;.
  73. </p>
  74. <p>The definition of the various mnemonics follows a scheme, where the first
  75. character usually hint at the type of the instruction:
  76. </p>
  77. <div class="display">
  78. <table>
  79. <tr><td><pre class="display">a</pre></td><td><pre class="display">add instruction, for example &lsquo;<samp>al</samp>&rsquo; for add logical 32-bit</pre></td></tr>
  80. <tr><td><pre class="display">b</pre></td><td><pre class="display">branch instruction, for example &lsquo;<samp>bc</samp>&rsquo; for branch on condition</pre></td></tr>
  81. <tr><td><pre class="display">c</pre></td><td><pre class="display">compare or convert instruction, for example &lsquo;<samp>cr</samp>&rsquo; for compare
  82. register 32-bit</pre></td></tr>
  83. <tr><td><pre class="display">d</pre></td><td><pre class="display">divide instruction, for example &lsquo;<samp>dlr</samp>&rsquo; devide logical register
  84. 64-bit to 32-bit</pre></td></tr>
  85. <tr><td><pre class="display">i</pre></td><td><pre class="display">insert instruction, for example &lsquo;<samp>ic</samp>&rsquo; insert character</pre></td></tr>
  86. <tr><td><pre class="display">l</pre></td><td><pre class="display">load instruction, for example &lsquo;<samp>ltr</samp>&rsquo; load and test register</pre></td></tr>
  87. <tr><td><pre class="display">mv</pre></td><td><pre class="display">move instruction, for example &lsquo;<samp>mvc</samp>&rsquo; move character</pre></td></tr>
  88. <tr><td><pre class="display">m</pre></td><td><pre class="display">multiply instruction, for example &lsquo;<samp>mh</samp>&rsquo; multiply halfword</pre></td></tr>
  89. <tr><td><pre class="display">n</pre></td><td><pre class="display">and instruction, for example &lsquo;<samp>ni</samp>&rsquo; and immediate</pre></td></tr>
  90. <tr><td><pre class="display">o</pre></td><td><pre class="display">or instruction, for example &lsquo;<samp>oc</samp>&rsquo; or character</pre></td></tr>
  91. <tr><td><pre class="display">sla, sll</pre></td><td><pre class="display">shift left single instruction</pre></td></tr>
  92. <tr><td><pre class="display">sra, srl</pre></td><td><pre class="display">shift right single instruction</pre></td></tr>
  93. <tr><td><pre class="display">st</pre></td><td><pre class="display">store instruction, for example &lsquo;<samp>stm</samp>&rsquo; store multiple</pre></td></tr>
  94. <tr><td><pre class="display">s</pre></td><td><pre class="display">subtract instruction, for example &lsquo;<samp>slr</samp>&rsquo; subtract
  95. logical 32-bit</pre></td></tr>
  96. <tr><td><pre class="display">t</pre></td><td><pre class="display">test or translate instruction, of example &lsquo;<samp>tm</samp>&rsquo; test under mask</pre></td></tr>
  97. <tr><td><pre class="display">x</pre></td><td><pre class="display">exclusive or instruction, for example &lsquo;<samp>xc</samp>&rsquo; exclusive or
  98. character</pre></td></tr>
  99. </table>
  100. </div>
  101. <p>Certain characters at the end of the mnemonic may describe a property
  102. of the instruction:
  103. </p>
  104. <div class="display">
  105. <table>
  106. <tr><td><pre class="display">c</pre></td><td><pre class="display">the instruction uses a 8-bit character operand</pre></td></tr>
  107. <tr><td><pre class="display">f</pre></td><td><pre class="display">the instruction extends a 32-bit operand to 64 bit</pre></td></tr>
  108. <tr><td><pre class="display">g</pre></td><td><pre class="display">the operands are treated as 64-bit values</pre></td></tr>
  109. <tr><td><pre class="display">h</pre></td><td><pre class="display">the operand uses a 16-bit halfword operand</pre></td></tr>
  110. <tr><td><pre class="display">i</pre></td><td><pre class="display">the instruction uses an immediate operand</pre></td></tr>
  111. <tr><td><pre class="display">l</pre></td><td><pre class="display">the instruction uses unsigned, logical operands</pre></td></tr>
  112. <tr><td><pre class="display">m</pre></td><td><pre class="display">the instruction uses a mask or operates on multiple values</pre></td></tr>
  113. <tr><td><pre class="display">r</pre></td><td><pre class="display">if r is the last character, the instruction operates on registers</pre></td></tr>
  114. <tr><td><pre class="display">y</pre></td><td><pre class="display">the instruction uses 20-bit displacements</pre></td></tr>
  115. </table>
  116. </div>
  117. <p>There are many exceptions to the scheme outlined in the above lists, in
  118. particular for the priviledged instructions. For non-priviledged
  119. instruction it works quite well, for example the instruction &lsquo;<samp>clgfr</samp>&rsquo;
  120. c: compare instruction, l: unsigned operands, g: 64-bit operands,
  121. f: 32- to 64-bit extension, r: register operands. The instruction compares
  122. an 64-bit value in a register with the zero extended 32-bit value from
  123. a second register.
  124. For a complete list of all mnemonics see appendix B in the Principles
  125. of Operation.
  126. </p>
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