i386_002d16bit.html 6.5 KB

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  59. <p>
  60. Next: <a href="i386_002dArch.html#i386_002dArch" accesskey="n" rel="next">i386-Arch</a>, Previous: <a href="i386_002dTBM.html#i386_002dTBM" accesskey="p" rel="prev">i386-TBM</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  63. <a name="Writing-16_002dbit-Code"></a>
  64. <h4 class="subsection">9.15.14 Writing 16-bit Code</h4>
  65. <a name="index-i386-16_002dbit-code"></a>
  66. <a name="index-16_002dbit-code_002c-i386"></a>
  67. <a name="index-real_002dmode-code_002c-i386"></a>
  68. <a name="index-code16gcc-directive_002c-i386"></a>
  69. <a name="index-code16-directive_002c-i386"></a>
  70. <a name="index-code32-directive_002c-i386"></a>
  71. <a name="index-code64-directive_002c-i386"></a>
  72. <a name="index-code64-directive_002c-x86_002d64"></a>
  73. <p>While <code>as</code> normally writes only &ldquo;pure&rdquo; 32-bit i386 code
  74. or 64-bit x86-64 code depending on the default configuration,
  75. it also supports writing code to run in real mode or in 16-bit protected
  76. mode code segments. To do this, put a &lsquo;<samp>.code16</samp>&rsquo; or
  77. &lsquo;<samp>.code16gcc</samp>&rsquo; directive before the assembly language instructions to
  78. be run in 16-bit mode. You can switch <code>as</code> to writing
  79. 32-bit code with the &lsquo;<samp>.code32</samp>&rsquo; directive or 64-bit code with the
  80. &lsquo;<samp>.code64</samp>&rsquo; directive.
  81. </p>
  82. <p>&lsquo;<samp>.code16gcc</samp>&rsquo; provides experimental support for generating 16-bit
  83. code from gcc, and differs from &lsquo;<samp>.code16</samp>&rsquo; in that &lsquo;<samp>call</samp>&rsquo;,
  84. &lsquo;<samp>ret</samp>&rsquo;, &lsquo;<samp>enter</samp>&rsquo;, &lsquo;<samp>leave</samp>&rsquo;, &lsquo;<samp>push</samp>&rsquo;, &lsquo;<samp>pop</samp>&rsquo;,
  85. &lsquo;<samp>pusha</samp>&rsquo;, &lsquo;<samp>popa</samp>&rsquo;, &lsquo;<samp>pushf</samp>&rsquo;, and &lsquo;<samp>popf</samp>&rsquo; instructions
  86. default to 32-bit size. This is so that the stack pointer is
  87. manipulated in the same way over function calls, allowing access to
  88. function parameters at the same stack offsets as in 32-bit mode.
  89. &lsquo;<samp>.code16gcc</samp>&rsquo; also automatically adds address size prefixes where
  90. necessary to use the 32-bit addressing modes that gcc generates.
  91. </p>
  92. <p>The code which <code>as</code> generates in 16-bit mode will not
  93. necessarily run on a 16-bit pre-80386 processor. To write code that
  94. runs on such a processor, you must refrain from using <em>any</em> 32-bit
  95. constructs which require <code>as</code> to output address or operand
  96. size prefixes.
  97. </p>
  98. <p>Note that writing 16-bit code instructions by explicitly specifying a
  99. prefix or an instruction mnemonic suffix within a 32-bit code section
  100. generates different machine instructions than those generated for a
  101. 16-bit code segment. In a 32-bit code section, the following code
  102. generates the machine opcode bytes &lsquo;<samp>66 6a 04</samp>&rsquo;, which pushes the
  103. value &lsquo;<samp>4</samp>&rsquo; onto the stack, decrementing &lsquo;<samp>%esp</samp>&rsquo; by 2.
  104. </p>
  105. <div class="smallexample">
  106. <pre class="smallexample"> pushw $4
  107. </pre></div>
  108. <p>The same code in a 16-bit code section would generate the machine
  109. opcode bytes &lsquo;<samp>6a 04</samp>&rsquo; (i.e., without the operand size prefix), which
  110. is correct since the processor default operand size is assumed to be 16
  111. bits in a 16-bit code section.
  112. </p>
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