Xtensa-Automatic-Alignment.html 6.2 KB

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  57. <a name="Xtensa-Automatic-Alignment"></a>
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  60. Previous: <a href="Density-Instructions.html#Density-Instructions" accesskey="p" rel="prev">Density Instructions</a>, Up: <a href="Xtensa-Optimizations.html#Xtensa-Optimizations" accesskey="u" rel="up">Xtensa Optimizations</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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  63. <a name="Automatic-Instruction-Alignment"></a>
  64. <h4 class="subsubsection">9.53.3.2 Automatic Instruction Alignment</h4>
  65. <a name="index-alignment-of-LOOP-instructions"></a>
  66. <a name="index-alignment-of-branch-targets"></a>
  67. <a name="index-LOOP-instructions_002c-alignment"></a>
  68. <a name="index-branch-target-alignment"></a>
  69. <p>The Xtensa assembler will automatically align certain instructions, both
  70. to optimize performance and to satisfy architectural requirements.
  71. </p>
  72. <p>As an optimization to improve performance, the assembler attempts to
  73. align branch targets so they do not cross instruction fetch boundaries.
  74. (Xtensa processors can be configured with either 32-bit or 64-bit
  75. instruction fetch widths.) An
  76. instruction immediately following a call is treated as a branch target
  77. in this context, because it will be the target of a return from the
  78. call. This alignment has the potential to reduce branch penalties at
  79. some expense in code size.
  80. This optimization is enabled by default. You can disable it with the
  81. &lsquo;<samp>--no-target-align</samp>&rsquo; command-line option (see <a href="Xtensa-Options.html#Xtensa-Options">Command Line Options</a>).
  82. </p>
  83. <p>The target alignment optimization is done without adding instructions
  84. that could increase the execution time of the program. If there are
  85. density instructions in the code preceding a target, the assembler can
  86. change the target alignment by widening some of those instructions to
  87. the equivalent 24-bit instructions. Extra bytes of padding can be
  88. inserted immediately following unconditional jump and return
  89. instructions.
  90. This approach is usually successful in aligning many, but not all,
  91. branch targets.
  92. </p>
  93. <p>The <code>LOOP</code> family of instructions must be aligned such that the
  94. first instruction in the loop body does not cross an instruction fetch
  95. boundary (e.g., with a 32-bit fetch width, a <code>LOOP</code> instruction
  96. must be on either a 1 or 2 mod 4 byte boundary). The assembler knows
  97. about this restriction and inserts the minimal number of 2 or 3 byte
  98. no-op instructions to satisfy it. When no-op instructions are added,
  99. any label immediately preceding the original loop will be moved in order
  100. to refer to the loop instruction, not the newly generated no-op
  101. instruction. To preserve binary compatibility across processors with
  102. different fetch widths, the assembler conservatively assumes a 32-bit
  103. fetch width when aligning <code>LOOP</code> instructions (except if the first
  104. instruction in the loop is a 64-bit instruction).
  105. </p>
  106. <p>Previous versions of the assembler automatically aligned <code>ENTRY</code>
  107. instructions to 4-byte boundaries, but that alignment is now the
  108. programmer&rsquo;s responsibility.
  109. </p>
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