Options_002di960.html 7.7 KB

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  59. <p>
  60. Next: <a href="Floating-Point_002di960.html#Floating-Point_002di960" accesskey="n" rel="next">Floating Point-i960</a>, Up: <a href="i960_002dDependent.html#i960_002dDependent" accesskey="u" rel="up">i960-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
  61. </div>
  62. <hr>
  63. <a name="i960-Command_002dline-Options"></a>
  64. <h4 class="subsection">9.17.1 i960 Command-line Options</h4>
  65. <a name="index-i960-options"></a>
  66. <a name="index-options_002c-i960"></a>
  67. <dl compact="compact">
  68. <dd>
  69. <a name="index-i960-architecture-options"></a>
  70. <a name="index-architecture-options_002c-i960"></a>
  71. <a name="index-_002dA-options_002c-i960"></a>
  72. </dd>
  73. <dt><code>-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC</code></dt>
  74. <dd><p>Select the 80960 architecture. Instructions or features not supported
  75. by the selected architecture cause fatal errors.
  76. </p>
  77. <p>&lsquo;<samp>-ACA</samp>&rsquo; is equivalent to &lsquo;<samp>-ACA_A</samp>&rsquo;; &lsquo;<samp>-AKC</samp>&rsquo; is equivalent to
  78. &lsquo;<samp>-AMC</samp>&rsquo;. Synonyms are provided for compatibility with other tools.
  79. </p>
  80. <p>If you do not specify any of these options, <code>as</code> generates code
  81. for any instruction or feature that is supported by <em>some</em> version of the
  82. 960 (even if this means mixing architectures!). In principle,
  83. <code>as</code> attempts to deduce the minimal sufficient processor type if
  84. none is specified; depending on the object code format, the processor type may
  85. be recorded in the object file. If it is critical that the <code>as</code>
  86. output match a specific architecture, specify that architecture explicitly.
  87. </p>
  88. <a name="index-_002db-option_002c-i960"></a>
  89. <a name="index-branch-recording_002c-i960"></a>
  90. <a name="index-i960-branch-recording"></a>
  91. </dd>
  92. <dt><code>-b</code></dt>
  93. <dd><p>Add code to collect information about conditional branches taken, for
  94. later optimization using branch prediction bits. (The conditional branch
  95. instructions have branch prediction bits in the CA, CB, and CC
  96. architectures.) If <var>BR</var> represents a conditional branch instruction,
  97. the following represents the code generated by the assembler when
  98. &lsquo;<samp>-b</samp>&rsquo; is specified:
  99. </p>
  100. <div class="smallexample">
  101. <pre class="smallexample"> call <var>increment routine</var>
  102. .word 0 # pre-counter
  103. Label: <var>BR</var>
  104. call <var>increment routine</var>
  105. .word 0 # post-counter
  106. </pre></div>
  107. <p>The counter following a branch records the number of times that branch
  108. was <em>not</em> taken; the difference between the two counters is the
  109. number of times the branch <em>was</em> taken.
  110. </p>
  111. <a name="index-gbr960_002c-i960-postprocessor"></a>
  112. <a name="index-branch-statistics-table_002c-i960"></a>
  113. <p>A table of every such <code>Label</code> is also generated, so that the
  114. external postprocessor <code>gbr960</code> (supplied by Intel) can locate all
  115. the counters. This table is always labeled &lsquo;<samp>__BRANCH_TABLE__</samp>&rsquo;;
  116. this is a local symbol to permit collecting statistics for many separate
  117. object files. The table is word aligned, and begins with a two-word
  118. header. The first word, initialized to 0, is used in maintaining linked
  119. lists of branch tables. The second word is a count of the number of
  120. entries in the table, which follow immediately: each is a word, pointing
  121. to one of the labels illustrated above.
  122. </p>
  123. <p>The first word of the header is used to locate multiple branch tables,
  124. since each object file may contain one. Normally the links are
  125. maintained with a call to an initialization routine, placed at the
  126. beginning of each function in the file. The <small>GNU</small> C compiler
  127. generates these calls automatically when you give it a &lsquo;<samp>-b</samp>&rsquo; option.
  128. For further details, see the documentation of &lsquo;<samp>gbr960</samp>&rsquo;.
  129. </p>
  130. <a name="index-_002dno_002drelax-option_002c-i960"></a>
  131. </dd>
  132. <dt><code>-no-relax</code></dt>
  133. <dd><p>Normally, Compare-and-Branch instructions with targets that require
  134. displacements greater than 13 bits (or that have external targets) are
  135. replaced with the corresponding compare (or &lsquo;<samp>chkbit</samp>&rsquo;) and branch
  136. instructions. You can use the &lsquo;<samp>-no-relax</samp>&rsquo; option to specify that
  137. <code>as</code> should generate errors instead, if the target displacement
  138. is larger than 13 bits.
  139. </p>
  140. <p>This option does not affect the Compare-and-Jump instructions; the code
  141. emitted for them is <em>always</em> adjusted when necessary (depending on
  142. displacement size), regardless of whether you use &lsquo;<samp>-no-relax</samp>&rsquo;.
  143. </p></dd>
  144. </dl>
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