v4l2-dv-timings.h 31 KB

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  1. /*
  2. * V4L2 DV timings header.
  3. *
  4. * Copyright (C) 2012-2016 Hans Verkuil <hans.verkuil@cisco.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. */
  15. #ifndef _V4L2_DV_TIMINGS_H
  16. #define _V4L2_DV_TIMINGS_H
  17. #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
  18. /* Sadly gcc versions older than 4.6 have a bug in how they initialize
  19. anonymous unions where they require additional curly brackets.
  20. This violates the C1x standard. This workaround adds the curly brackets
  21. if needed. */
  22. #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  23. { .bt = { _width , ## args } }
  24. #else
  25. #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  26. .bt = { _width , ## args }
  27. #endif
  28. /* CEA-861-F timings (i.e. standard HDTV timings) */
  29. #define V4L2_DV_BT_CEA_640X480P59_94 { \
  30. .type = V4L2_DV_BT_656_1120, \
  31. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  32. 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
  33. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  34. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
  35. }
  36. /* Note: these are the nominal timings, for HDMI links this format is typically
  37. * double-clocked to meet the minimum pixelclock requirements. */
  38. #define V4L2_DV_BT_CEA_720X480I59_94 { \
  39. .type = V4L2_DV_BT_656_1120, \
  40. V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
  41. 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
  42. V4L2_DV_BT_STD_CEA861, \
  43. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  44. V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
  45. { 4, 3 }, 6) \
  46. }
  47. #define V4L2_DV_BT_CEA_720X480P59_94 { \
  48. .type = V4L2_DV_BT_656_1120, \
  49. V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
  50. 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
  51. V4L2_DV_BT_STD_CEA861, \
  52. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
  53. V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
  54. }
  55. /* Note: these are the nominal timings, for HDMI links this format is typically
  56. * double-clocked to meet the minimum pixelclock requirements. */
  57. #define V4L2_DV_BT_CEA_720X576I50 { \
  58. .type = V4L2_DV_BT_656_1120, \
  59. V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
  60. 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
  61. V4L2_DV_BT_STD_CEA861, \
  62. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  63. V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
  64. { 4, 3 }, 21) \
  65. }
  66. #define V4L2_DV_BT_CEA_720X576P50 { \
  67. .type = V4L2_DV_BT_656_1120, \
  68. V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
  69. 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
  70. V4L2_DV_BT_STD_CEA861, \
  71. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
  72. V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
  73. }
  74. #define V4L2_DV_BT_CEA_1280X720P24 { \
  75. .type = V4L2_DV_BT_656_1120, \
  76. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  77. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  78. 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  79. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  80. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
  81. }
  82. #define V4L2_DV_BT_CEA_1280X720P25 { \
  83. .type = V4L2_DV_BT_656_1120, \
  84. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  85. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  86. 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
  87. V4L2_DV_BT_STD_CEA861, \
  88. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
  89. }
  90. #define V4L2_DV_BT_CEA_1280X720P30 { \
  91. .type = V4L2_DV_BT_656_1120, \
  92. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  93. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  94. 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  95. V4L2_DV_BT_STD_CEA861, \
  96. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  97. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
  98. }
  99. #define V4L2_DV_BT_CEA_1280X720P50 { \
  100. .type = V4L2_DV_BT_656_1120, \
  101. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  102. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  103. 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
  104. V4L2_DV_BT_STD_CEA861, \
  105. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
  106. }
  107. #define V4L2_DV_BT_CEA_1280X720P60 { \
  108. .type = V4L2_DV_BT_656_1120, \
  109. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  110. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  111. 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
  112. V4L2_DV_BT_STD_CEA861, \
  113. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  114. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
  115. }
  116. #define V4L2_DV_BT_CEA_1920X1080P24 { \
  117. .type = V4L2_DV_BT_656_1120, \
  118. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  119. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  120. 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
  121. V4L2_DV_BT_STD_CEA861, \
  122. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  123. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
  124. }
  125. #define V4L2_DV_BT_CEA_1920X1080P25 { \
  126. .type = V4L2_DV_BT_656_1120, \
  127. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  128. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  129. 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
  130. V4L2_DV_BT_STD_CEA861, \
  131. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
  132. }
  133. #define V4L2_DV_BT_CEA_1920X1080P30 { \
  134. .type = V4L2_DV_BT_656_1120, \
  135. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  136. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  137. 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
  138. V4L2_DV_BT_STD_CEA861, \
  139. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  140. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
  141. }
  142. #define V4L2_DV_BT_CEA_1920X1080I50 { \
  143. .type = V4L2_DV_BT_656_1120, \
  144. V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
  145. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  146. 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
  147. V4L2_DV_BT_STD_CEA861, \
  148. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  149. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
  150. }
  151. #define V4L2_DV_BT_CEA_1920X1080P50 { \
  152. .type = V4L2_DV_BT_656_1120, \
  153. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  154. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  155. 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
  156. V4L2_DV_BT_STD_CEA861, \
  157. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
  158. }
  159. #define V4L2_DV_BT_CEA_1920X1080I60 { \
  160. .type = V4L2_DV_BT_656_1120, \
  161. V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
  162. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  163. 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
  164. V4L2_DV_BT_STD_CEA861, \
  165. V4L2_DV_FL_CAN_REDUCE_FPS | \
  166. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  167. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
  168. }
  169. #define V4L2_DV_BT_CEA_1920X1080P60 { \
  170. .type = V4L2_DV_BT_656_1120, \
  171. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  172. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  173. 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
  174. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  175. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  176. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
  177. }
  178. #define V4L2_DV_BT_CEA_3840X2160P24 { \
  179. .type = V4L2_DV_BT_656_1120, \
  180. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  181. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  182. 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
  183. V4L2_DV_BT_STD_CEA861, \
  184. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  185. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  186. { 0, 0 }, 93, 3) \
  187. }
  188. #define V4L2_DV_BT_CEA_3840X2160P25 { \
  189. .type = V4L2_DV_BT_656_1120, \
  190. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  191. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  192. 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
  193. V4L2_DV_BT_STD_CEA861, \
  194. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
  195. V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
  196. }
  197. #define V4L2_DV_BT_CEA_3840X2160P30 { \
  198. .type = V4L2_DV_BT_656_1120, \
  199. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  200. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  201. 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
  202. V4L2_DV_BT_STD_CEA861, \
  203. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  204. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  205. { 0, 0 }, 95, 1) \
  206. }
  207. #define V4L2_DV_BT_CEA_3840X2160P50 { \
  208. .type = V4L2_DV_BT_656_1120, \
  209. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  210. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  211. 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
  212. V4L2_DV_BT_STD_CEA861, \
  213. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
  214. }
  215. #define V4L2_DV_BT_CEA_3840X2160P60 { \
  216. .type = V4L2_DV_BT_656_1120, \
  217. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  218. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  219. 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
  220. V4L2_DV_BT_STD_CEA861, \
  221. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  222. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
  223. }
  224. #define V4L2_DV_BT_CEA_4096X2160P24 { \
  225. .type = V4L2_DV_BT_656_1120, \
  226. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  227. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  228. 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
  229. V4L2_DV_BT_STD_CEA861, \
  230. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  231. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  232. { 0, 0 }, 98, 4) \
  233. }
  234. #define V4L2_DV_BT_CEA_4096X2160P25 { \
  235. .type = V4L2_DV_BT_656_1120, \
  236. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  237. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  238. 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
  239. V4L2_DV_BT_STD_CEA861, \
  240. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
  241. }
  242. #define V4L2_DV_BT_CEA_4096X2160P30 { \
  243. .type = V4L2_DV_BT_656_1120, \
  244. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  245. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  246. 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
  247. V4L2_DV_BT_STD_CEA861, \
  248. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  249. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
  250. }
  251. #define V4L2_DV_BT_CEA_4096X2160P50 { \
  252. .type = V4L2_DV_BT_656_1120, \
  253. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  254. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  255. 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
  256. V4L2_DV_BT_STD_CEA861, \
  257. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
  258. }
  259. #define V4L2_DV_BT_CEA_4096X2160P60 { \
  260. .type = V4L2_DV_BT_656_1120, \
  261. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  262. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  263. 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
  264. V4L2_DV_BT_STD_CEA861, \
  265. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  266. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
  267. }
  268. /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
  269. #define V4L2_DV_BT_DMT_640X350P85 { \
  270. .type = V4L2_DV_BT_656_1120, \
  271. V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
  272. 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
  273. V4L2_DV_BT_STD_DMT, 0) \
  274. }
  275. #define V4L2_DV_BT_DMT_640X400P85 { \
  276. .type = V4L2_DV_BT_656_1120, \
  277. V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
  278. 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
  279. V4L2_DV_BT_STD_DMT, 0) \
  280. }
  281. #define V4L2_DV_BT_DMT_720X400P85 { \
  282. .type = V4L2_DV_BT_656_1120, \
  283. V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
  284. 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
  285. V4L2_DV_BT_STD_DMT, 0) \
  286. }
  287. /* VGA resolutions */
  288. #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
  289. #define V4L2_DV_BT_DMT_640X480P72 { \
  290. .type = V4L2_DV_BT_656_1120, \
  291. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  292. 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
  293. V4L2_DV_BT_STD_DMT, 0) \
  294. }
  295. #define V4L2_DV_BT_DMT_640X480P75 { \
  296. .type = V4L2_DV_BT_656_1120, \
  297. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  298. 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
  299. V4L2_DV_BT_STD_DMT, 0) \
  300. }
  301. #define V4L2_DV_BT_DMT_640X480P85 { \
  302. .type = V4L2_DV_BT_656_1120, \
  303. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  304. 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
  305. V4L2_DV_BT_STD_DMT, 0) \
  306. }
  307. /* SVGA resolutions */
  308. #define V4L2_DV_BT_DMT_800X600P56 { \
  309. .type = V4L2_DV_BT_656_1120, \
  310. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  311. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  312. 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
  313. V4L2_DV_BT_STD_DMT, 0) \
  314. }
  315. #define V4L2_DV_BT_DMT_800X600P60 { \
  316. .type = V4L2_DV_BT_656_1120, \
  317. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  318. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  319. 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
  320. V4L2_DV_BT_STD_DMT, 0) \
  321. }
  322. #define V4L2_DV_BT_DMT_800X600P72 { \
  323. .type = V4L2_DV_BT_656_1120, \
  324. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  325. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  326. 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
  327. V4L2_DV_BT_STD_DMT, 0) \
  328. }
  329. #define V4L2_DV_BT_DMT_800X600P75 { \
  330. .type = V4L2_DV_BT_656_1120, \
  331. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  332. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  333. 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
  334. V4L2_DV_BT_STD_DMT, 0) \
  335. }
  336. #define V4L2_DV_BT_DMT_800X600P85 { \
  337. .type = V4L2_DV_BT_656_1120, \
  338. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  339. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  340. 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
  341. V4L2_DV_BT_STD_DMT, 0) \
  342. }
  343. #define V4L2_DV_BT_DMT_800X600P120_RB { \
  344. .type = V4L2_DV_BT_656_1120, \
  345. V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
  346. 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
  347. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  348. V4L2_DV_FL_REDUCED_BLANKING) \
  349. }
  350. #define V4L2_DV_BT_DMT_848X480P60 { \
  351. .type = V4L2_DV_BT_656_1120, \
  352. V4L2_INIT_BT_TIMINGS(848, 480, 0, \
  353. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  354. 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
  355. V4L2_DV_BT_STD_DMT, 0) \
  356. }
  357. #define V4L2_DV_BT_DMT_1024X768I43 { \
  358. .type = V4L2_DV_BT_656_1120, \
  359. V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
  360. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  361. 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
  362. V4L2_DV_BT_STD_DMT, 0) \
  363. }
  364. /* XGA resolutions */
  365. #define V4L2_DV_BT_DMT_1024X768P60 { \
  366. .type = V4L2_DV_BT_656_1120, \
  367. V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
  368. 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
  369. V4L2_DV_BT_STD_DMT, 0) \
  370. }
  371. #define V4L2_DV_BT_DMT_1024X768P70 { \
  372. .type = V4L2_DV_BT_656_1120, \
  373. V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
  374. 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
  375. V4L2_DV_BT_STD_DMT, 0) \
  376. }
  377. #define V4L2_DV_BT_DMT_1024X768P75 { \
  378. .type = V4L2_DV_BT_656_1120, \
  379. V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
  380. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  381. 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
  382. V4L2_DV_BT_STD_DMT, 0) \
  383. }
  384. #define V4L2_DV_BT_DMT_1024X768P85 { \
  385. .type = V4L2_DV_BT_656_1120, \
  386. V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
  387. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  388. 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
  389. V4L2_DV_BT_STD_DMT, 0) \
  390. }
  391. #define V4L2_DV_BT_DMT_1024X768P120_RB { \
  392. .type = V4L2_DV_BT_656_1120, \
  393. V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  394. 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
  395. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  396. V4L2_DV_FL_REDUCED_BLANKING) \
  397. }
  398. /* XGA+ resolution */
  399. #define V4L2_DV_BT_DMT_1152X864P75 { \
  400. .type = V4L2_DV_BT_656_1120, \
  401. V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
  402. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  403. 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
  404. V4L2_DV_BT_STD_DMT, 0) \
  405. }
  406. #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
  407. /* WXGA resolutions */
  408. #define V4L2_DV_BT_DMT_1280X768P60_RB { \
  409. .type = V4L2_DV_BT_656_1120, \
  410. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  411. 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
  412. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  413. V4L2_DV_FL_REDUCED_BLANKING) \
  414. }
  415. #define V4L2_DV_BT_DMT_1280X768P60 { \
  416. .type = V4L2_DV_BT_656_1120, \
  417. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  418. 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
  419. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  420. }
  421. #define V4L2_DV_BT_DMT_1280X768P75 { \
  422. .type = V4L2_DV_BT_656_1120, \
  423. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  424. 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
  425. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  426. }
  427. #define V4L2_DV_BT_DMT_1280X768P85 { \
  428. .type = V4L2_DV_BT_656_1120, \
  429. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  430. 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
  431. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  432. }
  433. #define V4L2_DV_BT_DMT_1280X768P120_RB { \
  434. .type = V4L2_DV_BT_656_1120, \
  435. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  436. 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
  437. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  438. V4L2_DV_FL_REDUCED_BLANKING) \
  439. }
  440. #define V4L2_DV_BT_DMT_1280X800P60_RB { \
  441. .type = V4L2_DV_BT_656_1120, \
  442. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
  443. 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
  444. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  445. V4L2_DV_FL_REDUCED_BLANKING) \
  446. }
  447. #define V4L2_DV_BT_DMT_1280X800P60 { \
  448. .type = V4L2_DV_BT_656_1120, \
  449. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  450. 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
  451. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  452. }
  453. #define V4L2_DV_BT_DMT_1280X800P75 { \
  454. .type = V4L2_DV_BT_656_1120, \
  455. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  456. 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
  457. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  458. }
  459. #define V4L2_DV_BT_DMT_1280X800P85 { \
  460. .type = V4L2_DV_BT_656_1120, \
  461. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  462. 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
  463. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  464. }
  465. #define V4L2_DV_BT_DMT_1280X800P120_RB { \
  466. .type = V4L2_DV_BT_656_1120, \
  467. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
  468. 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
  469. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  470. V4L2_DV_FL_REDUCED_BLANKING) \
  471. }
  472. #define V4L2_DV_BT_DMT_1280X960P60 { \
  473. .type = V4L2_DV_BT_656_1120, \
  474. V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
  475. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  476. 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
  477. V4L2_DV_BT_STD_DMT, 0) \
  478. }
  479. #define V4L2_DV_BT_DMT_1280X960P85 { \
  480. .type = V4L2_DV_BT_656_1120, \
  481. V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
  482. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  483. 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
  484. V4L2_DV_BT_STD_DMT, 0) \
  485. }
  486. #define V4L2_DV_BT_DMT_1280X960P120_RB { \
  487. .type = V4L2_DV_BT_656_1120, \
  488. V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
  489. 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
  490. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  491. V4L2_DV_FL_REDUCED_BLANKING) \
  492. }
  493. /* SXGA resolutions */
  494. #define V4L2_DV_BT_DMT_1280X1024P60 { \
  495. .type = V4L2_DV_BT_656_1120, \
  496. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  497. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  498. 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
  499. V4L2_DV_BT_STD_DMT, 0) \
  500. }
  501. #define V4L2_DV_BT_DMT_1280X1024P75 { \
  502. .type = V4L2_DV_BT_656_1120, \
  503. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  504. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  505. 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
  506. V4L2_DV_BT_STD_DMT, 0) \
  507. }
  508. #define V4L2_DV_BT_DMT_1280X1024P85 { \
  509. .type = V4L2_DV_BT_656_1120, \
  510. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  511. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  512. 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
  513. V4L2_DV_BT_STD_DMT, 0) \
  514. }
  515. #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
  516. .type = V4L2_DV_BT_656_1120, \
  517. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
  518. 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
  519. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  520. V4L2_DV_FL_REDUCED_BLANKING) \
  521. }
  522. #define V4L2_DV_BT_DMT_1360X768P60 { \
  523. .type = V4L2_DV_BT_656_1120, \
  524. V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
  525. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  526. 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
  527. V4L2_DV_BT_STD_DMT, 0) \
  528. }
  529. #define V4L2_DV_BT_DMT_1360X768P120_RB { \
  530. .type = V4L2_DV_BT_656_1120, \
  531. V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  532. 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
  533. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  534. V4L2_DV_FL_REDUCED_BLANKING) \
  535. }
  536. #define V4L2_DV_BT_DMT_1366X768P60 { \
  537. .type = V4L2_DV_BT_656_1120, \
  538. V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
  539. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  540. 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
  541. V4L2_DV_BT_STD_DMT, 0) \
  542. }
  543. #define V4L2_DV_BT_DMT_1366X768P60_RB { \
  544. .type = V4L2_DV_BT_656_1120, \
  545. V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
  546. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  547. 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
  548. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  549. }
  550. /* SXGA+ resolutions */
  551. #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
  552. .type = V4L2_DV_BT_656_1120, \
  553. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  554. 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
  555. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  556. V4L2_DV_FL_REDUCED_BLANKING) \
  557. }
  558. #define V4L2_DV_BT_DMT_1400X1050P60 { \
  559. .type = V4L2_DV_BT_656_1120, \
  560. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  561. 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
  562. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  563. }
  564. #define V4L2_DV_BT_DMT_1400X1050P75 { \
  565. .type = V4L2_DV_BT_656_1120, \
  566. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  567. 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
  568. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  569. }
  570. #define V4L2_DV_BT_DMT_1400X1050P85 { \
  571. .type = V4L2_DV_BT_656_1120, \
  572. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  573. 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
  574. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  575. }
  576. #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
  577. .type = V4L2_DV_BT_656_1120, \
  578. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  579. 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
  580. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  581. V4L2_DV_FL_REDUCED_BLANKING) \
  582. }
  583. /* WXGA+ resolutions */
  584. #define V4L2_DV_BT_DMT_1440X900P60_RB { \
  585. .type = V4L2_DV_BT_656_1120, \
  586. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
  587. 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
  588. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  589. V4L2_DV_FL_REDUCED_BLANKING) \
  590. }
  591. #define V4L2_DV_BT_DMT_1440X900P60 { \
  592. .type = V4L2_DV_BT_656_1120, \
  593. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  594. 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
  595. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  596. }
  597. #define V4L2_DV_BT_DMT_1440X900P75 { \
  598. .type = V4L2_DV_BT_656_1120, \
  599. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  600. 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
  601. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  602. }
  603. #define V4L2_DV_BT_DMT_1440X900P85 { \
  604. .type = V4L2_DV_BT_656_1120, \
  605. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  606. 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
  607. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  608. }
  609. #define V4L2_DV_BT_DMT_1440X900P120_RB { \
  610. .type = V4L2_DV_BT_656_1120, \
  611. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
  612. 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
  613. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  614. V4L2_DV_FL_REDUCED_BLANKING) \
  615. }
  616. #define V4L2_DV_BT_DMT_1600X900P60_RB { \
  617. .type = V4L2_DV_BT_656_1120, \
  618. V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
  619. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  620. 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
  621. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  622. }
  623. /* UXGA resolutions */
  624. #define V4L2_DV_BT_DMT_1600X1200P60 { \
  625. .type = V4L2_DV_BT_656_1120, \
  626. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  627. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  628. 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  629. V4L2_DV_BT_STD_DMT, 0) \
  630. }
  631. #define V4L2_DV_BT_DMT_1600X1200P65 { \
  632. .type = V4L2_DV_BT_656_1120, \
  633. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  634. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  635. 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  636. V4L2_DV_BT_STD_DMT, 0) \
  637. }
  638. #define V4L2_DV_BT_DMT_1600X1200P70 { \
  639. .type = V4L2_DV_BT_656_1120, \
  640. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  641. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  642. 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  643. V4L2_DV_BT_STD_DMT, 0) \
  644. }
  645. #define V4L2_DV_BT_DMT_1600X1200P75 { \
  646. .type = V4L2_DV_BT_656_1120, \
  647. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  648. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  649. 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  650. V4L2_DV_BT_STD_DMT, 0) \
  651. }
  652. #define V4L2_DV_BT_DMT_1600X1200P85 { \
  653. .type = V4L2_DV_BT_656_1120, \
  654. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  655. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  656. 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  657. V4L2_DV_BT_STD_DMT, 0) \
  658. }
  659. #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
  660. .type = V4L2_DV_BT_656_1120, \
  661. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  662. 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
  663. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  664. V4L2_DV_FL_REDUCED_BLANKING) \
  665. }
  666. /* WSXGA+ resolutions */
  667. #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
  668. .type = V4L2_DV_BT_656_1120, \
  669. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  670. 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
  671. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  672. V4L2_DV_FL_REDUCED_BLANKING) \
  673. }
  674. #define V4L2_DV_BT_DMT_1680X1050P60 { \
  675. .type = V4L2_DV_BT_656_1120, \
  676. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  677. 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
  678. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  679. }
  680. #define V4L2_DV_BT_DMT_1680X1050P75 { \
  681. .type = V4L2_DV_BT_656_1120, \
  682. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  683. 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
  684. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  685. }
  686. #define V4L2_DV_BT_DMT_1680X1050P85 { \
  687. .type = V4L2_DV_BT_656_1120, \
  688. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  689. 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
  690. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  691. }
  692. #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
  693. .type = V4L2_DV_BT_656_1120, \
  694. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  695. 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
  696. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  697. V4L2_DV_FL_REDUCED_BLANKING) \
  698. }
  699. #define V4L2_DV_BT_DMT_1792X1344P60 { \
  700. .type = V4L2_DV_BT_656_1120, \
  701. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
  702. 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
  703. V4L2_DV_BT_STD_DMT, 0) \
  704. }
  705. #define V4L2_DV_BT_DMT_1792X1344P75 { \
  706. .type = V4L2_DV_BT_656_1120, \
  707. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
  708. 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
  709. V4L2_DV_BT_STD_DMT, 0) \
  710. }
  711. #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
  712. .type = V4L2_DV_BT_656_1120, \
  713. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
  714. 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
  715. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  716. V4L2_DV_FL_REDUCED_BLANKING) \
  717. }
  718. #define V4L2_DV_BT_DMT_1856X1392P60 { \
  719. .type = V4L2_DV_BT_656_1120, \
  720. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
  721. 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
  722. V4L2_DV_BT_STD_DMT, 0) \
  723. }
  724. #define V4L2_DV_BT_DMT_1856X1392P75 { \
  725. .type = V4L2_DV_BT_656_1120, \
  726. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
  727. 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
  728. V4L2_DV_BT_STD_DMT, 0) \
  729. }
  730. #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
  731. .type = V4L2_DV_BT_656_1120, \
  732. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
  733. 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
  734. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  735. V4L2_DV_FL_REDUCED_BLANKING) \
  736. }
  737. #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
  738. /* WUXGA resolutions */
  739. #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
  740. .type = V4L2_DV_BT_656_1120, \
  741. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  742. 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
  743. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  744. V4L2_DV_FL_REDUCED_BLANKING) \
  745. }
  746. #define V4L2_DV_BT_DMT_1920X1200P60 { \
  747. .type = V4L2_DV_BT_656_1120, \
  748. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  749. 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
  750. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  751. }
  752. #define V4L2_DV_BT_DMT_1920X1200P75 { \
  753. .type = V4L2_DV_BT_656_1120, \
  754. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  755. 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
  756. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  757. }
  758. #define V4L2_DV_BT_DMT_1920X1200P85 { \
  759. .type = V4L2_DV_BT_656_1120, \
  760. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  761. 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
  762. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  763. }
  764. #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
  765. .type = V4L2_DV_BT_656_1120, \
  766. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  767. 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
  768. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  769. V4L2_DV_FL_REDUCED_BLANKING) \
  770. }
  771. #define V4L2_DV_BT_DMT_1920X1440P60 { \
  772. .type = V4L2_DV_BT_656_1120, \
  773. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
  774. 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
  775. V4L2_DV_BT_STD_DMT, 0) \
  776. }
  777. #define V4L2_DV_BT_DMT_1920X1440P75 { \
  778. .type = V4L2_DV_BT_656_1120, \
  779. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
  780. 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
  781. V4L2_DV_BT_STD_DMT, 0) \
  782. }
  783. #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
  784. .type = V4L2_DV_BT_656_1120, \
  785. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
  786. 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
  787. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  788. V4L2_DV_FL_REDUCED_BLANKING) \
  789. }
  790. #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
  791. .type = V4L2_DV_BT_656_1120, \
  792. V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
  793. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  794. 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
  795. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  796. }
  797. /* WQXGA resolutions */
  798. #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
  799. .type = V4L2_DV_BT_656_1120, \
  800. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
  801. 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
  802. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  803. V4L2_DV_FL_REDUCED_BLANKING) \
  804. }
  805. #define V4L2_DV_BT_DMT_2560X1600P60 { \
  806. .type = V4L2_DV_BT_656_1120, \
  807. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  808. 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
  809. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  810. }
  811. #define V4L2_DV_BT_DMT_2560X1600P75 { \
  812. .type = V4L2_DV_BT_656_1120, \
  813. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  814. 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
  815. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  816. }
  817. #define V4L2_DV_BT_DMT_2560X1600P85 { \
  818. .type = V4L2_DV_BT_656_1120, \
  819. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  820. 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
  821. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  822. }
  823. #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
  824. .type = V4L2_DV_BT_656_1120, \
  825. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
  826. 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
  827. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  828. V4L2_DV_FL_REDUCED_BLANKING) \
  829. }
  830. /* 4K resolutions */
  831. #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
  832. .type = V4L2_DV_BT_656_1120, \
  833. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
  834. 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
  835. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  836. V4L2_DV_FL_REDUCED_BLANKING) \
  837. }
  838. #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
  839. .type = V4L2_DV_BT_656_1120, \
  840. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
  841. 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
  842. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  843. V4L2_DV_FL_REDUCED_BLANKING) \
  844. }
  845. /* SDI timings definitions */
  846. /* SMPTE-125M */
  847. #define V4L2_DV_BT_SDI_720X487I60 { \
  848. .type = V4L2_DV_BT_656_1120, \
  849. V4L2_INIT_BT_TIMINGS(720, 487, 1, \
  850. V4L2_DV_HSYNC_POS_POL, \
  851. 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
  852. V4L2_DV_BT_STD_SDI, \
  853. V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
  854. }
  855. #endif